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ARM: dts: rockchip: initialize rk3066 PLL clock rate

PATCH New Paweł Jarosz 2 participants 2 messages Oct 6, 2016 – Oct 11, 2016

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Paweł Jarosz

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PATCH 1/1 ARM: dts: rockchip: initialize rk3066 PLL clock rate

Initialize PLL rate while kernel init. No other module does than. Clock rates are taken from rk3066 TRM. Assigned values are for 125 degrees celcius operating point.
This gives us performance boost observable for example in mmc transfers.

Signed-off-by Pawe? Jarosz <[email protected]>
---
 arch/arm/boot/dts/rk3066a.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm/boot/dts/rk3066a.dtsi +4 -0
index 0d0dae3..cf215e8 100644
@@ -151,6 +151,10 @@
 
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		assigned-clocks = <&cru PLL_DPLL>, <&cru PLL_APLL>,
+				  <&cru PLL_CPLL>, <&cru PLL_GPLL>;
+		assigned-clock-rates = <533000000>, <600000000>,
+				       <600000000>, <600000000>;
 	};
 
 	timer at 2000e000 {
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#1 lore raw

PATCH 1/1 ARM: dts: rockchip: initialize rk3066 PLL clock rate

Am Donnerstag, 6. Oktober 2016, 21:42:21 CEST schrieb Pawe? Jarosz:

Quoted 15 lines

Initialize PLL rate while kernel init. No other module does than. Clock rates are taken from rk3066 TRM. Assigned values are for 125 degrees celcius operating point.
This gives us performance boost observable for example in mmc transfers.

Signed-off-by Pawe? Jarosz <[email protected]>
---
 arch/arm/boot/dts/rk3066a.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm/boot/dts/rk3066a.dtsi +0 -0
index 0d0dae3..cf215e8 100644

arch/arm/boot/dts/rk3066a.dtsi line 154

Quoted 4 lines
arch/arm/boot/dts/rk3066a.dtsi +1 -0
@@ -151,6 +151,10 @@
 
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		assigned-clocks = <&cru PLL_DPLL>, <&cru PLL_APLL>,

we shouldn't touch the DPLL and APLL at all in this context. They are quite reliant on the underlying voltages and the bootloader might've set other values. Also changing the DDR frequency through the DPLL requires special handling on the DDR side.

arch/arm/boot/dts/rk3066a.dtsi line 155

Quoted 1 line
arch/arm/boot/dts/rk3066a.dtsi +1 -0
+				  <&cru PLL_CPLL>, <&cru PLL_GPLL>;

please also initialize the PERI and BUS clocks (similar to what the rk3288 clk settings do), so that they stay sane, even if we change CPLL and GPLL frequencies.

arch/arm/boot/dts/rk3066a.dtsi line 157

Quoted 2 lines
arch/arm/boot/dts/rk3066a.dtsi +2 -0
+		assigned-clock-rates = <533000000>, <600000000>,
+				       <600000000>, <600000000>;

Also setting both CPLL and GPLL to the same value might be unhelpful to achieve special divided frequencies? Again see rk3288.dtsi where we have a 594 / 400 MHz division. Especially the downstream clocks normally can select between CPLL and GPLL.

Heiko