ppc4xx: Optimize PLB4 arbiter and memory queue settings for PPC 440SP/SPe, PPC405EX and PPC 460EX/GT
PATCH 1/1 ppc4xx: Optimize PLB4 arbiter and memory queue settings for PPC 440SP/SPe, PPC405EX and PPC 460EX/GT
Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors Add register bit definitions for Memory Queue Configuration registers
Signed-off-by Prodyut Hazarika <[email protected]>
--- cpu/ppc4xx/44x_spd_ddr2.c | 27 ++++++++++++++++--- cpu/ppc4xx/cpu_init.c | 16 ++++++++++- include/asm-ppc/ppc4xx-sdram.h | 48 ++++++++++++++++++++++----------- include/ppc440.h | 47 --------------------------------- include/ppc4xx.h | 56 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 126 insertions(+), 68 deletions(-)
cpu/ppc4xx/44x_spd_ddr2.c +23 -4
@@ -2172,6 +2172,11 @@ static void program_memory_queue(unsigned long *dimm_populated,unsigned long i;unsigned long bank_0_populated =0 ;phys_size_t total_size =0 ; +#if defined(CONFIG_440SP ) || defined(CONFIG_440SPE ) || \ + defined(CONFIG_460EX ) || defined(CONFIG_460GT ) || \ + defined(CONFIG_460SX ) +unsigned long val; +#endif /*------------------------------------------------------------------ * Reset the rank_base_address.
@@ -2249,17 +2254,31 @@ static void program_memory_queue(unsigned long *dimm_populated, } } -#if defined(CONFIG_460EX ) || defined(CONFIG_460GT ) +#if defined(CONFIG_440SP ) || defined(CONFIG_440SPE ) || \ + defined(CONFIG_460EX ) || defined(CONFIG_460GT ) || \ + defined(CONFIG_460SX ) +/* -* Enable high bandwidth access on 460EX/GT. -* This should/could probably be done on other -* PPC's too, like 440SPe. +* Enable high bandwidth access * This is currently not used, but with this setup * it is possible to use it later on in e.g. the Linux * EMAC driver for performance gain. */ mtdcr (SDRAM_PLBADDULL ,0x00000000 );/* MQ0_BAUL */ mtdcr (SDRAM_PLBADDUHB ,0x00000008 );/* MQ0_BAUH */ + +/* +* Set optimal value for Memory Queue HB/LL Configuration registers +*/ + + val = (mfdcr (SDRAM_CONF1HB ) |SDRAM_CONF1HB_AAFR |SDRAM_CONF1HB_RPEN |SDRAM_CONF1HB_RFTE ); +mtdcr (SDRAM_CONF1HB , val); + + val = (mfdcr (SDRAM_CONF1LL ) |SDRAM_CONF1LL_AAFR |SDRAM_CONF1LL_RPEN |SDRAM_CONF1LL_RFTE ); +mtdcr (SDRAM_CONF1LL , val); + + val = (mfdcr (SDRAM_CONFPATHB ) |SDRAM_CONFPATHB_TPEN ); +mtdcr (SDRAM_CONFPATHB , val);#endif }
cpu/ppc4xx/cpu_init.c +15 -1
@@ -138,7 +138,9 @@ void reconfigure_pll(u32 new_cpu_freq)void cpu_init_f (void ) { -#if defined(CONFIG_WATCHDOG ) || defined(CONFIG_440GX ) || defined(CONFIG_460EX ) +#if defined(CONFIG_WATCHDOG ) || defined(CONFIG_440GX ) || defined(CONFIG_460EX ) || \ + defined(CONFIG_440SP ) || defined(CONFIG_440SPE ) || defined(CONFIG_405EX ) || \ + defined(CONFIG_460GT ) || defined(CONFIG_460SX )u32 val;#endif
@@ -301,6 +303,18 @@ cpu_init_f (void) val |=0x400 ;mtsdr (SDR0_USB2HOST_CFG , val);#endif /* CONFIG_460EX */ + +#if defined(CONFIG_440SP ) || defined(CONFIG_440SPE ) || \ + defined(CONFIG_460EX ) || defined(CONFIG_460GT ) || \ + defined(CONFIG_405EX ) || defined(CONFIG_460SX ) +/* +* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read +*/ + val = (mfdcr (plb0_acr) & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; +mtdcr (plb0_acr, val); + val = (mfdcr (plb1_acr) & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; +mtdcr (plb1_acr, val); +#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ }/*
include/asm-ppc/ppc4xx-sdram.h +33 -17
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include/ppc440.h +0 -47
53 lines not on this page · raw message
include/ppc4xx.h +56 -0
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Signature · 1 line
1.5.5