WM8350 support
Subsystems (3)
cover WM8350 support
These patches against the regulator tree add initial support for the WM8350, a multi-function device with several subsystems targetted at embedded systems. This series adds a core driver providing device acess under drivers/mfd and support for the PMIC functionality of the device via the regulator API. Due to their use in the core some definitions for other parts of the device are also included - drivers for these will follow.
All the WM8350 drivers submitted here were originally written by Liam Girdwood with some updates from me for submission to mainline.
Samuel, as with the WM8400 are you OK with merging this via the regulator tree?
The following changes since commit fcbd54dd718e6741b05f8e5b08cbc75548acf0e4:
Mark Brown (1):
regulator: Add WM8400 regulator support
are available in the git repository at:
git://opensource.wolfsonmicro.com/linux-2.6-audioplus for-lrg
Mark Brown (13):
mfd: Add WM8350 audio register definitions
mfd: Add WM8350 GPIO register definitions
mfd: Add WM8350 PMIC register definitions
mfd: Add WM8350 PMU register definitions
mfd: Add WM8350 comparator register definitions
mfd: Add WM8350 RTC register definitions
mfd: Add WM8350 watchdog register definitions
mfd: Core support for the WM8350 AudioPlus PMIC
mfd: Add I2C control support for WM8350
mfd: Add GPIO pin configuration support for WM8350
mfd: Add initialisation callback for WM8350
mfd: Add WM8350 interrupt support
regulator: Add WM8350 regulator support
drivers/mfd/Kconfig | 58 ++ drivers/mfd/Makefile | 3 + drivers/mfd/wm8350-core.c | 1239 ++++++++++++++++++++++++++++ drivers/mfd/wm8350-gpio.c | 222 +++++ drivers/mfd/wm8350-i2c.c | 120 +++ drivers/mfd/wm8350-regmap.c | 1323 ++++++++++++++++++++++++++++++ drivers/regulator/Kconfig | 10 + drivers/regulator/Makefile | 1 + drivers/regulator/wm8350-regulator.c | 1430 +++++++++++++++++++++++++++++++++ include/linux/mfd/wm8350/audio.h | 592 ++++++++++++++ include/linux/mfd/wm8350/comparator.h | 167 ++++ include/linux/mfd/wm8350/core.h | 621 ++++++++++++++ include/linux/mfd/wm8350/gpio.h | 336 ++++++++ include/linux/mfd/wm8350/pmic.h | 741 +++++++++++++++++ include/linux/mfd/wm8350/rtc.h | 260 ++++++ include/linux/mfd/wm8350/supply.h | 105 +++ include/linux/mfd/wm8350/wdt.h | 22 + 17 files changed, 7250 insertions(+), 0 deletions(-) create mode 100644 drivers/mfd/wm8350-core.c create mode 100644 drivers/mfd/wm8350-gpio.c create mode 100644 drivers/mfd/wm8350-i2c.c create mode 100644 drivers/mfd/wm8350-regmap.c create mode 100644 drivers/regulator/wm8350-regulator.c create mode 100644 include/linux/mfd/wm8350/audio.h create mode 100644 include/linux/mfd/wm8350/comparator.h create mode 100644 include/linux/mfd/wm8350/core.h create mode 100644 include/linux/mfd/wm8350/gpio.h create mode 100644 include/linux/mfd/wm8350/pmic.h create mode 100644 include/linux/mfd/wm8350/rtc.h create mode 100644 include/linux/mfd/wm8350/supply.h create mode 100644 include/linux/mfd/wm8350/wdt.h
PATCH 1/13 mfd: Add WM8350 audio register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/audio.h | 592 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 592 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/audio.h
include/linux/mfd/wm8350/audio.h new file +592 -0
@@ -0,0 +1,592 @@ +/* +* audio.h -- Audio Driver for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +*/ + +#ifndef __LINUX_MFD_WM8350_AUDIO_H_ +#define __LINUX_MFD_WM8350_AUDIO_H_ + +#define WM8350_CLOCK_CONTROL_1 0x28 +#define WM8350_CLOCK_CONTROL_2 0x29 +#define WM8350_FLL_CONTROL_1 0x2A +#define WM8350_FLL_CONTROL_2 0x2B +#define WM8350_FLL_CONTROL_3 0x2C +#define WM8350_FLL_CONTROL_4 0x2D +#define WM8350_DAC_CONTROL 0x30 +#define WM8350_DAC_DIGITAL_VOLUME_L 0x32 +#define WM8350_DAC_DIGITAL_VOLUME_R 0x33 +#define WM8350_DAC_LR_RATE 0x35 +#define WM8350_DAC_CLOCK_CONTROL 0x36 +#define WM8350_DAC_MUTE 0x3A +#define WM8350_DAC_MUTE_VOLUME 0x3B +#define WM8350_DAC_SIDE 0x3C +#define WM8350_ADC_CONTROL 0x40 +#define WM8350_ADC_DIGITAL_VOLUME_L 0x42 +#define WM8350_ADC_DIGITAL_VOLUME_R 0x43 +#define WM8350_ADC_DIVIDER 0x44 +#define WM8350_ADC_LR_RATE 0x46 +#define WM8350_INPUT_CONTROL 0x48 +#define WM8350_IN3_INPUT_CONTROL 0x49 +#define WM8350_MIC_BIAS_CONTROL 0x4A +#define WM8350_OUTPUT_CONTROL 0x4C +#define WM8350_JACK_DETECT 0x4D +#define WM8350_ANTI_POP_CONTROL 0x4E +#define WM8350_LEFT_INPUT_VOLUME 0x50 +#define WM8350_RIGHT_INPUT_VOLUME 0x51 +#define WM8350_LEFT_MIXER_CONTROL 0x58 +#define WM8350_RIGHT_MIXER_CONTROL 0x59 +#define WM8350_OUT3_MIXER_CONTROL 0x5C +#define WM8350_OUT4_MIXER_CONTROL 0x5D +#define WM8350_OUTPUT_LEFT_MIXER_VOLUME 0x60 +#define WM8350_OUTPUT_RIGHT_MIXER_VOLUME 0x61 +#define WM8350_INPUT_MIXER_VOLUME_L 0x62 +#define WM8350_INPUT_MIXER_VOLUME_R 0x63 +#define WM8350_INPUT_MIXER_VOLUME 0x64 +#define WM8350_LOUT1_VOLUME 0x68 +#define WM8350_ROUT1_VOLUME 0x69 +#define WM8350_LOUT2_VOLUME 0x6A +#define WM8350_ROUT2_VOLUME 0x6B +#define WM8350_BEEP_VOLUME 0x6F +#define WM8350_AI_FORMATING 0x70 +#define WM8350_ADC_DAC_COMP 0x71 +#define WM8350_AI_ADC_CONTROL 0x72 +#define WM8350_AI_DAC_CONTROL 0x73 +#define WM8350_AIF_TEST 0x74 +#define WM8350_JACK_PIN_STATUS 0xE7 + +/* Bit values for R08 (0x08) */ +#define WM8350_CODEC_ISEL_1_5 0/* x1.5 */ +#define WM8350_CODEC_ISEL_1_0 1/* x1.0 */ +#define WM8350_CODEC_ISEL_0_75 2/* x0.75 */ +#define WM8350_CODEC_ISEL_0_5 3/* x0.5 */ + +#define WM8350_VMID_OFF 0 +#define WM8350_VMID_500K 1 +#define WM8350_VMID_100K 2 +#define WM8350_VMID_10K 3 + +/* +* R40 (0x28) - Clock Control 1 +*/ +#define WM8350_TOCLK_RATE 0x4000 +#define WM8350_MCLK_SEL 0x0800 +#define WM8350_MCLK_DIV_MASK 0x0100 +#define WM8350_BCLK_DIV_MASK 0x00F0 +#define WM8350_OPCLK_DIV_MASK 0x0007 + +/* +* R41 (0x29) - Clock Control 2 +*/ +#define WM8350_LRC_ADC_SEL 0x8000 +#define WM8350_MCLK_DIR 0x0001 + +/* +* R42 (0x2A) - FLL Control 1 +*/ +#define WM8350_FLL_DITHER_WIDTH_MASK 0x3000 +#define WM8350_FLL_DITHER_HP 0x0800 +#define WM8350_FLL_OUTDIV_MASK 0x0700 +#define WM8350_FLL_RSP_RATE_MASK 0x00F0 +#define WM8350_FLL_RATE_MASK 0x0007 + +/* +* R43 (0x2B) - FLL Control 2 +*/ +#define WM8350_FLL_RATIO_MASK 0xF800 +#define WM8350_FLL_N_MASK 0x03FF + +/* +* R44 (0x2C) - FLL Control 3 +*/ +#define WM8350_FLL_K_MASK 0xFFFF + +/* +* R45 (0x2D) - FLL Control 4 +*/ +#define WM8350_FLL_FRAC 0x0020 +#define WM8350_FLL_SLOW_LOCK_REF 0x0010 +#define WM8350_FLL_CLK_SRC_MASK 0x0003 + +/* +* R48 (0x30) - DAC Control +*/ +#define WM8350_DAC_MONO 0x2000 +#define WM8350_AIF_LRCLKRATE 0x1000 +#define WM8350_DEEMP_MASK 0x0030 +#define WM8350_DACL_DATINV 0x0002 +#define WM8350_DACR_DATINV 0x0001 + +/* +* R50 (0x32) - DAC Digital Volume L +*/ +#define WM8350_DAC_VU 0x0100 +#define WM8350_DACL_VOL_MASK 0x00FF + +/* +* R51 (0x33) - DAC Digital Volume R +*/ +#define WM8350_DAC_VU 0x0100 +#define WM8350_DACR_VOL_MASK 0x00FF + +/* +* R53 (0x35) - DAC LR Rate +*/ +#define WM8350_DACLRC_ENA 0x0800 +#define WM8350_DACLRC_RATE_MASK 0x07FF + +/* +* R54 (0x36) - DAC Clock Control +*/ +#define WM8350_DACCLK_POL 0x0010 +#define WM8350_DAC_CLKDIV_MASK 0x0007 + +/* +* R58 (0x3A) - DAC Mute +*/ +#define WM8350_DAC_MUTE_ENA 0x4000 + +/* +* R59 (0x3B) - DAC Mute Volume +*/ +#define WM8350_DAC_MUTEMODE 0x4000 +#define WM8350_DAC_MUTERATE 0x2000 +#define WM8350_DAC_SB_FILT 0x1000 + +/* +* R60 (0x3C) - DAC Side +*/ +#define WM8350_ADC_TO_DACL_MASK 0x3000 +#define WM8350_ADC_TO_DACR_MASK 0x0C00 + +/* +* R64 (0x40) - ADC Control +*/ +#define WM8350_ADC_HPF_CUT_MASK 0x0300 +#define WM8350_ADCL_DATINV 0x0002 +#define WM8350_ADCR_DATINV 0x0001 + +/* +* R66 (0x42) - ADC Digital Volume L +*/ +#define WM8350_ADC_VU 0x0100 +#define WM8350_ADCL_VOL_MASK 0x00FF + +/* +* R67 (0x43) - ADC Digital Volume R +*/ +#define WM8350_ADC_VU 0x0100 +#define WM8350_ADCR_VOL_MASK 0x00FF + +/* +* R68 (0x44) - ADC Divider +*/ +#define WM8350_ADCL_DAC_SVOL_MASK 0x0F00 +#define WM8350_ADCR_DAC_SVOL_MASK 0x00F0 +#define WM8350_ADCCLK_POL 0x0008 +#define WM8350_ADC_CLKDIV_MASK 0x0007 + +/* +* R70 (0x46) - ADC LR Rate +*/ +#define WM8350_ADCLRC_ENA 0x0800 +#define WM8350_ADCLRC_RATE_MASK 0x07FF + +/* +* R72 (0x48) - Input Control +*/ +#define WM8350_IN2R_ENA 0x0400 +#define WM8350_IN1RN_ENA 0x0200 +#define WM8350_IN1RP_ENA 0x0100 +#define WM8350_IN2L_ENA 0x0004 +#define WM8350_IN1LN_ENA 0x0002 +#define WM8350_IN1LP_ENA 0x0001 + +/* +* R73 (0x49) - IN3 Input Control +*/ +#define WM8350_IN3R_SHORT 0x4000 +#define WM8350_IN3L_SHORT 0x0040 + +/* +* R74 (0x4A) - Mic Bias Control +*/ +#define WM8350_MICBSEL 0x4000 +#define WM8350_MCDTHR_MASK 0x001C +#define WM8350_MCDSCTHR_MASK 0x0003 + +/* +* R76 (0x4C) - Output Control +*/ +#define WM8350_OUT4_VROI 0x0800 +#define WM8350_OUT3_VROI 0x0400 +#define WM8350_OUT2_VROI 0x0200 +#define WM8350_OUT1_VROI 0x0100 +#define WM8350_OUT2_FB 0x0004 +#define WM8350_OUT1_FB 0x0001 + +/* +* R77 (0x4D) - Jack Detect +*/ +#define WM8350_JDL_ENA 0x8000 +#define WM8350_JDR_ENA 0x4000 + +/* +* R78 (0x4E) - Anti Pop Control +*/ +#define WM8350_ANTI_POP_MASK 0x0300 +#define WM8350_DIS_OP_LN4_MASK 0x00C0 +#define WM8350_DIS_OP_LN3_MASK 0x0030 +#define WM8350_DIS_OP_OUT2_MASK 0x000C +#define WM8350_DIS_OP_OUT1_MASK 0x0003 + +/* +* R80 (0x50) - Left Input Volume +*/ +#define WM8350_INL_MUTE 0x4000 +#define WM8350_INL_ZC 0x2000 +#define WM8350_IN_VU 0x0100 +#define WM8350_INL_VOL_MASK 0x00FC + +/* +* R81 (0x51) - Right Input Volume +*/ +#define WM8350_INR_MUTE 0x4000 +#define WM8350_INR_ZC 0x2000 +#define WM8350_IN_VU 0x0100 +#define WM8350_INR_VOL_MASK 0x00FC + +/* +* R88 (0x58) - Left Mixer Control +*/ +#define WM8350_DACR_TO_MIXOUTL 0x1000 +#define WM8350_DACL_TO_MIXOUTL 0x0800 +#define WM8350_IN3L_TO_MIXOUTL 0x0004 +#define WM8350_INR_TO_MIXOUTL 0x0002 +#define WM8350_INL_TO_MIXOUTL 0x0001 + +/* +* R89 (0x59) - Right Mixer Control +*/ +#define WM8350_DACR_TO_MIXOUTR 0x1000 +#define WM8350_DACL_TO_MIXOUTR 0x0800 +#define WM8350_IN3R_TO_MIXOUTR 0x0008 +#define WM8350_INR_TO_MIXOUTR 0x0002 +#define WM8350_INL_TO_MIXOUTR 0x0001 + +/* +* R92 (0x5C) - OUT3 Mixer Control +*/ +#define WM8350_DACL_TO_OUT3 0x0800 +#define WM8350_MIXINL_TO_OUT3 0x0100 +#define WM8350_OUT4_TO_OUT3 0x0008 +#define WM8350_MIXOUTL_TO_OUT3 0x0001 + +/* +* R93 (0x5D) - OUT4 Mixer Control +*/ +#define WM8350_DACR_TO_OUT4 0x1000 +#define WM8350_DACL_TO_OUT4 0x0800 +#define WM8350_OUT4_ATTN 0x0400 +#define WM8350_MIXINR_TO_OUT4 0x0200 +#define WM8350_OUT3_TO_OUT4 0x0004 +#define WM8350_MIXOUTR_TO_OUT4 0x0002 +#define WM8350_MIXOUTL_TO_OUT4 0x0001 + +/* +* R96 (0x60) - Output Left Mixer Volume +*/ +#define WM8350_IN3L_MIXOUTL_VOL_MASK 0x0E00 +#define WM8350_IN3L_MIXOUTL_VOL_SHIFT 9 +#define WM8350_INR_MIXOUTL_VOL_MASK 0x00E0 +#define WM8350_INR_MIXOUTL_VOL_SHIFT 5 +#define WM8350_INL_MIXOUTL_VOL_MASK 0x000E +#define WM8350_INL_MIXOUTL_VOL_SHIFT 1 + +/* Bit values for R96 (0x60) */ +#define WM8350_IN3L_MIXOUTL_VOL_OFF 0 +#define WM8350_IN3L_MIXOUTL_VOL_M12DB 1 +#define WM8350_IN3L_MIXOUTL_VOL_M9DB 2 +#define WM8350_IN3L_MIXOUTL_VOL_M6DB 3 +#define WM8350_IN3L_MIXOUTL_VOL_M3DB 4 +#define WM8350_IN3L_MIXOUTL_VOL_0DB 5 +#define WM8350_IN3L_MIXOUTL_VOL_3DB 6 +#define WM8350_IN3L_MIXOUTL_VOL_6DB 7 + +#define WM8350_INR_MIXOUTL_VOL_OFF 0 +#define WM8350_INR_MIXOUTL_VOL_M12DB 1 +#define WM8350_INR_MIXOUTL_VOL_M9DB 2 +#define WM8350_INR_MIXOUTL_VOL_M6DB 3 +#define WM8350_INR_MIXOUTL_VOL_M3DB 4 +#define WM8350_INR_MIXOUTL_VOL_0DB 5 +#define WM8350_INR_MIXOUTL_VOL_3DB 6 +#define WM8350_INR_MIXOUTL_VOL_6DB 7 + +#define WM8350_INL_MIXOUTL_VOL_OFF 0 +#define WM8350_INL_MIXOUTL_VOL_M12DB 1 +#define WM8350_INL_MIXOUTL_VOL_M9DB 2 +#define WM8350_INL_MIXOUTL_VOL_M6DB 3 +#define WM8350_INL_MIXOUTL_VOL_M3DB 4 +#define WM8350_INL_MIXOUTL_VOL_0DB 5 +#define WM8350_INL_MIXOUTL_VOL_3DB 6 +#define WM8350_INL_MIXOUTL_VOL_6DB 7 + +/* +* R97 (0x61) - Output Right Mixer Volume +*/ +#define WM8350_IN3R_MIXOUTR_VOL_MASK 0xE000 +#define WM8350_IN3R_MIXOUTR_VOL_SHIFT 13 +#define WM8350_INR_MIXOUTR_VOL_MASK 0x00E0 +#define WM8350_INR_MIXOUTR_VOL_SHIFT 5 +#define WM8350_INL_MIXOUTR_VOL_MASK 0x000E +#define WM8350_INL_MIXOUTR_VOL_SHIFT 1 + +/* Bit values for R96 (0x60) */ +#define WM8350_IN3R_MIXOUTR_VOL_OFF 0 +#define WM8350_IN3R_MIXOUTR_VOL_M12DB 1 +#define WM8350_IN3R_MIXOUTR_VOL_M9DB 2 +#define WM8350_IN3R_MIXOUTR_VOL_M6DB 3 +#define WM8350_IN3R_MIXOUTR_VOL_M3DB 4 +#define WM8350_IN3R_MIXOUTR_VOL_0DB 5 +#define WM8350_IN3R_MIXOUTR_VOL_3DB 6 +#define WM8350_IN3R_MIXOUTR_VOL_6DB 7 + +#define WM8350_INR_MIXOUTR_VOL_OFF 0 +#define WM8350_INR_MIXOUTR_VOL_M12DB 1 +#define WM8350_INR_MIXOUTR_VOL_M9DB 2 +#define WM8350_INR_MIXOUTR_VOL_M6DB 3 +#define WM8350_INR_MIXOUTR_VOL_M3DB 4 +#define WM8350_INR_MIXOUTR_VOL_0DB 5 +#define WM8350_INR_MIXOUTR_VOL_3DB 6 +#define WM8350_INR_MIXOUTR_VOL_6DB 7 + +#define WM8350_INL_MIXOUTR_VOL_OFF 0 +#define WM8350_INL_MIXOUTR_VOL_M12DB 1 +#define WM8350_INL_MIXOUTR_VOL_M9DB 2 +#define WM8350_INL_MIXOUTR_VOL_M6DB 3 +#define WM8350_INL_MIXOUTR_VOL_M3DB 4 +#define WM8350_INL_MIXOUTR_VOL_0DB 5 +#define WM8350_INL_MIXOUTR_VOL_3DB 6 +#define WM8350_INL_MIXOUTR_VOL_6DB 7 + +/* +* R98 (0x62) - Input Mixer Volume L +*/ +#define WM8350_IN3L_MIXINL_VOL_MASK 0x0E00 +#define WM8350_IN2L_MIXINL_VOL_MASK 0x000E +#define WM8350_INL_MIXINL_VOL 0x0001 + +/* +* R99 (0x63) - Input Mixer Volume R +*/ +#define WM8350_IN3R_MIXINR_VOL_MASK 0xE000 +#define WM8350_IN2R_MIXINR_VOL_MASK 0x00E0 +#define WM8350_INR_MIXINR_VOL 0x0001 + +/* +* R100 (0x64) - Input Mixer Volume +*/ +#define WM8350_OUT4_MIXIN_DST 0x8000 +#define WM8350_OUT4_MIXIN_VOL_MASK 0x000E + +/* +* R104 (0x68) - LOUT1 Volume +*/ +#define WM8350_OUT1L_MUTE 0x4000 +#define WM8350_OUT1L_ZC 0x2000 +#define WM8350_OUT1_VU 0x0100 +#define WM8350_OUT1L_VOL_MASK 0x00FC +#define WM8350_OUT1L_VOL_SHIFT 2 + +/* +* R105 (0x69) - ROUT1 Volume +*/ +#define WM8350_OUT1R_MUTE 0x4000 +#define WM8350_OUT1R_ZC 0x2000 +#define WM8350_OUT1_VU 0x0100 +#define WM8350_OUT1R_VOL_MASK 0x00FC +#define WM8350_OUT1R_VOL_SHIFT 2 + +/* +* R106 (0x6A) - LOUT2 Volume +*/ +#define WM8350_OUT2L_MUTE 0x4000 +#define WM8350_OUT2L_ZC 0x2000 +#define WM8350_OUT2_VU 0x0100 +#define WM8350_OUT2L_VOL_MASK 0x00FC + +/* +* R107 (0x6B) - ROUT2 Volume +*/ +#define WM8350_OUT2R_MUTE 0x4000 +#define WM8350_OUT2R_ZC 0x2000 +#define WM8350_OUT2R_INV 0x0400 +#define WM8350_OUT2R_INV_MUTE 0x0200 +#define WM8350_OUT2_VU 0x0100 +#define WM8350_OUT2R_VOL_MASK 0x00FC + +/* +* R111 (0x6F) - BEEP Volume +*/ +#define WM8350_IN3R_OUT2R_VOL_MASK 0x00E0 + +/* +* R112 (0x70) - AI Formating +*/ +#define WM8350_AIF_BCLK_INV 0x8000 +#define WM8350_AIF_TRI 0x2000 +#define WM8350_AIF_LRCLK_INV 0x1000 +#define WM8350_AIF_WL_MASK 0x0C00 +#define WM8350_AIF_FMT_MASK 0x0300 + +/* +* R113 (0x71) - ADC DAC COMP +*/ +#define WM8350_DAC_COMP 0x0080 +#define WM8350_DAC_COMPMODE 0x0040 +#define WM8350_ADC_COMP 0x0020 +#define WM8350_ADC_COMPMODE 0x0010 +#define WM8350_LOOPBACK 0x0001 + +/* +* R114 (0x72) - AI ADC Control +*/ +#define WM8350_AIFADC_PD 0x0080 +#define WM8350_AIFADCL_SRC 0x0040 +#define WM8350_AIFADCR_SRC 0x0020 +#define WM8350_AIFADC_TDM_CHAN 0x0010 +#define WM8350_AIFADC_TDM 0x0008 + +/* +* R115 (0x73) - AI DAC Control +*/ +#define WM8350_BCLK_MSTR 0x4000 +#define WM8350_AIFDAC_PD 0x0080 +#define WM8350_DACL_SRC 0x0040 +#define WM8350_DACR_SRC 0x0020 +#define WM8350_AIFDAC_TDM_CHAN 0x0010 +#define WM8350_AIFDAC_TDM 0x0008 +#define WM8350_DAC_BOOST_MASK 0x0003 + +/* +* R116 (0x74) - AIF Test +*/ +#define WM8350_CODEC_BYP 0x4000 +#define WM8350_AIFADC_WR_TST 0x2000 +#define WM8350_AIFADC_RD_TST 0x1000 +#define WM8350_AIFDAC_WR_TST 0x0800 +#define WM8350_AIFDAC_RD_TST 0x0400 +#define WM8350_AIFADC_ASYN 0x0020 +#define WM8350_AIFDAC_ASYN 0x0010 + +/* +* R231 (0xE7) - Jack Status +*/ +#define WM8350_JACK_R_LVL 0x0400 + +/* +* WM8350 Platform setup +*/ +#define WM8350_S_CURVE_NONE 0x0 +#define WM8350_S_CURVE_FAST 0x1 +#define WM8350_S_CURVE_MEDIUM 0x2 +#define WM8350_S_CURVE_SLOW 0x3 + +#define WM8350_DISCHARGE_OFF 0x0 +#define WM8350_DISCHARGE_FAST 0x1 +#define WM8350_DISCHARGE_MEDIUM 0x2 +#define WM8350_DISCHARGE_SLOW 0x3 + +#define WM8350_TIE_OFF_500R 0x0 +#define WM8350_TIE_OFF_30K 0x1 + +/* +* Clock sources & directions +*/ +#define WM8350_SYSCLK 0 + +#define WM8350_MCLK_SEL_PLL_MCLK 0 +#define WM8350_MCLK_SEL_PLL_DAC 1 +#define WM8350_MCLK_SEL_PLL_ADC 2 +#define WM8350_MCLK_SEL_PLL_32K 3 +#define WM8350_MCLK_SEL_MCLK 5 + +#define WM8350_MCLK_DIR_OUT 0 +#define WM8350_MCLK_DIR_IN 1 + +/* clock divider id's */ +#define WM8350_ADC_CLKDIV 0 +#define WM8350_DAC_CLKDIV 1 +#define WM8350_BCLK_CLKDIV 2 +#define WM8350_OPCLK_CLKDIV 3 +#define WM8350_TO_CLKDIV 4 +#define WM8350_SYS_CLKDIV 5 +#define WM8350_DACLR_CLKDIV 6 +#define WM8350_ADCLR_CLKDIV 7 + +/* ADC clock dividers */ +#define WM8350_ADCDIV_1 0x0 +#define WM8350_ADCDIV_1_5 0x1 +#define WM8350_ADCDIV_2 0x2 +#define WM8350_ADCDIV_3 0x3 +#define WM8350_ADCDIV_4 0x4 +#define WM8350_ADCDIV_5_5 0x5 +#define WM8350_ADCDIV_6 0x6 + +/* ADC clock dividers */ +#define WM8350_DACDIV_1 0x0 +#define WM8350_DACDIV_1_5 0x1 +#define WM8350_DACDIV_2 0x2 +#define WM8350_DACDIV_3 0x3 +#define WM8350_DACDIV_4 0x4 +#define WM8350_DACDIV_5_5 0x5 +#define WM8350_DACDIV_6 0x6 + +/* BCLK clock dividers */ +#define WM8350_BCLK_DIV_1 (0x0 << 4) +#define WM8350_BCLK_DIV_1_5 (0x1 << 4) +#define WM8350_BCLK_DIV_2 (0x2 << 4) +#define WM8350_BCLK_DIV_3 (0x3 << 4) +#define WM8350_BCLK_DIV_4 (0x4 << 4) +#define WM8350_BCLK_DIV_5_5 (0x5 << 4) +#define WM8350_BCLK_DIV_6 (0x6 << 4) +#define WM8350_BCLK_DIV_8 (0x7 << 4) +#define WM8350_BCLK_DIV_11 (0x8 << 4) +#define WM8350_BCLK_DIV_12 (0x9 << 4) +#define WM8350_BCLK_DIV_16 (0xa << 4) +#define WM8350_BCLK_DIV_22 (0xb << 4) +#define WM8350_BCLK_DIV_24 (0xc << 4) +#define WM8350_BCLK_DIV_32 (0xd << 4) +#define WM8350_BCLK_DIV_44 (0xe << 4) +#define WM8350_BCLK_DIV_48 (0xf << 4) + +/* Sys (MCLK) clock dividers */ +#define WM8350_MCLK_DIV_1 (0x0 << 8) +#define WM8350_MCLK_DIV_2 (0x1 << 8) + +/* OP clock dividers */ +#define WM8350_OPCLK_DIV_1 0x0 +#define WM8350_OPCLK_DIV_2 0x1 +#define WM8350_OPCLK_DIV_3 0x2 +#define WM8350_OPCLK_DIV_4 0x3 +#define WM8350_OPCLK_DIV_5_5 0x4 +#define WM8350_OPCLK_DIV_6 0x5 + +/* DAI ID */ +#define WM8350_HIFI_DAI 0 + +/* +* Audio interrupts. +*/ +#define WM8350_IRQ_CODEC_JCK_DET_L 39 +#define WM8350_IRQ_CODEC_JCK_DET_R 40 +#define WM8350_IRQ_CODEC_MICSCD 41 +#define WM8350_IRQ_CODEC_MICD 42 + +#endif
Signature · 1 line
1.5.6.5
PATCH 2/13 mfd: Add WM8350 GPIO register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/gpio.h | 326 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 326 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/gpio.h
include/linux/mfd/wm8350/gpio.h new file +326 -0
@@ -0,0 +1,326 @@ +/* +* gpio.h -- GPIO Driver for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +*/ + +#ifndef __LINUX_MFD_WM8350_GPIO_H_ +#define __LINUX_MFD_WM8350_GPIO_H_ + +/* +* GPIO Registers. +*/ +#define WM8350_GPIO_DEBOUNCE 0x80 +#define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81 +#define WM8350_GPIO_PULL_DOWN_CONTROL 0x82 +#define WM8350_GPIO_INT_MODE 0x83 +#define WM8350_GPIO_CONTROL 0x85 +#define WM8350_GPIO_CONFIGURATION_I_O 0x86 +#define WM8350_GPIO_PIN_POLARITY_TYPE 0x87 +#define WM8350_GPIO_FUNCTION_SELECT_1 0x8C +#define WM8350_GPIO_FUNCTION_SELECT_2 0x8D +#define WM8350_GPIO_FUNCTION_SELECT_3 0x8E +#define WM8350_GPIO_FUNCTION_SELECT_4 0x8F + +/* +* GPIO Functions +*/ +#define WM8350_GPIO0_GPIO_IN 0x0 +#define WM8350_GPIO0_GPIO_OUT 0x0 +#define WM8350_GPIO0_PWR_ON_IN 0x1 +#define WM8350_GPIO0_PWR_ON_OUT 0x1 +#define WM8350_GPIO0_LDO_EN_IN 0x2 +#define WM8350_GPIO0_VRTC_OUT 0x2 +#define WM8350_GPIO0_LPWR1_IN 0x3 +#define WM8350_GPIO0_POR_B_OUT 0x3 + +#define WM8350_GPIO1_GPIO_IN 0x0 +#define WM8350_GPIO1_GPIO_OUT 0x0 +#define WM8350_GPIO1_PWR_ON_IN 0x1 +#define WM8350_GPIO1_DO_CONF_OUT 0x1 +#define WM8350_GPIO1_LDO_EN_IN 0x2 +#define WM8350_GPIO1_RESET_OUT 0x2 +#define WM8350_GPIO1_LPWR2_IN 0x3 +#define WM8350_GPIO1_MEMRST_OUT 0x3 + +#define WM8350_GPIO2_GPIO_IN 0x0 +#define WM8350_GPIO2_GPIO_OUT 0x0 +#define WM8350_GPIO2_PWR_ON_IN 0x1 +#define WM8350_GPIO2_PWR_ON_OUT 0x1 +#define WM8350_GPIO2_WAKE_UP_IN 0x2 +#define WM8350_GPIO2_VRTC_OUT 0x2 +#define WM8350_GPIO2_32KHZ_IN 0x3 +#define WM8350_GPIO2_32KHZ_OUT 0x3 + +#define WM8350_GPIO3_GPIO_IN 0x0 +#define WM8350_GPIO3_GPIO_OUT 0x0 +#define WM8350_GPIO3_PWR_ON_IN 0x1 +#define WM8350_GPIO3_P_CLK_OUT 0x1 +#define WM8350_GPIO3_LDO_EN_IN 0x2 +#define WM8350_GPIO3_VRTC_OUT 0x2 +#define WM8350_GPIO3_PWR_OFF_IN 0x3 +#define WM8350_GPIO3_32KHZ_OUT 0x3 + +#define WM8350_GPIO4_GPIO_IN 0x0 +#define WM8350_GPIO4_GPIO_OUT 0x0 +#define WM8350_GPIO4_MR_IN 0x1 +#define WM8350_GPIO4_MEM_RST_OUT 0x1 +#define WM8350_GPIO4_FLASH_IN 0x2 +#define WM8350_GPIO4_ADA_OUT 0x2 +#define WM8350_GPIO4_HIBERNATE_IN 0x3 +#define WM8350_GPIO4_FLASH_OUT 0x3 +#define WM8350_GPIO4_MICDET_OUT 0x4 +#define WM8350_GPIO4_MICSHT_OUT 0x5 + +#define WM8350_GPIO5_GPIO_IN 0x0 +#define WM8350_GPIO5_GPIO_OUT 0x0 +#define WM8350_GPIO5_LPWR1_IN 0x1 +#define WM8350_GPIO5_P_CLK_OUT 0x1 +#define WM8350_GPIO5_ADCLRCLK_IN 0x2 +#define WM8350_GPIO5_ADCLRCLK_OUT 0x2 +#define WM8350_GPIO5_HIBERNATE_IN 0x3 +#define WM8350_GPIO5_32KHZ_OUT 0x3 +#define WM8350_GPIO5_MICDET_OUT 0x4 +#define WM8350_GPIO5_MICSHT_OUT 0x5 +#define WM8350_GPIO5_ADA_OUT 0x6 +#define WM8350_GPIO5_OPCLK_OUT 0x7 + +#define WM8350_GPIO6_GPIO_IN 0x0 +#define WM8350_GPIO6_GPIO_OUT 0x0 +#define WM8350_GPIO6_LPWR2_IN 0x1 +#define WM8350_GPIO6_MEMRST_OUT 0x1 +#define WM8350_GPIO6_FLASH_IN 0x2 +#define WM8350_GPIO6_ADA_OUT 0x2 +#define WM8350_GPIO6_HIBERNATE_IN 0x3 +#define WM8350_GPIO6_RTC_OUT 0x3 +#define WM8350_GPIO6_MICDET_OUT 0x4 +#define WM8350_GPIO6_MICSHT_OUT 0x5 +#define WM8350_GPIO6_ADCLRCLKB_OUT 0x6 +#define WM8350_GPIO6_SDOUT_OUT 0x7 + +#define WM8350_GPIO7_GPIO_IN 0x0 +#define WM8350_GPIO7_GPIO_OUT 0x0 +#define WM8350_GPIO7_LPWR3_IN 0x1 +#define WM8350_GPIO7_P_CLK_OUT 0x1 +#define WM8350_GPIO7_MASK_IN 0x2 +#define WM8350_GPIO7_VCC_FAULT_OUT 0x2 +#define WM8350_GPIO7_HIBERNATE_IN 0x3 +#define WM8350_GPIO7_BATT_FAULT_OUT 0x3 +#define WM8350_GPIO7_MICDET_OUT 0x4 +#define WM8350_GPIO7_MICSHT_OUT 0x5 +#define WM8350_GPIO7_ADA_OUT 0x6 +#define WM8350_GPIO7_CSB_IN 0x7 + +#define WM8350_GPIO8_GPIO_IN 0x0 +#define WM8350_GPIO8_GPIO_OUT 0x0 +#define WM8350_GPIO8_MR_IN 0x1 +#define WM8350_GPIO8_VCC_FAULT_OUT 0x1 +#define WM8350_GPIO8_ADCBCLK_IN 0x2 +#define WM8350_GPIO8_ADCBCLK_OUT 0x2 +#define WM8350_GPIO8_PWR_OFF_IN 0x3 +#define WM8350_GPIO8_BATT_FAULT_OUT 0x3 +#define WM8350_GPIO8_ALTSCL_IN 0xf + +#define WM8350_GPIO9_GPIO_IN 0x0 +#define WM8350_GPIO9_GPIO_OUT 0x0 +#define WM8350_GPIO9_HEARTBEAT_IN 0x1 +#define WM8350_GPIO9_VCC_FAULT_OUT 0x1 +#define WM8350_GPIO9_MASK_IN 0x2 +#define WM8350_GPIO9_LINE_GT_BATT_OUT 0x2 +#define WM8350_GPIO9_PWR_OFF_IN 0x3 +#define WM8350_GPIO9_BATT_FAULT_OUT 0x3 +#define WM8350_GPIO9_ALTSDA_OUT 0xf + +#define WM8350_GPIO10_GPIO_IN 0x0 +#define WM8350_GPIO10_GPIO_OUT 0x0 +#define WM8350_GPIO10_ISINKC_OUT 0x1 +#define WM8350_GPIO10_PWR_OFF_IN 0x2 +#define WM8350_GPIO10_LINE_GT_BATT_OUT 0x2 +#define WM8350_GPIO10_CHD_IND_IN 0x3 + +#define WM8350_GPIO11_GPIO_IN 0x0 +#define WM8350_GPIO11_GPIO_OUT 0x0 +#define WM8350_GPIO11_ISINKD_OUT 0x1 +#define WM8350_GPIO11_WAKEUP_IN 0x2 +#define WM8350_GPIO11_LINE_GT_BATT_OUT 0x2 +#define WM8350_GPIO11_CHD_IND_IN 0x3 + +#define WM8350_GPIO12_GPIO_IN 0x0 +#define WM8350_GPIO12_GPIO_OUT 0x0 +#define WM8350_GPIO12_ISINKE_OUT 0x1 +#define WM8350_GPIO12_LINE_GT_BATT_OUT 0x2 +#define WM8350_GPIO12_LINE_EN_OUT 0x3 +#define WM8350_GPIO12_32KHZ_OUT 0x4 + +#define WM8350_GPIO_DIR_IN 0 +#define WM8350_GPIO_DIR_OUT 1 +#define WM8350_GPIO_ACTIVE_LOW 0 +#define WM8350_GPIO_ACTIVE_HIGH 1 +#define WM8350_GPIO_PULL_NONE 0 +#define WM8350_GPIO_PULL_UP 1 +#define WM8350_GPIO_PULL_DOWN 2 +#define WM8350_GPIO_INVERT_OFF 0 +#define WM8350_GPIO_INVERT_ON 1 +#define WM8350_GPIO_DEBOUNCE_OFF 0 +#define WM8350_GPIO_DEBOUNCE_ON 1 + +/* +* R128 (0x80) - GPIO Debounce +*/ +#define WM8350_GP12_DB 0x1000 +#define WM8350_GP11_DB 0x0800 +#define WM8350_GP10_DB 0x0400 +#define WM8350_GP9_DB 0x0200 +#define WM8350_GP8_DB 0x0100 +#define WM8350_GP7_DB 0x0080 +#define WM8350_GP6_DB 0x0040 +#define WM8350_GP5_DB 0x0020 +#define WM8350_GP4_DB 0x0010 +#define WM8350_GP3_DB 0x0008 +#define WM8350_GP2_DB 0x0004 +#define WM8350_GP1_DB 0x0002 +#define WM8350_GP0_DB 0x0001 + +/* +* R129 (0x81) - GPIO Pin pull up Control +*/ +#define WM8350_GP12_PU 0x1000 +#define WM8350_GP11_PU 0x0800 +#define WM8350_GP10_PU 0x0400 +#define WM8350_GP9_PU 0x0200 +#define WM8350_GP8_PU 0x0100 +#define WM8350_GP7_PU 0x0080 +#define WM8350_GP6_PU 0x0040 +#define WM8350_GP5_PU 0x0020 +#define WM8350_GP4_PU 0x0010 +#define WM8350_GP3_PU 0x0008 +#define WM8350_GP2_PU 0x0004 +#define WM8350_GP1_PU 0x0002 +#define WM8350_GP0_PU 0x0001 + +/* +* R130 (0x82) - GPIO Pull down Control +*/ +#define WM8350_GP12_PD 0x1000 +#define WM8350_GP11_PD 0x0800 +#define WM8350_GP10_PD 0x0400 +#define WM8350_GP9_PD 0x0200 +#define WM8350_GP8_PD 0x0100 +#define WM8350_GP7_PD 0x0080 +#define WM8350_GP6_PD 0x0040 +#define WM8350_GP5_PD 0x0020 +#define WM8350_GP4_PD 0x0010 +#define WM8350_GP3_PD 0x0008 +#define WM8350_GP2_PD 0x0004 +#define WM8350_GP1_PD 0x0002 +#define WM8350_GP0_PD 0x0001 + +/* +* R131 (0x83) - GPIO Interrupt Mode +*/ +#define WM8350_GP12_INTMODE 0x1000 +#define WM8350_GP11_INTMODE 0x0800 +#define WM8350_GP10_INTMODE 0x0400 +#define WM8350_GP9_INTMODE 0x0200 +#define WM8350_GP8_INTMODE 0x0100 +#define WM8350_GP7_INTMODE 0x0080 +#define WM8350_GP6_INTMODE 0x0040 +#define WM8350_GP5_INTMODE 0x0020 +#define WM8350_GP4_INTMODE 0x0010 +#define WM8350_GP3_INTMODE 0x0008 +#define WM8350_GP2_INTMODE 0x0004 +#define WM8350_GP1_INTMODE 0x0002 +#define WM8350_GP0_INTMODE 0x0001 + +/* +* R133 (0x85) - GPIO Control +*/ +#define WM8350_GP_DBTIME_MASK 0x00C0 + +/* +* R134 (0x86) - GPIO Configuration (i/o) +*/ +#define WM8350_GP12_DIR 0x1000 +#define WM8350_GP11_DIR 0x0800 +#define WM8350_GP10_DIR 0x0400 +#define WM8350_GP9_DIR 0x0200 +#define WM8350_GP8_DIR 0x0100 +#define WM8350_GP7_DIR 0x0080 +#define WM8350_GP6_DIR 0x0040 +#define WM8350_GP5_DIR 0x0020 +#define WM8350_GP4_DIR 0x0010 +#define WM8350_GP3_DIR 0x0008 +#define WM8350_GP2_DIR 0x0004 +#define WM8350_GP1_DIR 0x0002 +#define WM8350_GP0_DIR 0x0001 + +/* +* R135 (0x87) - GPIO Pin Polarity / Type +*/ +#define WM8350_GP12_CFG 0x1000 +#define WM8350_GP11_CFG 0x0800 +#define WM8350_GP10_CFG 0x0400 +#define WM8350_GP9_CFG 0x0200 +#define WM8350_GP8_CFG 0x0100 +#define WM8350_GP7_CFG 0x0080 +#define WM8350_GP6_CFG 0x0040 +#define WM8350_GP5_CFG 0x0020 +#define WM8350_GP4_CFG 0x0010 +#define WM8350_GP3_CFG 0x0008 +#define WM8350_GP2_CFG 0x0004 +#define WM8350_GP1_CFG 0x0002 +#define WM8350_GP0_CFG 0x0001 + +/* +* R140 (0x8C) - GPIO Function Select 1 +*/ +#define WM8350_GP3_FN_MASK 0xF000 +#define WM8350_GP2_FN_MASK 0x0F00 +#define WM8350_GP1_FN_MASK 0x00F0 +#define WM8350_GP0_FN_MASK 0x000F + +/* +* R141 (0x8D) - GPIO Function Select 2 +*/ +#define WM8350_GP7_FN_MASK 0xF000 +#define WM8350_GP6_FN_MASK 0x0F00 +#define WM8350_GP5_FN_MASK 0x00F0 +#define WM8350_GP4_FN_MASK 0x000F + +/* +* R142 (0x8E) - GPIO Function Select 3 +*/ +#define WM8350_GP11_FN_MASK 0xF000 +#define WM8350_GP10_FN_MASK 0x0F00 +#define WM8350_GP9_FN_MASK 0x00F0 +#define WM8350_GP8_FN_MASK 0x000F + +/* +* R143 (0x8F) - GPIO Function Select 4 +*/ +#define WM8350_GP12_FN_MASK 0x000F + +/* +* R230 (0xE6) - GPIO Pin Status +*/ +#define WM8350_GP12_LVL 0x1000 +#define WM8350_GP11_LVL 0x0800 +#define WM8350_GP10_LVL 0x0400 +#define WM8350_GP9_LVL 0x0200 +#define WM8350_GP8_LVL 0x0100 +#define WM8350_GP7_LVL 0x0080 +#define WM8350_GP6_LVL 0x0040 +#define WM8350_GP5_LVL 0x0020 +#define WM8350_GP4_LVL 0x0010 +#define WM8350_GP3_LVL 0x0008 +#define WM8350_GP2_LVL 0x0004 +#define WM8350_GP1_LVL 0x0002 +#define WM8350_GP0_LVL 0x0001 + +#endif
Signature · 1 line
1.5.6.5
PATCH 3/13 mfd: Add WM8350 PMIC register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/pmic.h | 699 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 699 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/pmic.h
include/linux/mfd/wm8350/pmic.h new file +699 -0
@@ -0,0 +1,699 @@ +/* +* pmic.h -- Power Managment Driver for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +*/ + +#ifndef __LINUX_MFD_WM8350_PMIC_H +#define __LINUX_MFD_WM8350_PMIC_H + +/* +* Register values. +*/ + +#define WM8350_CURRENT_SINK_DRIVER_A 0xAC +#define WM8350_CSA_FLASH_CONTROL 0xAD +#define WM8350_CURRENT_SINK_DRIVER_B 0xAE +#define WM8350_CSB_FLASH_CONTROL 0xAF +#define WM8350_DCDC_LDO_REQUESTED 0xB0 +#define WM8350_DCDC_ACTIVE_OPTIONS 0xB1 +#define WM8350_DCDC_SLEEP_OPTIONS 0xB2 +#define WM8350_POWER_CHECK_COMPARATOR 0xB3 +#define WM8350_DCDC1_CONTROL 0xB4 +#define WM8350_DCDC1_TIMEOUTS 0xB5 +#define WM8350_DCDC1_LOW_POWER 0xB6 +#define WM8350_DCDC2_CONTROL 0xB7 +#define WM8350_DCDC2_TIMEOUTS 0xB8 +#define WM8350_DCDC3_CONTROL 0xBA +#define WM8350_DCDC3_TIMEOUTS 0xBB +#define WM8350_DCDC3_LOW_POWER 0xBC +#define WM8350_DCDC4_CONTROL 0xBD +#define WM8350_DCDC4_TIMEOUTS 0xBE +#define WM8350_DCDC4_LOW_POWER 0xBF +#define WM8350_DCDC5_CONTROL 0xC0 +#define WM8350_DCDC5_TIMEOUTS 0xC1 +#define WM8350_DCDC6_CONTROL 0xC3 +#define WM8350_DCDC6_TIMEOUTS 0xC4 +#define WM8350_DCDC6_LOW_POWER 0xC5 +#define WM8350_LIMIT_SWITCH_CONTROL 0xC7 +#define WM8350_LDO1_CONTROL 0xC8 +#define WM8350_LDO1_TIMEOUTS 0xC9 +#define WM8350_LDO1_LOW_POWER 0xCA +#define WM8350_LDO2_CONTROL 0xCB +#define WM8350_LDO2_TIMEOUTS 0xCC +#define WM8350_LDO2_LOW_POWER 0xCD +#define WM8350_LDO3_CONTROL 0xCE +#define WM8350_LDO3_TIMEOUTS 0xCF +#define WM8350_LDO3_LOW_POWER 0xD0 +#define WM8350_LDO4_CONTROL 0xD1 +#define WM8350_LDO4_TIMEOUTS 0xD2 +#define WM8350_LDO4_LOW_POWER 0xD3 +#define WM8350_VCC_FAULT_MASKS 0xD7 +#define WM8350_MAIN_BANDGAP_CONTROL 0xD8 +#define WM8350_OSC_CONTROL 0xD9 +#define WM8350_RTC_TICK_CONTROL 0xDA +#define WM8350_SECURITY 0xDB +#define WM8350_RAM_BIST_1 0xDC +#define WM8350_DCDC_LDO_STATUS 0xE1 +#define WM8350_GPIO_PIN_STATUS 0xE6 + +#define WM8350_DCDC1_FORCE_PWM 0xF8 +#define WM8350_DCDC3_FORCE_PWM 0xFA +#define WM8350_DCDC4_FORCE_PWM 0xFB +#define WM8350_DCDC6_FORCE_PWM 0xFD + +/* +* R172 (0xAC) - Current Sink Driver A +*/ +#define WM8350_CS1_HIB_MODE 0x1000 +#define WM8350_CS1_HIB_MODE_MASK 0x1000 +#define WM8350_CS1_HIB_MODE_SHIFT 12 +#define WM8350_CS1_ISEL_MASK 0x003F +#define WM8350_CS1_ISEL_SHIFT 0 + +/* Bit values for R172 (0xAC) */ +#define WM8350_CS1_HIB_MODE_DISABLE 0 +#define WM8350_CS1_HIB_MODE_LEAVE 1 + +#define WM8350_CS1_ISEL_220M 0x3F + +/* +* R173 (0xAD) - CSA Flash control +*/ +#define WM8350_CS1_FLASH_MODE 0x8000 +#define WM8350_CS1_TRIGSRC 0x4000 +#define WM8350_CS1_DRIVE 0x2000 +#define WM8350_CS1_FLASH_DUR_MASK 0x0300 +#define WM8350_CS1_OFF_RAMP_MASK 0x0030 +#define WM8350_CS1_ON_RAMP_MASK 0x0003 + +/* +* R174 (0xAE) - Current Sink Driver B +*/ +#define WM8350_CS2_HIB_MODE 0x1000 +#define WM8350_CS2_ISEL_MASK 0x003F + +/* +* R175 (0xAF) - CSB Flash control +*/ +#define WM8350_CS2_FLASH_MODE 0x8000 +#define WM8350_CS2_TRIGSRC 0x4000 +#define WM8350_CS2_DRIVE 0x2000 +#define WM8350_CS2_FLASH_DUR_MASK 0x0300 +#define WM8350_CS2_OFF_RAMP_MASK 0x0030 +#define WM8350_CS2_ON_RAMP_MASK 0x0003 + +/* +* R176 (0xB0) - DCDC/LDO requested +*/ +#define WM8350_LS_ENA 0x8000 +#define WM8350_LDO4_ENA 0x0800 +#define WM8350_LDO3_ENA 0x0400 +#define WM8350_LDO2_ENA 0x0200 +#define WM8350_LDO1_ENA 0x0100 +#define WM8350_DC6_ENA 0x0020 +#define WM8350_DC5_ENA 0x0010 +#define WM8350_DC4_ENA 0x0008 +#define WM8350_DC3_ENA 0x0004 +#define WM8350_DC2_ENA 0x0002 +#define WM8350_DC1_ENA 0x0001 + +/* +* R177 (0xB1) - DCDC Active options +*/ +#define WM8350_PUTO_MASK 0x3000 +#define WM8350_PWRUP_DELAY_MASK 0x0300 +#define WM8350_DC6_ACTIVE 0x0020 +#define WM8350_DC4_ACTIVE 0x0008 +#define WM8350_DC3_ACTIVE 0x0004 +#define WM8350_DC1_ACTIVE 0x0001 + +/* +* R178 (0xB2) - DCDC Sleep options +*/ +#define WM8350_DC6_SLEEP 0x0020 +#define WM8350_DC4_SLEEP 0x0008 +#define WM8350_DC3_SLEEP 0x0004 +#define WM8350_DC1_SLEEP 0x0001 + +/* +* R179 (0xB3) - Power-check comparator +*/ +#define WM8350_PCCMP_ERRACT 0x4000 +#define WM8350_PCCMP_RAIL 0x0100 +#define WM8350_PCCMP_OFF_THR_MASK 0x0070 +#define WM8350_PCCMP_ON_THR_MASK 0x0007 + +/* +* R180 (0xB4) - DCDC1 Control +*/ +#define WM8350_DC1_OPFLT 0x0400 +#define WM8350_DC1_VSEL_MASK 0x007F +#define WM8350_DC1_VSEL_SHIFT 0 + +/* +* R181 (0xB5) - DCDC1 Timeouts +*/ +#define WM8350_DC1_ERRACT_MASK 0xC000 +#define WM8350_DC1_ERRACT_SHIFT 14 +#define WM8350_DC1_ENSLOT_MASK 0x3C00 +#define WM8350_DC1_ENSLOT_SHIFT 10 +#define WM8350_DC1_SDSLOT_MASK 0x03C0 +#define WM8350_DC1_UVTO_MASK 0x0030 +#define WM8350_DC1_SDSLOT_SHIFT 6 + +/* Bit values for R181 (0xB5) */ +#define WM8350_DC1_ERRACT_NONE 0 +#define WM8350_DC1_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_DC1_ERRACT_SHUTDOWN_SYS 2 + +/* +* R182 (0xB6) - DCDC1 Low Power +*/ +#define WM8350_DC1_HIB_MODE_MASK 0x7000 +#define WM8350_DC1_HIB_TRIG_MASK 0x0300 +#define WM8350_DC1_VIMG_MASK 0x007F + +/* +* R183 (0xB7) - DCDC2 Control +*/ +#define WM8350_DC2_MODE 0x4000 +#define WM8350_DC2_MODE_MASK 0x4000 +#define WM8350_DC2_MODE_SHIFT 14 +#define WM8350_DC2_HIB_MODE 0x1000 +#define WM8350_DC2_HIB_MODE_MASK 0x1000 +#define WM8350_DC2_HIB_MODE_SHIFT 12 +#define WM8350_DC2_HIB_TRIG_MASK 0x0300 +#define WM8350_DC2_HIB_TRIG_SHIFT 8 +#define WM8350_DC2_ILIM 0x0040 +#define WM8350_DC2_ILIM_MASK 0x0040 +#define WM8350_DC2_ILIM_SHIFT 6 +#define WM8350_DC2_RMP_MASK 0x0018 +#define WM8350_DC2_RMP_SHIFT 3 +#define WM8350_DC2_FBSRC_MASK 0x0003 +#define WM8350_DC2_FBSRC_SHIFT 0 + +/* Bit values for R183 (0xB7) */ +#define WM8350_DC2_MODE_BOOST 0 +#define WM8350_DC2_MODE_SWITCH 1 + +#define WM8350_DC2_HIB_MODE_ACTIVE 1 +#define WM8350_DC2_HIB_MODE_DISABLE 0 + +#define WM8350_DC2_HIB_TRIG_NONE 0 +#define WM8350_DC2_HIB_TRIG_LPWR1 1 +#define WM8350_DC2_HIB_TRIG_LPWR2 2 +#define WM8350_DC2_HIB_TRIG_LPWR3 3 + +#define WM8350_DC2_ILIM_HIGH 0 +#define WM8350_DC2_ILIM_LOW 1 + +#define WM8350_DC2_RMP_30V 0 +#define WM8350_DC2_RMP_20V 1 +#define WM8350_DC2_RMP_10V 2 +#define WM8350_DC2_RMP_5V 3 + +#define WM8350_DC2_FBSRC_FB2 0 +#define WM8350_DC2_FBSRC_ISINKA 1 +#define WM8350_DC2_FBSRC_ISINKB 2 +#define WM8350_DC2_FBSRC_USB 3 + +/* +* R184 (0xB8) - DCDC2 Timeouts +*/ +#define WM8350_DC2_ERRACT_MASK 0xC000 +#define WM8350_DC2_ERRACT_SHIFT 14 +#define WM8350_DC2_ENSLOT_MASK 0x3C00 +#define WM8350_DC2_ENSLOT_SHIFT 10 +#define WM8350_DC2_SDSLOT_MASK 0x03C0 +#define WM8350_DC2_UVTO_MASK 0x0030 + +/* Bit values for R184 (0xB8) */ +#define WM8350_DC2_ERRACT_NONE 0 +#define WM8350_DC2_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_DC2_ERRACT_SHUTDOWN_SYS 2 + +/* +* R186 (0xBA) - DCDC3 Control +*/ +#define WM8350_DC3_OPFLT 0x0400 +#define WM8350_DC3_VSEL_MASK 0x007F +#define WM8350_DC3_VSEL_SHIFT 0 + +/* +* R187 (0xBB) - DCDC3 Timeouts +*/ +#define WM8350_DC3_ERRACT_MASK 0xC000 +#define WM8350_DC3_ERRACT_SHIFT 14 +#define WM8350_DC3_ENSLOT_MASK 0x3C00 +#define WM8350_DC3_ENSLOT_SHIFT 10 +#define WM8350_DC3_SDSLOT_MASK 0x03C0 +#define WM8350_DC3_UVTO_MASK 0x0030 +#define WM8350_DC3_SDSLOT_SHIFT 6 + +/* Bit values for R187 (0xBB) */ +#define WM8350_DC3_ERRACT_NONE 0 +#define WM8350_DC3_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_DC3_ERRACT_SHUTDOWN_SYS 2 +/* +* R188 (0xBC) - DCDC3 Low Power +*/ +#define WM8350_DC3_HIB_MODE_MASK 0x7000 +#define WM8350_DC3_HIB_TRIG_MASK 0x0300 +#define WM8350_DC3_VIMG_MASK 0x007F + +/* +* R189 (0xBD) - DCDC4 Control +*/ +#define WM8350_DC4_OPFLT 0x0400 +#define WM8350_DC4_VSEL_MASK 0x007F +#define WM8350_DC4_VSEL_SHIFT 0 + +/* +* R190 (0xBE) - DCDC4 Timeouts +*/ +#define WM8350_DC4_ERRACT_MASK 0xC000 +#define WM8350_DC4_ERRACT_SHIFT 14 +#define WM8350_DC4_ENSLOT_MASK 0x3C00 +#define WM8350_DC4_ENSLOT_SHIFT 10 +#define WM8350_DC4_SDSLOT_MASK 0x03C0 +#define WM8350_DC4_UVTO_MASK 0x0030 +#define WM8350_DC4_SDSLOT_SHIFT 6 + +/* Bit values for R190 (0xBE) */ +#define WM8350_DC4_ERRACT_NONE 0 +#define WM8350_DC4_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_DC4_ERRACT_SHUTDOWN_SYS 2 + +/* +* R191 (0xBF) - DCDC4 Low Power +*/ +#define WM8350_DC4_HIB_MODE_MASK 0x7000 +#define WM8350_DC4_HIB_TRIG_MASK 0x0300 +#define WM8350_DC4_VIMG_MASK 0x007F + +/* +* R192 (0xC0) - DCDC5 Control +*/ +#define WM8350_DC5_MODE 0x4000 +#define WM8350_DC5_MODE_MASK 0x4000 +#define WM8350_DC5_MODE_SHIFT 14 +#define WM8350_DC5_HIB_MODE 0x1000 +#define WM8350_DC5_HIB_MODE_MASK 0x1000 +#define WM8350_DC5_HIB_MODE_SHIFT 12 +#define WM8350_DC5_HIB_TRIG_MASK 0x0300 +#define WM8350_DC5_HIB_TRIG_SHIFT 8 +#define WM8350_DC5_ILIM 0x0040 +#define WM8350_DC5_ILIM_MASK 0x0040 +#define WM8350_DC5_ILIM_SHIFT 6 +#define WM8350_DC5_RMP_MASK 0x0018 +#define WM8350_DC5_RMP_SHIFT 3 +#define WM8350_DC5_FBSRC_MASK 0x0003 +#define WM8350_DC5_FBSRC_SHIFT 0 + +/* Bit values for R192 (0xC0) */ +#define WM8350_DC5_MODE_BOOST 0 +#define WM8350_DC5_MODE_SWITCH 1 + +#define WM8350_DC5_HIB_MODE_ACTIVE 1 +#define WM8350_DC5_HIB_MODE_DISABLE 0 + +#define WM8350_DC5_HIB_TRIG_NONE 0 +#define WM8350_DC5_HIB_TRIG_LPWR1 1 +#define WM8350_DC5_HIB_TRIG_LPWR2 2 +#define WM8350_DC5_HIB_TRIG_LPWR3 3 + +#define WM8350_DC5_ILIM_HIGH 0 +#define WM8350_DC5_ILIM_LOW 1 + +#define WM8350_DC5_RMP_30V 0 +#define WM8350_DC5_RMP_20V 1 +#define WM8350_DC5_RMP_10V 2 +#define WM8350_DC5_RMP_5V 3 + +#define WM8350_DC5_FBSRC_FB2 0 +#define WM8350_DC5_FBSRC_ISINKA 1 +#define WM8350_DC5_FBSRC_ISINKB 2 +#define WM8350_DC5_FBSRC_USB 3 + +/* +* R193 (0xC1) - DCDC5 Timeouts +*/ +#define WM8350_DC5_ERRACT_MASK 0xC000 +#define WM8350_DC5_ERRACT_SHIFT 14 +#define WM8350_DC5_ENSLOT_MASK 0x3C00 +#define WM8350_DC5_ENSLOT_SHIFT 10 +#define WM8350_DC5_SDSLOT_MASK 0x03C0 +#define WM8350_DC5_UVTO_MASK 0x0030 +#define WM8350_DC5_SDSLOT_SHIFT 6 + +/* Bit values for R193 (0xC1) */ +#define WM8350_DC5_ERRACT_NONE 0 +#define WM8350_DC5_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_DC5_ERRACT_SHUTDOWN_SYS 2 + +/* +* R195 (0xC3) - DCDC6 Control +*/ +#define WM8350_DC6_OPFLT 0x0400 +#define WM8350_DC6_VSEL_MASK 0x007F +#define WM8350_DC6_VSEL_SHIFT 0 + +/* +* R196 (0xC4) - DCDC6 Timeouts +*/ +#define WM8350_DC6_ERRACT_MASK 0xC000 +#define WM8350_DC6_ERRACT_SHIFT 14 +#define WM8350_DC6_ENSLOT_MASK 0x3C00 +#define WM8350_DC6_ENSLOT_SHIFT 10 +#define WM8350_DC6_SDSLOT_MASK 0x03C0 +#define WM8350_DC6_UVTO_MASK 0x0030 +#define WM8350_DC6_SDSLOT_SHIFT 6 + +/* Bit values for R196 (0xC4) */ +#define WM8350_DC6_ERRACT_NONE 0 +#define WM8350_DC6_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_DC6_ERRACT_SHUTDOWN_SYS 2 + +/* +* R197 (0xC5) - DCDC6 Low Power +*/ +#define WM8350_DC6_HIB_MODE_MASK 0x7000 +#define WM8350_DC6_HIB_TRIG_MASK 0x0300 +#define WM8350_DC6_VIMG_MASK 0x007F + +/* +* R199 (0xC7) - Limit Switch Control +*/ +#define WM8350_LS_ERRACT_MASK 0xC000 +#define WM8350_LS_ERRACT_SHIFT 14 +#define WM8350_LS_ENSLOT_MASK 0x3C00 +#define WM8350_LS_ENSLOT_SHIFT 10 +#define WM8350_LS_SDSLOT_MASK 0x03C0 +#define WM8350_LS_SDSLOT_SHIFT 6 +#define WM8350_LS_HIB_MODE 0x0010 +#define WM8350_LS_HIB_MODE_MASK 0x0010 +#define WM8350_LS_HIB_MODE_SHIFT 4 +#define WM8350_LS_HIB_PROT 0x0002 +#define WM8350_LS_HIB_PROT_MASK 0x0002 +#define WM8350_LS_HIB_PROT_SHIFT 1 +#define WM8350_LS_PROT 0x0001 +#define WM8350_LS_PROT_MASK 0x0001 +#define WM8350_LS_PROT_SHIFT 0 + +/* Bit values for R199 (0xC7) */ +#define WM8350_LS_ERRACT_NONE 0 +#define WM8350_LS_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_LS_ERRACT_SHUTDOWN_SYS 2 + +/* +* R200 (0xC8) - LDO1 Control +*/ +#define WM8350_LDO1_SWI 0x4000 +#define WM8350_LDO1_OPFLT 0x0400 +#define WM8350_LDO1_VSEL_MASK 0x001F +#define WM8350_LDO1_VSEL_SHIFT 0 + +/* +* R201 (0xC9) - LDO1 Timeouts +*/ +#define WM8350_LDO1_ERRACT_MASK 0xC000 +#define WM8350_LDO1_ERRACT_SHIFT 14 +#define WM8350_LDO1_ENSLOT_MASK 0x3C00 +#define WM8350_LDO1_ENSLOT_SHIFT 10 +#define WM8350_LDO1_SDSLOT_MASK 0x03C0 +#define WM8350_LDO1_UVTO_MASK 0x0030 +#define WM8350_LDO1_SDSLOT_SHIFT 6 + +/* Bit values for R201 (0xC9) */ +#define WM8350_LDO1_ERRACT_NONE 0 +#define WM8350_LDO1_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_LDO1_ERRACT_SHUTDOWN_SYS 2 + +/* +* R202 (0xCA) - LDO1 Low Power +*/ +#define WM8350_LDO1_HIB_MODE_MASK 0x3000 +#define WM8350_LDO1_HIB_TRIG_MASK 0x0300 +#define WM8350_LDO1_VIMG_MASK 0x001F +#define WM8350_LDO1_HIB_MODE_DIS (0x1 << 12) + + +/* +* R203 (0xCB) - LDO2 Control +*/ +#define WM8350_LDO2_SWI 0x4000 +#define WM8350_LDO2_OPFLT 0x0400 +#define WM8350_LDO2_VSEL_MASK 0x001F +#define WM8350_LDO2_VSEL_SHIFT 0 + +/* +* R204 (0xCC) - LDO2 Timeouts +*/ +#define WM8350_LDO2_ERRACT_MASK 0xC000 +#define WM8350_LDO2_ERRACT_SHIFT 14 +#define WM8350_LDO2_ENSLOT_MASK 0x3C00 +#define WM8350_LDO2_ENSLOT_SHIFT 10 +#define WM8350_LDO2_SDSLOT_MASK 0x03C0 +#define WM8350_LDO2_SDSLOT_SHIFT 6 + +/* Bit values for R204 (0xCC) */ +#define WM8350_LDO2_ERRACT_NONE 0 +#define WM8350_LDO2_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_LDO2_ERRACT_SHUTDOWN_SYS 2 + +/* +* R205 (0xCD) - LDO2 Low Power +*/ +#define WM8350_LDO2_HIB_MODE_MASK 0x3000 +#define WM8350_LDO2_HIB_TRIG_MASK 0x0300 +#define WM8350_LDO2_VIMG_MASK 0x001F + +/* +* R206 (0xCE) - LDO3 Control +*/ +#define WM8350_LDO3_SWI 0x4000 +#define WM8350_LDO3_OPFLT 0x0400 +#define WM8350_LDO3_VSEL_MASK 0x001F +#define WM8350_LDO3_VSEL_SHIFT 0 + +/* +* R207 (0xCF) - LDO3 Timeouts +*/ +#define WM8350_LDO3_ERRACT_MASK 0xC000 +#define WM8350_LDO3_ERRACT_SHIFT 14 +#define WM8350_LDO3_ENSLOT_MASK 0x3C00 +#define WM8350_LDO3_ENSLOT_SHIFT 10 +#define WM8350_LDO3_SDSLOT_MASK 0x03C0 +#define WM8350_LDO3_UVTO_MASK 0x0030 +#define WM8350_LDO3_SDSLOT_SHIFT 6 + +/* Bit values for R207 (0xCF) */ +#define WM8350_LDO3_ERRACT_NONE 0 +#define WM8350_LDO3_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_LDO3_ERRACT_SHUTDOWN_SYS 2 + +/* +* R208 (0xD0) - LDO3 Low Power +*/ +#define WM8350_LDO3_HIB_MODE_MASK 0x3000 +#define WM8350_LDO3_HIB_TRIG_MASK 0x0300 +#define WM8350_LDO3_VIMG_MASK 0x001F + +/* +* R209 (0xD1) - LDO4 Control +*/ +#define WM8350_LDO4_SWI 0x4000 +#define WM8350_LDO4_OPFLT 0x0400 +#define WM8350_LDO4_VSEL_MASK 0x001F +#define WM8350_LDO4_VSEL_SHIFT 0 + +/* +* R210 (0xD2) - LDO4 Timeouts +*/ +#define WM8350_LDO4_ERRACT_MASK 0xC000 +#define WM8350_LDO4_ERRACT_SHIFT 14 +#define WM8350_LDO4_ENSLOT_MASK 0x3C00 +#define WM8350_LDO4_ENSLOT_SHIFT 10 +#define WM8350_LDO4_SDSLOT_MASK 0x03C0 +#define WM8350_LDO4_UVTO_MASK 0x0030 +#define WM8350_LDO4_SDSLOT_SHIFT 6 + +/* Bit values for R210 (0xD2) */ +#define WM8350_LDO4_ERRACT_NONE 0 +#define WM8350_LDO4_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_LDO4_ERRACT_SHUTDOWN_SYS 2 + +/* +* R211 (0xD3) - LDO4 Low Power +*/ +#define WM8350_LDO4_HIB_MODE_MASK 0x3000 +#define WM8350_LDO4_HIB_TRIG_MASK 0x0300 +#define WM8350_LDO4_VIMG_MASK 0x001F + +/* +* R215 (0xD7) - VCC_FAULT Masks +*/ +#define WM8350_LS_FAULT 0x8000 +#define WM8350_LDO4_FAULT 0x0800 +#define WM8350_LDO3_FAULT 0x0400 +#define WM8350_LDO2_FAULT 0x0200 +#define WM8350_LDO1_FAULT 0x0100 +#define WM8350_DC6_FAULT 0x0020 +#define WM8350_DC5_FAULT 0x0010 +#define WM8350_DC4_FAULT 0x0008 +#define WM8350_DC3_FAULT 0x0004 +#define WM8350_DC2_FAULT 0x0002 +#define WM8350_DC1_FAULT 0x0001 + +/* +* R216 (0xD8) - Main Bandgap Control +*/ +#define WM8350_MBG_LOAD_FUSES 0x8000 +#define WM8350_MBG_FUSE_WPREP 0x4000 +#define WM8350_MBG_FUSE_WRITE 0x2000 +#define WM8350_MBG_FUSE_TRIM_MASK 0x1F00 +#define WM8350_MBG_TRIM_SRC 0x0020 +#define WM8350_MBG_USER_TRIM_MASK 0x001F + +/* +* R217 (0xD9) - OSC Control +*/ +#define WM8350_OSC_LOAD_FUSES 0x8000 +#define WM8350_OSC_FUSE_WPREP 0x4000 +#define WM8350_OSC_FUSE_WRITE 0x2000 +#define WM8350_OSC_FUSE_TRIM_MASK 0x0F00 +#define WM8350_OSC_TRIM_SRC 0x0020 +#define WM8350_OSC_USER_TRIM_MASK 0x000F + +/* +* R248 (0xF8) - DCDC1 Force PWM +*/ +#define WM8350_DCDC1_FORCE_PWM_ENA 0x0010 + +/* +* R250 (0xFA) - DCDC3 Force PWM +*/ +#define WM8350_DCDC3_FORCE_PWM_ENA 0x0010 + +/* +* R251 (0xFB) - DCDC4 Force PWM +*/ +#define WM8350_DCDC4_FORCE_PWM_ENA 0x0010 + +/* +* R253 (0xFD) - DCDC1 Force PWM +*/ +#define WM8350_DCDC6_FORCE_PWM_ENA 0x0010 + +/* +* DCDC's +*/ +#define WM8350_DCDC_1 0 +#define WM8350_DCDC_2 1 +#define WM8350_DCDC_3 2 +#define WM8350_DCDC_4 3 +#define WM8350_DCDC_5 4 +#define WM8350_DCDC_6 5 + +/* DCDC modes */ +#define WM8350_DCDC_ACTIVE_STANDBY 0 +#define WM8350_DCDC_ACTIVE_PULSE 1 +#define WM8350_DCDC_SLEEP_NORMAL 0 +#define WM8350_DCDC_SLEEP_LOW 1 + +/* DCDC Low power (Hibernate) mode */ +#define WM8350_DCDC_HIB_MODE_CUR (0 << 12) +#define WM8350_DCDC_HIB_MODE_IMAGE (1 << 12) +#define WM8350_DCDC_HIB_MODE_STANDBY (2 << 12) +#define WM8350_DCDC_HIB_MODE_LDO (4 << 12) +#define WM8350_DCDC_HIB_MODE_LDO_IM (5 << 12) +#define WM8350_DCDC_HIB_MODE_DIS (7 << 12) +#define WM8350_DCDC_HIB_MODE_MASK (7 << 12) + +/* DCDC Low Power (Hibernate) signal */ +#define WM8350_DCDC_HIB_SIG_REG (0 << 8) +#define WM8350_DCDC_HIB_SIG_LPWR1 (1 << 8) +#define WM8350_DCDC_HIB_SIG_LPWR2 (2 << 8) +#define WM8350_DCDC_HIB_SIG_LPWR3 (3 << 8) + +/* LDO Low power (Hibernate) mode */ +#define WM8350_LDO_HIB_MODE_IMAGE (0 << 0) +#define WM8350_LDO_HIB_MODE_DIS (1 << 0) + +/* LDO Low Power (Hibernate) signal */ +#define WM8350_LDO_HIB_SIG_REG (0 << 8) +#define WM8350_LDO_HIB_SIG_LPWR1 (1 << 8) +#define WM8350_LDO_HIB_SIG_LPWR2 (2 << 8) +#define WM8350_LDO_HIB_SIG_LPWR3 (3 << 8) + +/* +* LDOs +*/ +#define WM8350_LDO_1 6 +#define WM8350_LDO_2 7 +#define WM8350_LDO_3 8 +#define WM8350_LDO_4 9 + +/* +* ISINKs +*/ +#define WM8350_ISINK_A 10 +#define WM8350_ISINK_B 11 + +#define WM8350_ISINK_MODE_BOOST 0 +#define WM8350_ISINK_MODE_SWITCH 1 +#define WM8350_ISINK_ILIM_NORMAL 0 +#define WM8350_ISINK_ILIM_LOW 1 + +#define WM8350_ISINK_FLASH_DISABLE 0 +#define WM8350_ISINK_FLASH_ENABLE 1 +#define WM8350_ISINK_FLASH_TRIG_BIT 0 +#define WM8350_ISINK_FLASH_TRIG_GPIO 1 +#define WM8350_ISINK_FLASH_MODE_EN (1 << 13) +#define WM8350_ISINK_FLASH_MODE_DIS (0 << 13) +#define WM8350_ISINK_FLASH_DUR_32MS (0 << 8) +#define WM8350_ISINK_FLASH_DUR_64MS (1 << 8) +#define WM8350_ISINK_FLASH_DUR_96MS (2 << 8) +#define WM8350_ISINK_FLASH_DUR_1024MS (3 << 8) +#define WM8350_ISINK_FLASH_ON_INSTANT (0 << 4) +#define WM8350_ISINK_FLASH_ON_0_25S (1 << 4) +#define WM8350_ISINK_FLASH_ON_0_50S (2 << 4) +#define WM8350_ISINK_FLASH_ON_1_00S (3 << 4) +#define WM8350_ISINK_FLASH_ON_1_95S (1 << 4) +#define WM8350_ISINK_FLASH_ON_3_91S (2 << 4) +#define WM8350_ISINK_FLASH_ON_7_80S (3 << 4) +#define WM8350_ISINK_FLASH_OFF_INSTANT (0 << 0) +#define WM8350_ISINK_FLASH_OFF_0_25S (1 << 0) +#define WM8350_ISINK_FLASH_OFF_0_50S (2 << 0) +#define WM8350_ISINK_FLASH_OFF_1_00S (3 << 0) +#define WM8350_ISINK_FLASH_OFF_1_95S (1 << 0) +#define WM8350_ISINK_FLASH_OFF_3_91S (2 << 0) +#define WM8350_ISINK_FLASH_OFF_7_80S (3 << 0) + +/* +* Regulator Interrupts. +*/ +#define WM8350_IRQ_CS1 13 +#define WM8350_IRQ_CS2 14 +#define WM8350_IRQ_UV_LDO4 25 +#define WM8350_IRQ_UV_LDO3 26 +#define WM8350_IRQ_UV_LDO2 27 +#define WM8350_IRQ_UV_LDO1 28 +#define WM8350_IRQ_UV_DC6 29 +#define WM8350_IRQ_UV_DC5 30 +#define WM8350_IRQ_UV_DC4 31 +#define WM8350_IRQ_UV_DC3 32 +#define WM8350_IRQ_UV_DC2 33 +#define WM8350_IRQ_UV_DC1 34 +#define WM8350_IRQ_OC_LS 35 + +#define NUM_WM8350_REGULATORS 12 + +#endif
Signature · 1 line
1.5.6.5
PATCH 4/13 mfd: Add WM8350 PMU register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/supply.h | 105 +++++++++++++++++++++++++++++++++++++ 1 files changed, 105 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/supply.h
include/linux/mfd/wm8350/supply.h new file +105 -0
@@ -0,0 +1,105 @@ +/* +* supply.h -- Power Supply Driver for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +*/ + +#ifndef __LINUX_MFD_WM8350_SUPPLY_H_ +#define __LINUX_MFD_WM8350_SUPPLY_H_ + +/* +* Charger registers +*/ +#define WM8350_BATTERY_CHARGER_CONTROL_1 0xA8 +#define WM8350_BATTERY_CHARGER_CONTROL_2 0xA9 +#define WM8350_BATTERY_CHARGER_CONTROL_3 0xAA + +/* +* R168 (0xA8) - Battery Charger Control 1 +*/ +#define WM8350_CHG_ENA_R168 0x8000 +#define WM8350_CHG_THR 0x2000 +#define WM8350_CHG_EOC_SEL_MASK 0x1C00 +#define WM8350_CHG_TRICKLE_TEMP_CHOKE 0x0200 +#define WM8350_CHG_TRICKLE_USB_CHOKE 0x0100 +#define WM8350_CHG_RECOVER_T 0x0080 +#define WM8350_CHG_END_ACT 0x0040 +#define WM8350_CHG_FAST 0x0020 +#define WM8350_CHG_FAST_USB_THROTTLE 0x0010 +#define WM8350_CHG_NTC_MON 0x0008 +#define WM8350_CHG_BATT_HOT_MON 0x0004 +#define WM8350_CHG_BATT_COLD_MON 0x0002 +#define WM8350_CHG_CHIP_TEMP_MON 0x0001 + +/* +* R169 (0xA9) - Battery Charger Control 2 +*/ +#define WM8350_CHG_ACTIVE 0x8000 +#define WM8350_CHG_PAUSE 0x4000 +#define WM8350_CHG_STS_MASK 0x3000 +#define WM8350_CHG_TIME_MASK 0x0F00 +#define WM8350_CHG_MASK_WALL_FB 0x0080 +#define WM8350_CHG_TRICKLE_SEL 0x0040 +#define WM8350_CHG_VSEL_MASK 0x0030 +#define WM8350_CHG_ISEL_MASK 0x000F +#define WM8350_CHG_STS_OFF 0x0000 +#define WM8350_CHG_STS_TRICKLE 0x1000 +#define WM8350_CHG_STS_FAST 0x2000 + +/* +* R170 (0xAA) - Battery Charger Control 3 +*/ +#define WM8350_CHG_THROTTLE_T_MASK 0x0060 +#define WM8350_CHG_SMART 0x0010 +#define WM8350_CHG_TIMER_ADJT_MASK 0x000F + +/* +* Charger Interrupts +*/ +#define WM8350_IRQ_CHG_BAT_HOT 0 +#define WM8350_IRQ_CHG_BAT_COLD 1 +#define WM8350_IRQ_CHG_BAT_FAIL 2 +#define WM8350_IRQ_CHG_TO 3 +#define WM8350_IRQ_CHG_END 4 +#define WM8350_IRQ_CHG_START 5 +#define WM8350_IRQ_CHG_FAST_RDY 6 +#define WM8350_IRQ_CHG_VBATT_LT_3P9 10 +#define WM8350_IRQ_CHG_VBATT_LT_3P1 11 +#define WM8350_IRQ_CHG_VBATT_LT_2P85 12 + +/* +* Charger Policy +*/ +#define WM8350_CHG_TRICKLE_50mA (0 << 6) +#define WM8350_CHG_TRICKLE_100mA (1 << 6) +#define WM8350_CHG_4_05V (0 << 4) +#define WM8350_CHG_4_10V (1 << 4) +#define WM8350_CHG_4_15V (2 << 4) +#define WM8350_CHG_4_20V (3 << 4) +#define WM8350_CHG_FAST_LIMIT_mA (x) ((x / 50) & 0xf) +#define WM8350_CHG_EOC_mA (x) (((x - 10) & 0x7) << 10) +#define WM8350_CHG_TRICKLE_3_1V (0 << 13) +#define WM8350_CHG_TRICKLE_3_9V (1 << 13) + +/* +* Supply Registers. +*/ +#define WM8350_USB_VOLTAGE_READBACK 0x9C +#define WM8350_LINE_VOLTAGE_READBACK 0x9D +#define WM8350_BATT_VOLTAGE_READBACK 0x9E + +/* +* Supply Interrupts. +*/ +#define WM8350_IRQ_USB_LIMIT 15 +#define WM8350_IRQ_EXT_USB_FB 36 +#define WM8350_IRQ_EXT_WALL_FB 37 +#define WM8350_IRQ_EXT_BAT_FB 38 + +#endif
Signature · 1 line
1.5.6.5
PATCH 5/13 mfd: Add WM8350 comparator register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/comparator.h | 167 +++++++++++++++++++++++++++++++++ 1 files changed, 167 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/comparator.h
include/linux/mfd/wm8350/comparator.h new file +167 -0
@@ -0,0 +1,167 @@ +/* +* comparator.h -- Comparator Aux ADC for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +*/ + +#ifndef __LINUX_MFD_WM8350_COMPARATOR_H_ +#define __LINUX_MFD_WM8350_COMPARATOR_H_ + +/* +* Registers +*/ + +#define WM8350_DIGITISER_CONTROL_1 0x90 +#define WM8350_DIGITISER_CONTROL_2 0x91 +#define WM8350_AUX1_READBACK 0x98 +#define WM8350_AUX2_READBACK 0x99 +#define WM8350_AUX3_READBACK 0x9A +#define WM8350_AUX4_READBACK 0x9B +#define WM8350_CHIP_TEMP_READBACK 0x9F +#define WM8350_GENERIC_COMPARATOR_CONTROL 0xA3 +#define WM8350_GENERIC_COMPARATOR_1 0xA4 +#define WM8350_GENERIC_COMPARATOR_2 0xA5 +#define WM8350_GENERIC_COMPARATOR_3 0xA6 +#define WM8350_GENERIC_COMPARATOR_4 0xA7 + +/* +* R144 (0x90) - Digitiser Control (1) +*/ +#define WM8350_AUXADC_CTC 0x4000 +#define WM8350_AUXADC_POLL 0x2000 +#define WM8350_AUXADC_HIB_MODE 0x1000 +#define WM8350_AUXADC_SEL8 0x0080 +#define WM8350_AUXADC_SEL7 0x0040 +#define WM8350_AUXADC_SEL6 0x0020 +#define WM8350_AUXADC_SEL5 0x0010 +#define WM8350_AUXADC_SEL4 0x0008 +#define WM8350_AUXADC_SEL3 0x0004 +#define WM8350_AUXADC_SEL2 0x0002 +#define WM8350_AUXADC_SEL1 0x0001 + +/* +* R145 (0x91) - Digitiser Control (2) +*/ +#define WM8350_AUXADC_MASKMODE_MASK 0x3000 +#define WM8350_AUXADC_CRATE_MASK 0x0700 +#define WM8350_AUXADC_CAL 0x0004 +#define WM8350_AUX_RBMODE 0x0002 +#define WM8350_AUXADC_WAIT 0x0001 + +/* +* R152 (0x98) - AUX1 Readback +*/ +#define WM8350_AUXADC_SCALE1_MASK 0x6000 +#define WM8350_AUXADC_REF1 0x1000 +#define WM8350_AUXADC_DATA1_MASK 0x0FFF + +/* +* R153 (0x99) - AUX2 Readback +*/ +#define WM8350_AUXADC_SCALE2_MASK 0x6000 +#define WM8350_AUXADC_REF2 0x1000 +#define WM8350_AUXADC_DATA2_MASK 0x0FFF + +/* +* R154 (0x9A) - AUX3 Readback +*/ +#define WM8350_AUXADC_SCALE3_MASK 0x6000 +#define WM8350_AUXADC_REF3 0x1000 +#define WM8350_AUXADC_DATA3_MASK 0x0FFF + +/* +* R155 (0x9B) - AUX4 Readback +*/ +#define WM8350_AUXADC_SCALE4_MASK 0x6000 +#define WM8350_AUXADC_REF4 0x1000 +#define WM8350_AUXADC_DATA4_MASK 0x0FFF + +/* +* R156 (0x9C) - USB Voltage Readback +*/ +#define WM8350_AUXADC_DATA_USB_MASK 0x0FFF + +/* +* R157 (0x9D) - LINE Voltage Readback +*/ +#define WM8350_AUXADC_DATA_LINE_MASK 0x0FFF + +/* +* R158 (0x9E) - BATT Voltage Readback +*/ +#define WM8350_AUXADC_DATA_BATT_MASK 0x0FFF + +/* +* R159 (0x9F) - Chip Temp Readback +*/ +#define WM8350_AUXADC_DATA_CHIPTEMP_MASK 0x0FFF + +/* +* R163 (0xA3) - Generic Comparator Control +*/ +#define WM8350_DCMP4_ENA 0x0008 +#define WM8350_DCMP3_ENA 0x0004 +#define WM8350_DCMP2_ENA 0x0002 +#define WM8350_DCMP1_ENA 0x0001 + +/* +* R164 (0xA4) - Generic comparator 1 +*/ +#define WM8350_DCMP1_SRCSEL_MASK 0xE000 +#define WM8350_DCMP1_GT 0x1000 +#define WM8350_DCMP1_THR_MASK 0x0FFF + +/* +* R165 (0xA5) - Generic comparator 2 +*/ +#define WM8350_DCMP2_SRCSEL_MASK 0xE000 +#define WM8350_DCMP2_GT 0x1000 +#define WM8350_DCMP2_THR_MASK 0x0FFF + +/* +* R166 (0xA6) - Generic comparator 3 +*/ +#define WM8350_DCMP3_SRCSEL_MASK 0xE000 +#define WM8350_DCMP3_GT 0x1000 +#define WM8350_DCMP3_THR_MASK 0x0FFF + +/* +* R167 (0xA7) - Generic comparator 4 +*/ +#define WM8350_DCMP4_SRCSEL_MASK 0xE000 +#define WM8350_DCMP4_GT 0x1000 +#define WM8350_DCMP4_THR_MASK 0x0FFF + +/* +* Interrupts. +*/ +#define WM8350_IRQ_AUXADC_DATARDY 16 +#define WM8350_IRQ_AUXADC_DCOMP4 17 +#define WM8350_IRQ_AUXADC_DCOMP3 18 +#define WM8350_IRQ_AUXADC_DCOMP2 19 +#define WM8350_IRQ_AUXADC_DCOMP1 20 +#define WM8350_IRQ_SYS_HYST_COMP_FAIL 21 +#define WM8350_IRQ_SYS_CHIP_GT115 22 +#define WM8350_IRQ_SYS_CHIP_GT140 23 + +/* +* USB/2, LINE & BATT = ((VRTC * 2) / 4095)) * 10e6 uV +* Where VRTC = 2.7 V +*/ +#define WM8350_AUX_COEFF 1319 + +#define WM8350_AUXADC_AUX1 0 +#define WM8350_AUXADC_AUX2 1 +#define WM8350_AUXADC_AUX3 2 +#define WM8350_AUXADC_AUX4 3 +#define WM8350_AUXADC_USB 4 +#define WM8350_AUXADC_LINE 5 +#define WM8350_AUXADC_BATT 6 +#define WM8350_AUXADC_TEMP 7 + +#endif
Signature · 1 line
1.5.6.5
PATCH 6/13 mfd: Add WM8350 RTC register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/rtc.h | 260 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 260 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/rtc.h
include/linux/mfd/wm8350/rtc.h new file +260 -0
@@ -0,0 +1,260 @@ +/* +* rtc.h -- RTC driver for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +*/ + +#ifndef __LINUX_MFD_WM8350_RTC_H +#define __LINUX_MFD_WM8350_RTC_H + +/* +* Register values. +*/ +#define WM8350_RTC_SECONDS_MINUTES 0x10 +#define WM8350_RTC_HOURS_DAY 0x11 +#define WM8350_RTC_DATE_MONTH 0x12 +#define WM8350_RTC_YEAR 0x13 +#define WM8350_ALARM_SECONDS_MINUTES 0x14 +#define WM8350_ALARM_HOURS_DAY 0x15 +#define WM8350_ALARM_DATE_MONTH 0x16 +#define WM8350_RTC_TIME_CONTROL 0x17 + +/* +* R16 (0x10) - RTC Seconds/Minutes +*/ +#define WM8350_RTC_MINS_MASK 0x7F00 +#define WM8350_RTC_MINS_SHIFT 8 +#define WM8350_RTC_SECS_MASK 0x007F +#define WM8350_RTC_SECS_SHIFT 0 + +/* +* R17 (0x11) - RTC Hours/Day +*/ +#define WM8350_RTC_DAY_MASK 0x0700 +#define WM8350_RTC_DAY_SHIFT 8 +#define WM8350_RTC_HPM_MASK 0x0020 +#define WM8350_RTC_HPM_SHIFT 5 +#define WM8350_RTC_HRS_MASK 0x001F +#define WM8350_RTC_HRS_SHIFT 0 + +/* Bit values for R21 (0x15) */ +#define WM8350_RTC_DAY_SUN 1 +#define WM8350_RTC_DAY_MON 2 +#define WM8350_RTC_DAY_TUE 3 +#define WM8350_RTC_DAY_WED 4 +#define WM8350_RTC_DAY_THU 5 +#define WM8350_RTC_DAY_FRI 6 +#define WM8350_RTC_DAY_SAT 7 + +#define WM8350_RTC_HPM_AM 0 +#define WM8350_RTC_HPM_PM 1 + +/* +* R18 (0x12) - RTC Date/Month +*/ +#define WM8350_RTC_MTH_MASK 0x1F00 +#define WM8350_RTC_MTH_SHIFT 8 +#define WM8350_RTC_DATE_MASK 0x003F +#define WM8350_RTC_DATE_SHIFT 0 + +/* Bit values for R22 (0x16) */ +#define WM8350_RTC_MTH_JAN 1 +#define WM8350_RTC_MTH_FEB 2 +#define WM8350_RTC_MTH_MAR 3 +#define WM8350_RTC_MTH_APR 4 +#define WM8350_RTC_MTH_MAY 5 +#define WM8350_RTC_MTH_JUN 6 +#define WM8350_RTC_MTH_JUL 7 +#define WM8350_RTC_MTH_AUG 8 +#define WM8350_RTC_MTH_SEP 9 +#define WM8350_RTC_MTH_OCT 10 +#define WM8350_RTC_MTH_NOV 11 +#define WM8350_RTC_MTH_DEC 12 +#define WM8350_RTC_MTH_JAN_BCD 0x01 +#define WM8350_RTC_MTH_FEB_BCD 0x02 +#define WM8350_RTC_MTH_MAR_BCD 0x03 +#define WM8350_RTC_MTH_APR_BCD 0x04 +#define WM8350_RTC_MTH_MAY_BCD 0x05 +#define WM8350_RTC_MTH_JUN_BCD 0x06 +#define WM8350_RTC_MTH_JUL_BCD 0x07 +#define WM8350_RTC_MTH_AUG_BCD 0x08 +#define WM8350_RTC_MTH_SEP_BCD 0x09 +#define WM8350_RTC_MTH_OCT_BCD 0x10 +#define WM8350_RTC_MTH_NOV_BCD 0x11 +#define WM8350_RTC_MTH_DEC_BCD 0x12 + +/* +* R19 (0x13) - RTC Year +*/ +#define WM8350_RTC_YHUNDREDS_MASK 0x3F00 +#define WM8350_RTC_YHUNDREDS_SHIFT 8 +#define WM8350_RTC_YUNITS_MASK 0x00FF +#define WM8350_RTC_YUNITS_SHIFT 0 + +/* +* R20 (0x14) - Alarm Seconds/Minutes +*/ +#define WM8350_RTC_ALMMINS_MASK 0x7F00 +#define WM8350_RTC_ALMMINS_SHIFT 8 +#define WM8350_RTC_ALMSECS_MASK 0x007F +#define WM8350_RTC_ALMSECS_SHIFT 0 + +/* Bit values for R20 (0x14) */ +#define WM8350_RTC_ALMMINS_DONT_CARE -1 +#define WM8350_RTC_ALMSECS_DONT_CARE -1 + +/* +* R21 (0x15) - Alarm Hours/Day +*/ +#define WM8350_RTC_ALMDAY_MASK 0x0F00 +#define WM8350_RTC_ALMDAY_SHIFT 8 +#define WM8350_RTC_ALMHPM_MASK 0x0020 +#define WM8350_RTC_ALMHPM_SHIFT 5 +#define WM8350_RTC_ALMHRS_MASK 0x001F +#define WM8350_RTC_ALMHRS_SHIFT 0 + +/* Bit values for R21 (0x15) */ +#define WM8350_RTC_ALMDAY_DONT_CARE -1 +#define WM8350_RTC_ALMDAY_SUN 1 +#define WM8350_RTC_ALMDAY_MON 2 +#define WM8350_RTC_ALMDAY_TUE 3 +#define WM8350_RTC_ALMDAY_WED 4 +#define WM8350_RTC_ALMDAY_THU 5 +#define WM8350_RTC_ALMDAY_FRI 6 +#define WM8350_RTC_ALMDAY_SAT 7 + +#define WM8350_RTC_ALMHPM_AM 0 +#define WM8350_RTC_ALMHPM_PM 1 + +#define WM8350_RTC_ALMHRS_DONT_CARE -1 + +/* +* R22 (0x16) - Alarm Date/Month +*/ +#define WM8350_RTC_ALMMTH_MASK 0x1F00 +#define WM8350_RTC_ALMMTH_SHIFT 8 +#define WM8350_RTC_ALMDATE_MASK 0x003F +#define WM8350_RTC_ALMDATE_SHIFT 0 + +/* Bit values for R22 (0x16) */ +#define WM8350_RTC_ALMDATE_DONT_CARE -1 + +#define WM8350_RTC_ALMMTH_DONT_CARE -1 +#define WM8350_RTC_ALMMTH_JAN 1 +#define WM8350_RTC_ALMMTH_FEB 2 +#define WM8350_RTC_ALMMTH_MAR 3 +#define WM8350_RTC_ALMMTH_APR 4 +#define WM8350_RTC_ALMMTH_MAY 5 +#define WM8350_RTC_ALMMTH_JUN 6 +#define WM8350_RTC_ALMMTH_JUL 7 +#define WM8350_RTC_ALMMTH_AUG 8 +#define WM8350_RTC_ALMMTH_SEP 9 +#define WM8350_RTC_ALMMTH_OCT 10 +#define WM8350_RTC_ALMMTH_NOV 11 +#define WM8350_RTC_ALMMTH_DEC 12 +#define WM8350_RTC_ALMMTH_JAN_BCD 0x01 +#define WM8350_RTC_ALMMTH_FEB_BCD 0x02 +#define WM8350_RTC_ALMMTH_MAR_BCD 0x03 +#define WM8350_RTC_ALMMTH_APR_BCD 0x04 +#define WM8350_RTC_ALMMTH_MAY_BCD 0x05 +#define WM8350_RTC_ALMMTH_JUN_BCD 0x06 +#define WM8350_RTC_ALMMTH_JUL_BCD 0x07 +#define WM8350_RTC_ALMMTH_AUG_BCD 0x08 +#define WM8350_RTC_ALMMTH_SEP_BCD 0x09 +#define WM8350_RTC_ALMMTH_OCT_BCD 0x10 +#define WM8350_RTC_ALMMTH_NOV_BCD 0x11 +#define WM8350_RTC_ALMMTH_DEC_BCD 0x12 + +/* +* R23 (0x17) - RTC Time Control +*/ +#define WM8350_RTC_BCD 0x8000 +#define WM8350_RTC_BCD_MASK 0x8000 +#define WM8350_RTC_BCD_SHIFT 15 +#define WM8350_RTC_12HR 0x4000 +#define WM8350_RTC_12HR_MASK 0x4000 +#define WM8350_RTC_12HR_SHIFT 14 +#define WM8350_RTC_DST 0x2000 +#define WM8350_RTC_DST_MASK 0x2000 +#define WM8350_RTC_DST_SHIFT 13 +#define WM8350_RTC_SET 0x0800 +#define WM8350_RTC_SET_MASK 0x0800 +#define WM8350_RTC_SET_SHIFT 11 +#define WM8350_RTC_STS 0x0400 +#define WM8350_RTC_STS_MASK 0x0400 +#define WM8350_RTC_STS_SHIFT 10 +#define WM8350_RTC_ALMSET 0x0200 +#define WM8350_RTC_ALMSET_MASK 0x0200 +#define WM8350_RTC_ALMSET_SHIFT 9 +#define WM8350_RTC_ALMSTS 0x0100 +#define WM8350_RTC_ALMSTS_MASK 0x0100 +#define WM8350_RTC_ALMSTS_SHIFT 8 +#define WM8350_RTC_PINT 0x0070 +#define WM8350_RTC_PINT_MASK 0x0070 +#define WM8350_RTC_PINT_SHIFT 4 +#define WM8350_RTC_DSW 0x000F +#define WM8350_RTC_DSW_MASK 0x000F +#define WM8350_RTC_DSW_SHIFT 0 + +/* Bit values for R23 (0x17) */ +#define WM8350_RTC_BCD_BINARY 0 +#define WM8350_RTC_BCD_BCD 1 + +#define WM8350_RTC_12HR_24HR 0 +#define WM8350_RTC_12HR_12HR 1 + +#define WM8350_RTC_DST_DISABLED 0 +#define WM8350_RTC_DST_ENABLED 1 + +#define WM8350_RTC_SET_RUN 0 +#define WM8350_RTC_SET_SET 1 + +#define WM8350_RTC_STS_RUNNING 0 +#define WM8350_RTC_STS_STOPPED 1 + +#define WM8350_RTC_ALMSET_RUN 0 +#define WM8350_RTC_ALMSET_SET 1 + +#define WM8350_RTC_ALMSTS_RUNNING 0 +#define WM8350_RTC_ALMSTS_STOPPED 1 + +#define WM8350_RTC_PINT_DISABLED 0 +#define WM8350_RTC_PINT_SECS 1 +#define WM8350_RTC_PINT_MINS 2 +#define WM8350_RTC_PINT_HRS 3 +#define WM8350_RTC_PINT_DAYS 4 +#define WM8350_RTC_PINT_MTHS 5 + +#define WM8350_RTC_DSW_DISABLED 0 +#define WM8350_RTC_DSW_1HZ 1 +#define WM8350_RTC_DSW_2HZ 2 +#define WM8350_RTC_DSW_4HZ 3 +#define WM8350_RTC_DSW_8HZ 4 +#define WM8350_RTC_DSW_16HZ 5 +#define WM8350_RTC_DSW_32HZ 6 +#define WM8350_RTC_DSW_64HZ 7 +#define WM8350_RTC_DSW_128HZ 8 +#define WM8350_RTC_DSW_256HZ 9 +#define WM8350_RTC_DSW_512HZ 10 +#define WM8350_RTC_DSW_1024HZ 11 + +/* +* R218 (0xDA) - RTC Tick Control +*/ +#define WM8350_RTC_TICKSTS 0x4000 +#define WM8350_RTC_CLKSRC 0x2000 +#define WM8350_RTC_TRIM_MASK 0x03FF + +/* +* RTC Interrupts. +*/ +#define WM8350_IRQ_RTC_PER 7 +#define WM8350_IRQ_RTC_SEC 8 +#define WM8350_IRQ_RTC_ALM 9 + +#endif
Signature · 1 line
1.5.6.5
PATCH 7/13 mfd: Add WM8350 watchdog register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/wdt.h | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/wdt.h
include/linux/mfd/wm8350/wdt.h new file +22 -0
@@ -0,0 +1,22 @@ +/* +* wdt.h -- Watchdog Driver for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +*/ + +#ifndef __LINUX_MFD_WM8350_WDT_H_ +#define __LINUX_MFD_WM8350_WDT_H_ + +#define WM8350_WDOG_HIB_MODE 0x0080 +#define WM8350_WDOG_DEBUG 0x0040 +#define WM8350_WDOG_MODE_MASK 0x0030 +#define WM8350_WDOG_TO_MASK 0x0007 + +#define WM8350_IRQ_SYS_WDOG_TO 24 + +#endif
Signature · 1 line
1.5.6.5
PATCH 8/13 mfd: Core support for the WM8350 AudioPlus PMIC
The WM8350 is an integrated audio and power management subsystem intended for use as the primary PMIC in mobile multimedia applications. The WM8350 can be controlled via either I2C or SPI - the control interface is provided by a separate module in order to allow greatest flexibility in configuring the kernel.
This driver was originally written by Liam Girdwood and has since been updated to current kernel APIs and split up for submission by me. All the heavy lifting here was done by Liam.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/Kconfig | 47 ++ drivers/mfd/Makefile | 2 + drivers/mfd/wm8350-core.c | 456 ++++++++++++++ drivers/mfd/wm8350-regmap.c | 1323 +++++++++++++++++++++++++++++++++++++++ include/linux/mfd/wm8350/core.h | 585 +++++++++++++++++ 5 files changed, 2413 insertions(+), 0 deletions(-) create mode 100644 drivers/mfd/wm8350-core.c create mode 100644 drivers/mfd/wm8350-regmap.c create mode 100644 include/linux/mfd/wm8350/core.h
drivers/mfd/Kconfig +47 -0
@@ -86,6 +86,53 @@ config MFD_WM8400 the device, additional drivers must be enabled in order to use the functionality of the device. +config MFD_WM8350 + tristate + +config MFD_WM8350_CONFIG_MODE_0 + bool "Support WM8350 in configuration mode 0" + depends on MFD_WM8350 + default y + help + The WM8350 offers four configuration modes with different + initial register states. This option enables support for the + WM8350 in mode 0. + + If unsure say Y + +config MFD_WM8350_CONFIG_MODE_1 + bool "Support WM8350 in configuration mode 1" + depends on MFD_WM8350 + default y + help + The WM8350 offers four configuration modes with different + initial register states. This option enables support for the + WM8350 in mode 1. + + If unsure say Y + +config MFD_WM8350_CONFIG_MODE_2 + bool "Support WM8350 in configuration mode 2" + depends on MFD_WM8350 + default y + help + The WM8350 offers four configuration modes with different + initial register states. This option enables support for the + WM8350 in mode 2. + + If unsure say Y + +config MFD_WM8350_CONFIG_MODE_3 + bool "Support WM8350 in configuration mode 3" + depends on MFD_WM8350 + default y + help + The WM8350 offers four configuration modes with different + initial register states. This option enables support for the + WM8350 in mode 3. + + If unsure say Y + endmenu menu "Multimedia Capabilities Port drivers"
drivers/mfd/Makefile +2 -0
@@ -13,6 +13,8 @@ obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o obj-$(CONFIG_MFD_WM8400) += wm8400-core.o +wm8350-objs := wm8350-core.o wm8350-regmap.o +obj-$(CONFIG_MFD_WM8350) += wm8350.o obj-$(CONFIG_MFD_CORE) += mfd-core.o
drivers/mfd/wm8350-core.c new file +456 -0
456 lines not on this page · raw message
drivers/mfd/wm8350-regmap.c new file +1323 -0
1,323 lines not on this page · raw message
include/linux/mfd/wm8350/core.h new file +585 -0
585 lines not on this page · raw message
Signature · 1 line
1.5.6.5
PATCH 9/13 mfd: Add I2C control support for WM8350
Implement the I2C control interface for the WM8350. This code was originally written by Liam Girdwood and has been updated for submission by Mark Brown.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/Kconfig | 11 ++++ drivers/mfd/Makefile | 1 + drivers/mfd/wm8350-i2c.c | 120 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+), 0 deletions(-) create mode 100644 drivers/mfd/wm8350-i2c.c
drivers/mfd/Kconfig +11 -0
@@ -133,6 +133,17 @@ config MFD_WM8350_CONFIG_MODE_3 If unsure say Y +config MFD_WM8350_I2C + tristate "Support Wolfson Microelectronics WM8350 with I2C" + select MFD_WM8350 + depends on I2C + help + The WM8350 is an integrated audio and power management + subsystem with watchdog and RTC functionality for embedded + systems. This option enables core support for the WM8350 with + I2C as the control interface. Additional options must be + selected to enable support for the functionality of the chip. + endmenu menu "Multimedia Capabilities Port drivers"
drivers/mfd/Makefile +1 -0
@@ -15,6 +15,7 @@ obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o obj-$(CONFIG_MFD_WM8400) += wm8400-core.o wm8350-objs := wm8350-core.o wm8350-regmap.o obj-$(CONFIG_MFD_WM8350) += wm8350.o +obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o obj-$(CONFIG_MFD_CORE) += mfd-core.o
drivers/mfd/wm8350-i2c.c new file +120 -0
120 lines not on this page · raw message
Signature · 1 line
1.5.6.5
PATCH 10/13 mfd: Add GPIO pin configuration support for WM8350
The WM8350 provides a number of user-configurable pins providing access to various signals generated by the functions on the chip. These are referred to as GPIO pins in the device documentation but in Linux terms they are more general than that, providing configuration of alternate functions.
This patch implements support for selecting the alternate functions for these pins. They can also be used as GPIOs in the normal Linux sense - a subsequent patch will add support for doing so.
This code was all written by Liam Girdwood and has had minor updates and rearrangements by Mark Brown.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/Makefile | 2 +- drivers/mfd/wm8350-gpio.c | 222 +++++++++++++++++++++++++++++++++++++++ include/linux/mfd/wm8350/gpio.h | 10 ++ 3 files changed, 233 insertions(+), 1 deletions(-) create mode 100644 drivers/mfd/wm8350-gpio.c
drivers/mfd/Makefile +1 -1
@@ -13,7 +13,7 @@ obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o obj-$(CONFIG_MFD_WM8400) += wm8400-core.o -wm8350-objs := wm8350-core.o wm8350-regmap.o +wm8350-objs := wm8350-core.o wm8350-regmap.o wm8350-gpio.o obj-$(CONFIG_MFD_WM8350) += wm8350.o obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o
drivers/mfd/wm8350-gpio.c new file +222 -0
222 lines not on this page · raw message
include/linux/mfd/wm8350/gpio.h +10 -0
@@ -323,4 +323,14 @@#define WM8350_GP1_LVL 0x0002#define WM8350_GP0_LVL 0x0001 +struct wm8350 ; + +int wm8350_gpio_config (struct wm8350 *wm8350,int gpio,int dir,int func, +int pol,int pull,int invert,int debounce); + +/* +* GPIO Interrupts +*/ +#define WM8350_IRQ_GPIO (x) (50 + x) +#endif
Signature · 1 line
1.5.6.5
PATCH 11/13 mfd: Add initialisation callback for WM8350
Some functions of the WM8350 require board-specific initialisation on startup. Provide a callback to the WM8350 driver in platform data for platforms to use to configure the chip. Use of a callback allows platforms to control the ordering of initialisation which can be important.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/wm8350-core.c | 12 +++++++++++- drivers/mfd/wm8350-i2c.c | 2 +- include/linux/mfd/wm8350/core.h | 14 +++++++++++++- 3 files changed, 25 insertions(+), 3 deletions(-)
drivers/mfd/wm8350-core.c +11 -1
@@ -388,7 +388,8 @@ out: }EXPORT_SYMBOL_GPL (wm8350_create_cache); -int wm8350_device_init (struct wm8350 *wm8350) +int wm8350_device_init (struct wm8350 *wm8350, +struct wm8350_platform_data *pdata) {int ret = -EINVAL ;u16 id1, id2, mask, mode;
@@ -439,6 +440,15 @@ int wm8350_device_init(struct wm8350 *wm8350)return ret; } +if (pdata->init) { + ret = pdata->init (wm8350); +if (ret !=0 ) { +dev_err (wm8350->dev,"Platform init() failed: %d\n" , + ret); + goto err; + } + } +return 0 ; err:
drivers/mfd/wm8350-i2c.c +1 -1
@@ -65,7 +65,7 @@ static int wm8350_i2c_probe(struct i2c_client *i2c, wm8350->read_dev = wm8350_i2c_read_device; wm8350->write_dev = wm8350_i2c_write_device; - ret =wm8350_device_init (wm8350); + ret =wm8350_device_init (wm8350, i2c->dev.platform_data);if (ret <0 ) goto err;
include/linux/mfd/wm8350/core.h +13 -1
@@ -564,10 +564,22 @@ struct wm8350 {u16 *reg_cache; }; +/** +* Data to be supplied by the platform to initialise the WM8350. +* +* @init: Function called during driver initialisation. Should be +* used by the platform to configure GPIO functions and similar. +*/ +struct wm8350_platform_data { +int (*init)(struct wm8350 *wm8350); +}; + +/* * WM8350 device initialisation and exit. */ -int wm8350_device_init (struct wm8350 *wm8350); +int wm8350_device_init (struct wm8350 *wm8350, +struct wm8350_platform_data *pdata);void wm8350_device_exit (struct wm8350 *wm8350);/*
Signature · 1 line
1.5.6.5
PATCH 12/13 mfd: Add WM8350 interrupt support
The WM8350 has an interrupt line to the CPU which is shared by the devices on the CPU. This patch adds support for the interrupt controller within the WM8350 which identifies which identifies the interrupt cause. In common with other similar chips this is done outside the standard interrupt framework due to the need to access the interrupt controller over an interrupt-driven bus.
This code was all originally written by Liam Girdwood with updates for submission by me.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/wm8350-core.c | 775 ++++++++++++++++++++++++++++++++++++++- drivers/mfd/wm8350-i2c.c | 2 +- include/linux/mfd/wm8350/core.h | 21 +- 3 files changed, 792 insertions(+), 6 deletions(-)
drivers/mfd/wm8350-core.c +771 -4
@@ -15,15 +15,20 @@#include <linux/kernel.h> #include <linux/module.h> #include <linux/init.h> +#include <linux/bug.h> #include <linux/device.h> #include <linux/delay.h> #include <linux/interrupt.h> +#include <linux/workqueue.h> #include <linux/mfd/wm8350/core.h> #include <linux/mfd/wm8350/audio.h> +#include <linux/mfd/wm8350/comparator.h> #include <linux/mfd/wm8350/gpio.h> #include <linux/mfd/wm8350/pmic.h> +#include <linux/mfd/wm8350/rtc.h> #include <linux/mfd/wm8350/supply.h> +#include <linux/mfd/wm8350/wdt.h> #define WM8350_UNLOCK_KEY 0x0013#define WM8350_LOCK_KEY 0x0000
@@ -321,6 +326,743 @@ int wm8350_reg_unlock(struct wm8350 *wm8350) }EXPORT_SYMBOL_GPL (wm8350_reg_unlock); +static void wm8350_irq_call_handler (struct wm8350 *wm8350,int irq) +{ +mutex_lock (&wm8350->irq_mutex); + +if (wm8350->irq[irq].handler) + wm8350->irq[irq].handler (wm8350, irq, wm8350->irq[irq].data); +else { +dev_err (wm8350->dev,"irq %d nobody cared. now masked.\n" , + irq); +wm8350_mask_irq (wm8350, irq); + } + +mutex_unlock (&wm8350->irq_mutex); +} + +/* +* wm8350_irq_worker actually handles the interrupts. Since all +* interrupts are clear on read the IRQ line will be reasserted and +* the physical IRQ will be handled again if another interrupt is +* asserted while we run - in the normal course of events this is a +* rare occurrence so we save I2C/SPI reads. +*/ +static void wm8350_irq_worker (struct work_struct *work) +{ + struct wm8350 *wm8350 = container_of(work, struct wm8350, irq_work); +u16 level_one, status1, status2, comp; + +/* TODO: Use block reads to improve performance? */ + level_one =wm8350_reg_read (wm8350,WM8350_SYSTEM_INTERRUPTS ) + & ~wm8350_reg_read (wm8350,WM8350_SYSTEM_INTERRUPTS_MASK ); + status1 =wm8350_reg_read (wm8350,WM8350_INT_STATUS_1 ) + & ~wm8350_reg_read (wm8350,WM8350_INT_STATUS_1_MASK ); + status2 =wm8350_reg_read (wm8350,WM8350_INT_STATUS_2 ) + & ~wm8350_reg_read (wm8350,WM8350_INT_STATUS_2_MASK ); + comp =wm8350_reg_read (wm8350,WM8350_COMPARATOR_INT_STATUS ) + & ~wm8350_reg_read (wm8350,WM8350_COMPARATOR_INT_STATUS_MASK ); + +/* over current */ +if (level_one &WM8350_OC_INT ) { +u16 oc; + + oc =wm8350_reg_read (wm8350,WM8350_OVER_CURRENT_INT_STATUS ); + oc &= ~wm8350_reg_read (wm8350, +WM8350_OVER_CURRENT_INT_STATUS_MASK ); + +if (oc &WM8350_OC_LS_EINT )/* limit switch */ +wm8350_irq_call_handler (wm8350,WM8350_IRQ_OC_LS ); + } + +/* under voltage */ +if (level_one &WM8350_UV_INT ) { +u16 uv; + + uv =wm8350_reg_read (wm8350,WM8350_UNDER_VOLTAGE_INT_STATUS ); + uv &= ~wm8350_reg_read (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK ); + +if (uv &WM8350_UV_DC1_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_DC1 ); +if (uv &WM8350_UV_DC2_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_DC2 ); +if (uv &WM8350_UV_DC3_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_DC3 ); +if (uv &WM8350_UV_DC4_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_DC4 ); +if (uv &WM8350_UV_DC5_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_DC5 ); +if (uv &WM8350_UV_DC6_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_DC6 ); +if (uv &WM8350_UV_LDO1_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_LDO1 ); +if (uv &WM8350_UV_LDO2_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_LDO2 ); +if (uv &WM8350_UV_LDO3_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_LDO3 ); +if (uv &WM8350_UV_LDO4_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_LDO4 ); + } + +/* charger, RTC */ +if (status1) { +if (status1 &WM8350_CHG_BAT_HOT_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_BAT_HOT ); +if (status1 &WM8350_CHG_BAT_COLD_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_BAT_COLD ); +if (status1 &WM8350_CHG_BAT_FAIL_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_BAT_FAIL ); +if (status1 &WM8350_CHG_TO_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_CHG_TO ); +if (status1 &WM8350_CHG_END_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_CHG_END ); +if (status1 &WM8350_CHG_START_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_CHG_START ); +if (status1 &WM8350_CHG_FAST_RDY_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_FAST_RDY ); +if (status1 &WM8350_CHG_VBATT_LT_3P9_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_VBATT_LT_3P9 ); +if (status1 &WM8350_CHG_VBATT_LT_3P1_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_VBATT_LT_3P1 ); +if (status1 &WM8350_CHG_VBATT_LT_2P85_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_VBATT_LT_2P85 ); +if (status1 &WM8350_RTC_ALM_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_RTC_ALM ); +if (status1 &WM8350_RTC_SEC_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_RTC_SEC ); +if (status1 &WM8350_RTC_PER_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_RTC_PER ); + } + +/* current sink, system, aux adc */ +if (status2) { +if (status2 &WM8350_CS1_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_CS1 ); +if (status2 &WM8350_CS2_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_CS2 ); + +if (status2 &WM8350_SYS_HYST_COMP_FAIL_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_SYS_HYST_COMP_FAIL ); +if (status2 &WM8350_SYS_CHIP_GT115_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_SYS_CHIP_GT115 ); +if (status2 &WM8350_SYS_CHIP_GT140_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_SYS_CHIP_GT140 ); +if (status2 &WM8350_SYS_WDOG_TO_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_SYS_WDOG_TO ); + +if (status2 &WM8350_AUXADC_DATARDY_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_AUXADC_DATARDY ); +if (status2 &WM8350_AUXADC_DCOMP4_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_AUXADC_DCOMP4 ); +if (status2 &WM8350_AUXADC_DCOMP3_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_AUXADC_DCOMP3 ); +if (status2 &WM8350_AUXADC_DCOMP2_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_AUXADC_DCOMP2 ); +if (status2 &WM8350_AUXADC_DCOMP1_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_AUXADC_DCOMP1 ); + +if (status2 &WM8350_USB_LIMIT_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_USB_LIMIT ); + } + +/* wake, codec, ext */ +if (comp) { +if (comp &WM8350_WKUP_OFF_STATE_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_WKUP_OFF_STATE ); +if (comp &WM8350_WKUP_HIB_STATE_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_WKUP_HIB_STATE ); +if (comp &WM8350_WKUP_CONV_FAULT_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_WKUP_CONV_FAULT ); +if (comp &WM8350_WKUP_WDOG_RST_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_WKUP_WDOG_RST ); +if (comp &WM8350_WKUP_GP_PWR_ON_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_WKUP_GP_PWR_ON ); +if (comp &WM8350_WKUP_ONKEY_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_WKUP_ONKEY ); +if (comp &WM8350_WKUP_GP_WAKEUP_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_WKUP_GP_WAKEUP ); + +if (comp &WM8350_CODEC_JCK_DET_L_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CODEC_JCK_DET_L ); +if (comp &WM8350_CODEC_JCK_DET_R_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CODEC_JCK_DET_R ); +if (comp &WM8350_CODEC_MICSCD_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CODEC_MICSCD ); +if (comp &WM8350_CODEC_MICD_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_CODEC_MICD ); + +if (comp &WM8350_EXT_USB_FB_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_EXT_USB_FB ); +if (comp &WM8350_EXT_WALL_FB_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_EXT_WALL_FB ); +if (comp &WM8350_EXT_BAT_FB_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_EXT_BAT_FB ); + } + +if (level_one &WM8350_GP_INT ) { +int i; +u16 gpio; + + gpio =wm8350_reg_read (wm8350,WM8350_GPIO_INT_STATUS ); + gpio &= ~wm8350_reg_read (wm8350, +WM8350_GPIO_INT_STATUS_MASK ); + +for (i =0 ; i <12 ; i++) { +if (gpio & (1 << i)) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_GPIO (i)); + } + } + +enable_irq (wm8350->chip_irq); +} + +static irqreturn_t wm8350_irq (int irq,void *data) +{ +struct wm8350 *wm8350 = data; + +disable_irq_nosync (irq); +schedule_work (&wm8350->irq_work); + +return IRQ_HANDLED ; +} + +int wm8350_register_irq (struct wm8350 *wm8350,int irq, +void (*handler) (struct wm8350 *,int ,void *), +void *data) +{ +if (irq <0 || irq >WM8350_NUM_IRQ || !handler) +return -EINVAL ; + +if (wm8350->irq[irq].handler) +return -EBUSY ; + +mutex_lock (&wm8350->irq_mutex); + wm8350->irq[irq].handler = handler; + wm8350->irq[irq].data = data; +mutex_unlock (&wm8350->irq_mutex); + +return 0 ; +} +EXPORT_SYMBOL_GPL (wm8350_register_irq); + +int wm8350_free_irq (struct wm8350 *wm8350,int irq) +{ +if (irq <0 || irq >WM8350_NUM_IRQ ) +return -EINVAL ; + +mutex_lock (&wm8350->irq_mutex); + wm8350->irq[irq].handler =NULL ; +mutex_unlock (&wm8350->irq_mutex); +return 0 ; +} +EXPORT_SYMBOL_GPL (wm8350_free_irq); + +int wm8350_mask_irq (struct wm8350 *wm8350,int irq) +{ +switch (irq) { +case WM8350_IRQ_CHG_BAT_HOT : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_BAT_HOT_EINT ); +case WM8350_IRQ_CHG_BAT_COLD : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_BAT_COLD_EINT ); +case WM8350_IRQ_CHG_BAT_FAIL : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_BAT_FAIL_EINT ); +case WM8350_IRQ_CHG_TO : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_TO_EINT ); +case WM8350_IRQ_CHG_END : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_END_EINT ); +case WM8350_IRQ_CHG_START : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_START_EINT ); +case WM8350_IRQ_CHG_FAST_RDY : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_FAST_RDY_EINT ); +case WM8350_IRQ_RTC_PER : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_RTC_PER_EINT ); +case WM8350_IRQ_RTC_SEC : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_RTC_SEC_EINT ); +case WM8350_IRQ_RTC_ALM : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_RTC_ALM_EINT ); +case WM8350_IRQ_CHG_VBATT_LT_3P9 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_VBATT_LT_3P9_EINT ); +case WM8350_IRQ_CHG_VBATT_LT_3P1 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_VBATT_LT_3P1_EINT ); +case WM8350_IRQ_CHG_VBATT_LT_2P85 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_VBATT_LT_2P85_EINT ); +case WM8350_IRQ_CS1 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_CS1_EINT ); +case WM8350_IRQ_CS2 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_CS2_EINT ); +case WM8350_IRQ_USB_LIMIT : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_USB_LIMIT_EINT ); +case WM8350_IRQ_AUXADC_DATARDY : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DATARDY_EINT ); +case WM8350_IRQ_AUXADC_DCOMP4 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP4_EINT ); +case WM8350_IRQ_AUXADC_DCOMP3 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP3_EINT ); +case WM8350_IRQ_AUXADC_DCOMP2 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP2_EINT ); +case WM8350_IRQ_AUXADC_DCOMP1 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP1_EINT ); +case WM8350_IRQ_SYS_HYST_COMP_FAIL : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_HYST_COMP_FAIL_EINT ); +case WM8350_IRQ_SYS_CHIP_GT115 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_CHIP_GT115_EINT ); +case WM8350_IRQ_SYS_CHIP_GT140 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_CHIP_GT140_EINT ); +case WM8350_IRQ_SYS_WDOG_TO : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_WDOG_TO_EINT ); +case WM8350_IRQ_UV_LDO4 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO4_EINT ); +case WM8350_IRQ_UV_LDO3 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO3_EINT ); +case WM8350_IRQ_UV_LDO2 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO2_EINT ); +case WM8350_IRQ_UV_LDO1 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO1_EINT ); +case WM8350_IRQ_UV_DC6 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC6_EINT ); +case WM8350_IRQ_UV_DC5 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC5_EINT ); +case WM8350_IRQ_UV_DC4 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC4_EINT ); +case WM8350_IRQ_UV_DC3 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC3_EINT ); +case WM8350_IRQ_UV_DC2 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC2_EINT ); +case WM8350_IRQ_UV_DC1 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC1_EINT ); +case WM8350_IRQ_OC_LS : +return wm8350_set_bits (wm8350, +WM8350_OVER_CURRENT_INT_STATUS_MASK , +WM8350_IM_OC_LS_EINT ); +case WM8350_IRQ_EXT_USB_FB : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_EXT_USB_FB_EINT ); +case WM8350_IRQ_EXT_WALL_FB : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_EXT_WALL_FB_EINT ); +case WM8350_IRQ_EXT_BAT_FB : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_EXT_BAT_FB_EINT ); +case WM8350_IRQ_CODEC_JCK_DET_L : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_JCK_DET_L_EINT ); +case WM8350_IRQ_CODEC_JCK_DET_R : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_JCK_DET_R_EINT ); +case WM8350_IRQ_CODEC_MICSCD : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_MICSCD_EINT ); +case WM8350_IRQ_CODEC_MICD : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_MICD_EINT ); +case WM8350_IRQ_WKUP_OFF_STATE : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_OFF_STATE_EINT ); +case WM8350_IRQ_WKUP_HIB_STATE : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_HIB_STATE_EINT ); +case WM8350_IRQ_WKUP_CONV_FAULT : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_CONV_FAULT_EINT ); +case WM8350_IRQ_WKUP_WDOG_RST : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_OFF_STATE_EINT ); +case WM8350_IRQ_WKUP_GP_PWR_ON : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_GP_PWR_ON_EINT ); +case WM8350_IRQ_WKUP_ONKEY : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_ONKEY_EINT ); +case WM8350_IRQ_WKUP_GP_WAKEUP : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_GP_WAKEUP_EINT ); +case WM8350_IRQ_GPIO (0 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP0_EINT ); +case WM8350_IRQ_GPIO (1 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP1_EINT ); +case WM8350_IRQ_GPIO (2 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP2_EINT ); +case WM8350_IRQ_GPIO (3 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP3_EINT ); +case WM8350_IRQ_GPIO (4 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP4_EINT ); +case WM8350_IRQ_GPIO (5 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP5_EINT ); +case WM8350_IRQ_GPIO (6 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP6_EINT ); +case WM8350_IRQ_GPIO (7 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP7_EINT ); +case WM8350_IRQ_GPIO (8 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP8_EINT ); +case WM8350_IRQ_GPIO (9 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP9_EINT ); +case WM8350_IRQ_GPIO (10 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP10_EINT ); +case WM8350_IRQ_GPIO (11 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP11_EINT ); +case WM8350_IRQ_GPIO (12 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP12_EINT ); +default : +dev_warn (wm8350->dev,"Attempting to mask unknown IRQ %d\n" , + irq); +return -EINVAL ; + } +return 0 ; +} +EXPORT_SYMBOL_GPL (wm8350_mask_irq); + +int wm8350_unmask_irq (struct wm8350 *wm8350,int irq) +{ +switch (irq) { +case WM8350_IRQ_CHG_BAT_HOT : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_BAT_HOT_EINT ); +case WM8350_IRQ_CHG_BAT_COLD : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_BAT_COLD_EINT ); +case WM8350_IRQ_CHG_BAT_FAIL : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_BAT_FAIL_EINT ); +case WM8350_IRQ_CHG_TO : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_TO_EINT ); +case WM8350_IRQ_CHG_END : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_END_EINT ); +case WM8350_IRQ_CHG_START : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_START_EINT ); +case WM8350_IRQ_CHG_FAST_RDY : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_FAST_RDY_EINT ); +case WM8350_IRQ_RTC_PER : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_RTC_PER_EINT ); +case WM8350_IRQ_RTC_SEC : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_RTC_SEC_EINT ); +case WM8350_IRQ_RTC_ALM : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_RTC_ALM_EINT ); +case WM8350_IRQ_CHG_VBATT_LT_3P9 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_VBATT_LT_3P9_EINT ); +case WM8350_IRQ_CHG_VBATT_LT_3P1 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_VBATT_LT_3P1_EINT ); +case WM8350_IRQ_CHG_VBATT_LT_2P85 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_VBATT_LT_2P85_EINT ); +case WM8350_IRQ_CS1 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_CS1_EINT ); +case WM8350_IRQ_CS2 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_CS2_EINT ); +case WM8350_IRQ_USB_LIMIT : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_USB_LIMIT_EINT ); +case WM8350_IRQ_AUXADC_DATARDY : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DATARDY_EINT ); +case WM8350_IRQ_AUXADC_DCOMP4 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP4_EINT ); +case WM8350_IRQ_AUXADC_DCOMP3 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP3_EINT ); +case WM8350_IRQ_AUXADC_DCOMP2 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP2_EINT ); +case WM8350_IRQ_AUXADC_DCOMP1 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP1_EINT ); +case WM8350_IRQ_SYS_HYST_COMP_FAIL : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_HYST_COMP_FAIL_EINT ); +case WM8350_IRQ_SYS_CHIP_GT115 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_CHIP_GT115_EINT ); +case WM8350_IRQ_SYS_CHIP_GT140 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_CHIP_GT140_EINT ); +case WM8350_IRQ_SYS_WDOG_TO : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_WDOG_TO_EINT ); +case WM8350_IRQ_UV_LDO4 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO4_EINT ); +case WM8350_IRQ_UV_LDO3 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO3_EINT ); +case WM8350_IRQ_UV_LDO2 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO2_EINT ); +case WM8350_IRQ_UV_LDO1 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO1_EINT ); +case WM8350_IRQ_UV_DC6 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC6_EINT ); +case WM8350_IRQ_UV_DC5 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC5_EINT ); +case WM8350_IRQ_UV_DC4 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC4_EINT ); +case WM8350_IRQ_UV_DC3 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC3_EINT ); +case WM8350_IRQ_UV_DC2 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC2_EINT ); +case WM8350_IRQ_UV_DC1 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC1_EINT ); +case WM8350_IRQ_OC_LS : +return wm8350_clear_bits (wm8350, +WM8350_OVER_CURRENT_INT_STATUS_MASK , +WM8350_IM_OC_LS_EINT ); +case WM8350_IRQ_EXT_USB_FB : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_EXT_USB_FB_EINT ); +case WM8350_IRQ_EXT_WALL_FB : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_EXT_WALL_FB_EINT ); +case WM8350_IRQ_EXT_BAT_FB : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_EXT_BAT_FB_EINT ); +case WM8350_IRQ_CODEC_JCK_DET_L : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_JCK_DET_L_EINT ); +case WM8350_IRQ_CODEC_JCK_DET_R : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_JCK_DET_R_EINT ); +case WM8350_IRQ_CODEC_MICSCD : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_MICSCD_EINT ); +case WM8350_IRQ_CODEC_MICD : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_MICD_EINT ); +case WM8350_IRQ_WKUP_OFF_STATE : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_OFF_STATE_EINT ); +case WM8350_IRQ_WKUP_HIB_STATE : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_HIB_STATE_EINT ); +case WM8350_IRQ_WKUP_CONV_FAULT : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_CONV_FAULT_EINT ); +case WM8350_IRQ_WKUP_WDOG_RST : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_OFF_STATE_EINT ); +case WM8350_IRQ_WKUP_GP_PWR_ON : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_GP_PWR_ON_EINT ); +case WM8350_IRQ_WKUP_ONKEY : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_ONKEY_EINT ); +case WM8350_IRQ_WKUP_GP_WAKEUP : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_GP_WAKEUP_EINT ); +case WM8350_IRQ_GPIO (0 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP0_EINT ); +case WM8350_IRQ_GPIO (1 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP1_EINT ); +case WM8350_IRQ_GPIO (2 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP2_EINT ); +case WM8350_IRQ_GPIO (3 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP3_EINT ); +case WM8350_IRQ_GPIO (4 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP4_EINT ); +case WM8350_IRQ_GPIO (5 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP5_EINT ); +case WM8350_IRQ_GPIO (6 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP6_EINT ); +case WM8350_IRQ_GPIO (7 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP7_EINT ); +case WM8350_IRQ_GPIO (8 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP8_EINT ); +case WM8350_IRQ_GPIO (9 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP9_EINT ); +case WM8350_IRQ_GPIO (10 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP10_EINT ); +case WM8350_IRQ_GPIO (11 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP11_EINT ); +case WM8350_IRQ_GPIO (12 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP12_EINT ); +default : +dev_warn (wm8350->dev,"Attempting to unmask unknown IRQ %d\n" , + irq); +return -EINVAL ; + } +return 0 ; +} +EXPORT_SYMBOL_GPL (wm8350_unmask_irq); +/* * Cache is always host endian. */
@@ -388,11 +1130,17 @@ out: }EXPORT_SYMBOL_GPL (wm8350_create_cache); -int wm8350_device_init (struct wm8350 *wm8350, +int wm8350_device_init (struct wm8350 *wm8350,int irq,struct wm8350_platform_data *pdata) {int ret = -EINVAL ;u16 id1, id2, mask, mode; +int i; + +/* Must be set up by platform init call (0 might be a valid IRQ so +* we can't rely on zeroing). +*/ + wm8350->rtc.per_irq =NO_IRQ ;/* get WM8350 revision and config mode */ wm8350->read_dev (wm8350,WM8350_RESET_ID ,sizeof (id1), &id1);
@@ -401,9 +1149,7 @@ int wm8350_device_init(struct wm8350 *wm8350, id1 =be16_to_cpu (id1); id2 =be16_to_cpu (id2); -if (id1 ==0x0 ) -dev_info (wm8350->dev,"Found Rev C device\n" ); -else if (id1 ==0x6143 ) { +if (id1 ==0x6143 ) {switch ((id2 &WM8350_CHIP_REV_MASK ) >>12 ) {case WM8350_REV_E :dev_info (wm8350->dev,"Found Rev E device\n" );
@@ -449,6 +1195,24 @@ int wm8350_device_init(struct wm8350 *wm8350, } } +mutex_init (&wm8350->irq_mutex); +INIT_WORK (&wm8350->irq_work, wm8350_irq_worker); +if (irq !=NO_IRQ ) { + ret =request_irq (irq, wm8350_irq,0 , +"wm8350" , wm8350); +if (ret !=0 ) { +dev_err (wm8350->dev,"Failed to request IRQ: %d\n" , + ret); + goto err; + } + }else { +dev_err (wm8350->dev,"No IRQ configured\n" ); + goto err; + } + wm8350->chip_irq = irq; + +wm8350_reg_write (wm8350,WM8350_SYSTEM_INTERRUPTS_MASK ,0x0 ); +return 0 ; err:
@@ -459,8 +1223,11 @@ EXPORT_SYMBOL_GPL(wm8350_device_init);void wm8350_device_exit (struct wm8350 *wm8350) { +free_irq (wm8350->chip_irq, wm8350); +flush_work (&wm8350->irq_work);kfree (wm8350->reg_cache); }EXPORT_SYMBOL_GPL (wm8350_device_exit); +MODULE_DESCRIPTION ("WM8350 AudioPlus PMIC core driver" );MODULE_LICENSE ("GPL" );
drivers/mfd/wm8350-i2c.c +1 -1
@@ -65,7 +65,7 @@ static int wm8350_i2c_probe(struct i2c_client *i2c, wm8350->read_dev = wm8350_i2c_read_device; wm8350->write_dev = wm8350_i2c_write_device; - ret =wm8350_device_init (wm8350, i2c->dev.platform_data); + ret =wm8350_device_init (wm8350, i2c->irq, i2c->dev.platform_data);if (ret <0 ) goto err;
include/linux/mfd/wm8350/core.h +20 -1
@@ -530,6 +530,8 @@#define WM8350_REV_F 0x5#define WM8350_REV_G 0x6 +#define WM8350_NUM_IRQ 63 +struct wm8350_reg_access {u16 readable;/* Mask of readable bits */ u16 writable;/* Mask of writable bits */
@@ -562,6 +564,12 @@ struct wm8350 {int (*write_dev)(struct wm8350 *wm8350,char reg,int size,void *src);u16 *reg_cache; + +/* Interrupt handling */ +struct work_struct irq_work; +struct mutex irq_mutex;/* IRQ table mutex */ +struct wm8350_irq irq[WM8350_NUM_IRQ ]; +int chip_irq; };/**
@@ -578,7 +586,7 @@ struct wm8350_platform_data {/* * WM8350 device initialisation and exit. */ -int wm8350_device_init (struct wm8350 *wm8350, +int wm8350_device_init (struct wm8350 *wm8350,int irq,struct wm8350_platform_data *pdata);void wm8350_device_exit (struct wm8350 *wm8350);
@@ -594,4 +602,15 @@ int wm8350_reg_unlock(struct wm8350 *wm8350);int wm8350_block_read (struct wm8350 *wm8350,int reg,int size,u16 *dest);int wm8350_block_write (struct wm8350 *wm8350,int reg,int size,u16 *src); +/* +* WM8350 internal interrupts +*/ +int wm8350_register_irq (struct wm8350 *wm8350,int irq, +void (*handler) (struct wm8350 *,int ,void *), +void *data); +int wm8350_free_irq (struct wm8350 *wm8350,int irq); +int wm8350_mask_irq (struct wm8350 *wm8350,int irq); +int wm8350_unmask_irq (struct wm8350 *wm8350,int irq); + +#endif
Signature · 1 line
1.5.6.5
PATCH 13/13 regulator: Add WM8350 regulator support
The WM8350 features six DCDC convertors (four buck and two boost), four LDO voltage regulators and two constant current sinks. This driver adds support for these through the regulator API.
This driver was written by Liam Girdwood with updates for submission from Mark Brown.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/wm8350-core.c | 6 + drivers/regulator/Kconfig | 10 + drivers/regulator/Makefile | 1 + drivers/regulator/wm8350-regulator.c | 1430 ++++++++++++++++++++++++++++++++++ include/linux/mfd/wm8350/core.h | 5 + include/linux/mfd/wm8350/pmic.h | 42 + 6 files changed, 1494 insertions(+), 0 deletions(-) create mode 100644 drivers/regulator/wm8350-regulator.c
drivers/mfd/wm8350-core.c +6 -0
@@ -1223,6 +1223,12 @@ EXPORT_SYMBOL_GPL(wm8350_device_init);void wm8350_device_exit (struct wm8350 *wm8350) { +int i; + +for (i =0 ; i <ARRAY_SIZE (wm8350->pmic.pdev); i++) +if (wm8350->pmic.pdev[i] !=NULL ) +platform_device_unregister (wm8350->pmic.pdev[i]); +free_irq (wm8350->chip_irq, wm8350);flush_work (&wm8350->irq_work);kfree (wm8350->reg_cache);
drivers/regulator/Kconfig +10 -0
@@ -56,6 +56,14 @@ config REGULATOR_BQ24022 charging select between 100 mA and 500 mA charging current limit. +config REGULATOR_WM8350 + tristate "Wolfson Microelectroncis WM8350 AudioPlus PMIC" + depends on MFD_WM8350 + select REGULATOR + help + This driver provides support for the voltage and current regulators + of the WM8350 AudioPlus PMIC. + config REGULATOR_WM8400 tristate "Wolfson Microelectroncis WM8400 AudioPlus PMIC" depends on MFD_WM8400
@@ -63,3 +71,5 @@ config REGULATOR_WM8400 help This driver provides support for the voltage regulators of the WM8400 AudioPlus PMIC. + +endmenu
drivers/regulator/Makefile +1 -0
@@ -8,6 +8,7 @@ obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += fixed.o obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o +obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
drivers/regulator/wm8350-regulator.c new file +1430 -0
1,430 lines not on this page · raw message
include/linux/mfd/wm8350/core.h +5 -0
@@ -17,6 +17,8 @@#include <linux/mutex.h> #include <linux/workqueue.h> +#include <linux/mfd/wm8350/pmic.h> +/* * Register values. */
@@ -570,6 +572,9 @@ struct wm8350 {struct mutex irq_mutex;/* IRQ table mutex */ struct wm8350_irq irq[WM8350_NUM_IRQ ];int chip_irq; + +/* Client devices */ +struct wm8350_pmic pmic; };/**
include/linux/mfd/wm8350/pmic.h +42 -0
46 lines not on this page · raw message
Signature · 1 line
1.5.6.5
Re: [PATCH 08/13] mfd: Core support for the WM8350 AudioPlus PMIC
In reply to Mark BrownQuoted 11 lines · Mark Brown
drivers/mfd/Kconfig +3
-0@@ -86,6 +86,53 @@ config MFD_WM8400 the device, additional drivers must be enabled in order to use the functionality of the device. +config MFD_WM8350 + tristate +
drivers/mfd/Kconfig config MFD_WM8400 · line 101
Quoted 10 lines
drivers/mfd/Kconfig +10
-0+config MFD_WM8350_CONFIG_MODE_0 + bool "Support WM8350 in configuration mode 0" + depends on MFD_WM8350 + default y + help + The WM8350 offers four configuration modes with different + initial register states. This option enables support for the + WM8350 in mode 0. + + If unsure say Y
I would make the WM8350 mode configuration selectable by the target machines Kconfig rather than let the user choose. Wrong choices would probably mean broken hardware.
Quoted 42 lines
drivers/mfd/Kconfig +0
-0menu "Multimedia Capabilities Port drivers"drivers/mfd/Makefile +2
-0@@ -13,6 +13,8 @@ obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o obj-$(CONFIG_MFD_WM8400) += wm8400-core.o +wm8350-objs := wm8350-core.o wm8350-regmap.o +obj-$(CONFIG_MFD_WM8350) += wm8350.o obj-$(CONFIG_MFD_CORE) += mfd-core.odrivers/mfd/wm8350-core.c new file +21
-0+ +/* +* Cache is always host endian. +*/ +static int wm8350_create_cache (struct wm8350 *wm8350,int mode) +{ +int i, ret =0 ; +u16 value; +const u16 *reg_map; + +switch (mode) { +#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0 +case 0 : + reg_map = wm8350_mode0_defaults; +break ; +#endif +#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1 +case 1 : + reg_map = wm8350_mode1_defaults; +break ; +#endif
drivers/mfd/wm8350-core.c line 353
Quoted 10 lines
drivers/mfd/wm8350-core.c new file +10
-0+#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2 +case 2 : + reg_map = wm8350_mode2_defaults; +break ; +#endif +#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3 +case 3 : + reg_map = wm8350_mode3_defaults; +break ; +#endif
Shouldn't this be #elif for each mode ?
Ditto for the default register values. I would also #error if no mode was selected just to make it's correctly set by machine/board authors.
Liam
Re: [PATCH 08/13] mfd: Core support for the WM8350 AudioPlus PMIC
Quoted 8 lines · Liam Girdwood
Review
Quoted 2 lines · Mark Brown
(quoted diff) +2
-0+config MFD_WM8350_CONFIG_MODE_0 + bool "Support WM8350 in configuration mode 0"I would make the WM8350 mode configuration selectable by the target machines
Kconfigrather than let the user choose. Wrong choices would probably mean broken hardware.
Machines can still select config modes - this just allows people to enable additional modes. That said, on reflection I can't actually see much use for that so I'll just hide the options from the user menus (patch below).
Quoted 7 lines
Review
Quoted 4 lines
(quoted diff) +4
-0+ case 3: + reg_map = wm8350_mode3_defaults; + break; +#endifShouldn't this be #elif for each mode ?
Ditto for the default register values.
This is a deliberate decision in order to allow people to build kernel images supporting multiple boards - the driver will check the mode with the hardware and error out at probe time if support for the mode isn't compiled in. If the register maps were smaller I'd just compile them all in.
Quoted 2 lines
I would also #error if no mode
was selected just to make it's correctly set by machine/board authors.
Yeah, that'd be nice but if the driver does that then it'll be harder for people like subsystem maintainers to do build tests with WM8350 drivers and they won't get picked up by things like allmodconfig checks.
The patch below adds a build time warning for this case - the runtime checks will mean that the driver should be safe since it won't run on unknown hardware.
drivers/mfd/Kconfig +4 -32
@@ -82,48 +82,20 @@ config MFD_WM8350 tristate config MFD_WM8350_CONFIG_MODE_0 - bool "Support WM8350 in configuration mode 0" + bool depends on MFD_WM8350 - default y - help - The WM8350 offers four configuration modes with different - initial register states. This option enables support for the - WM8350 in mode 0. - - If unsure say Y config MFD_WM8350_CONFIG_MODE_1 - bool "Support WM8350 in configuration mode 1" + bool depends on MFD_WM8350 - default y - help - The WM8350 offers four configuration modes with different - initial register states. This option enables support for the - WM8350 in mode 1. - - If unsure say Y config MFD_WM8350_CONFIG_MODE_2 - bool "Support WM8350 in configuration mode 2" + bool depends on MFD_WM8350 - default y - help - The WM8350 offers four configuration modes with different - initial register states. This option enables support for the - WM8350 in mode 2. - - If unsure say Y config MFD_WM8350_CONFIG_MODE_3 - bool "Support WM8350 in configuration mode 3" + bool depends on MFD_WM8350 - default y - help - The WM8350 offers four configuration modes with different - initial register states. This option enables support for the - WM8350 in mode 3. - - If unsure say Y config MFD_WM8350_I2C tristate "Support Wolfson Microelectronics WM8350 with I2C"
drivers/mfd/wm8350-regmap.c +24 -0
@@ -15,6 +15,10 @@#include <linux/mfd/wm8350/core.h> #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0 + +#undef WM8350_HAVE_CONFIG_MODE +#define WM8350_HAVE_CONFIG_MODE +const u16 wm8350_mode0_defaults[] = {0x17FF ,/* R0 - Reset/ID */ 0x1000, /* R1 - ID */
@@ -276,6 +280,10 @@ const u16 wm8350_mode0_defaults[] = {#endif #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1 + +#undef WM8350_HAVE_CONFIG_MODE +#define WM8350_HAVE_CONFIG_MODE +const u16 wm8350_mode1_defaults[] = {0x17FF ,/* R0 - Reset/ID */ 0x1000, /* R1 - ID */
@@ -537,6 +545,10 @@ const u16 wm8350_mode1_defaults[] = {#endif #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2 + +#undef WM8350_HAVE_CONFIG_MODE +#define WM8350_HAVE_CONFIG_MODE +const u16 wm8350_mode2_defaults[] = {0x17FF ,/* R0 - Reset/ID */ 0x1000, /* R1 - ID */
@@ -798,6 +810,10 @@ const u16 wm8350_mode2_defaults[] = {#endif #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3 + +#undef WM8350_HAVE_CONFIG_MODE +#define WM8350_HAVE_CONFIG_MODE +const u16 wm8350_mode3_defaults[] = {0x17FF ,/* R0 - Reset/ID */ 0x1000, /* R1 - ID */
@@ -1058,6 +1074,14 @@ const u16 wm8350_mode3_defaults[] = { };#endif +/* The register defaults for the config mode used must be compiled in but +* due to the impact on kernel size it is possible to disable +*/ +#ifndef WM8350_HAVE_CONFIG_MODE +#warning No WM8350 config modes supported - select at least one of the +#warning MFD_WM8350_CONFIG_MODE_n options from the board driver. +#endif +/* * Access masks. */
Quoted 8 lines · Mark Brown
These patches against the regulator tree add initial support for the WM8350, a multi-function device with several subsystems targetted at embedded systems. This series adds a core driver providing device acess under
drivers/mfdand support for the PMIC functionality of the device via the regulator API. Due to their use in the core some definitions for other parts of the device are also included - drivers for these will follow.
Quoted 5 lines
All the WM8350 drivers submitted here were originally written by Liam Girdwood with some updates from me for submission to mainline.
Samuel, as with the WM8400 are you OK with merging this via the regulator tree?
Samuel, are fine to Ack the MFD parts ?
Liam
Quoted 9 lines · Liam Girdwood
Quoted 8 lines · Mark Brown
These patches against the regulator tree add initial support for the WM8350, a multi-function device with several subsystems targetted at embedded systems. This series adds a core driver providing device acess under
drivers/mfdand support for the PMIC functionality of the device via the regulator API. Due to their use in the core some definitions for other parts of the device are also included - drivers for these will follow.
Quoted 7 lines
Quoted 5 lines
All the WM8350 drivers submitted here were originally written by Liam Girdwood with some updates from me for submission to mainline.
Samuel, as with the WM8400 are you OK with merging this via the regulator tree?
Samuel, are fine to Ack the MFD parts ?
Sorry guys, but I havent had time to look at those patches yet. Liam, when would be the last moment for me to ACK/NACK them ? I expect to be able to do so during this weekend.
Cheers,
Samuel.
Quoted 2 lines
Liam
Signature · 2 lines
Intel Open Source Technology Centre http://oss.intel.com/
Quoted 3 lines · Samuel Ortiz
Sorry guys, but I havent had time to look at those patches yet. Liam, when would be the last moment for me to ACK/NACK them ? I expect to be able to do so during this weekend.
I've done some updates since the original posting incorporating feedback from Liam and an update for the regulator API - do you want me to repost with those? They're sitting in:
git://opensource.wolfsonmicro.com/linux-2.6-audioplus for-lrg
Quoted 11 lines · Mark Brown
Quoted 3 lines · Samuel Ortiz
Sorry guys, but I havent had time to look at those patches yet. Liam, when would be the last moment for me to ACK/NACK them ? I expect to be able to do so during this weekend.
I've done some updates since the original posting incorporating feedback from Liam and an update for the regulator API - do you want me to repost with those? They're sitting in:
git://opensource.wolfsonmicro.com/linux-2.6-audioplusfor-lrg
Yes please.
Thanks
Liam
PATCH 1/14 mfd: Add WM8350 audio register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/audio.h | 592 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 592 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/audio.h
include/linux/mfd/wm8350/audio.h new file +592 -0
@@ -0,0 +1,592 @@ +/* +* audio.h -- Audio Driver for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +*/ + +#ifndef __LINUX_MFD_WM8350_AUDIO_H_ +#define __LINUX_MFD_WM8350_AUDIO_H_ + +#define WM8350_CLOCK_CONTROL_1 0x28 +#define WM8350_CLOCK_CONTROL_2 0x29 +#define WM8350_FLL_CONTROL_1 0x2A +#define WM8350_FLL_CONTROL_2 0x2B +#define WM8350_FLL_CONTROL_3 0x2C +#define WM8350_FLL_CONTROL_4 0x2D +#define WM8350_DAC_CONTROL 0x30 +#define WM8350_DAC_DIGITAL_VOLUME_L 0x32 +#define WM8350_DAC_DIGITAL_VOLUME_R 0x33 +#define WM8350_DAC_LR_RATE 0x35 +#define WM8350_DAC_CLOCK_CONTROL 0x36 +#define WM8350_DAC_MUTE 0x3A +#define WM8350_DAC_MUTE_VOLUME 0x3B +#define WM8350_DAC_SIDE 0x3C +#define WM8350_ADC_CONTROL 0x40 +#define WM8350_ADC_DIGITAL_VOLUME_L 0x42 +#define WM8350_ADC_DIGITAL_VOLUME_R 0x43 +#define WM8350_ADC_DIVIDER 0x44 +#define WM8350_ADC_LR_RATE 0x46 +#define WM8350_INPUT_CONTROL 0x48 +#define WM8350_IN3_INPUT_CONTROL 0x49 +#define WM8350_MIC_BIAS_CONTROL 0x4A +#define WM8350_OUTPUT_CONTROL 0x4C +#define WM8350_JACK_DETECT 0x4D +#define WM8350_ANTI_POP_CONTROL 0x4E +#define WM8350_LEFT_INPUT_VOLUME 0x50 +#define WM8350_RIGHT_INPUT_VOLUME 0x51 +#define WM8350_LEFT_MIXER_CONTROL 0x58 +#define WM8350_RIGHT_MIXER_CONTROL 0x59 +#define WM8350_OUT3_MIXER_CONTROL 0x5C +#define WM8350_OUT4_MIXER_CONTROL 0x5D +#define WM8350_OUTPUT_LEFT_MIXER_VOLUME 0x60 +#define WM8350_OUTPUT_RIGHT_MIXER_VOLUME 0x61 +#define WM8350_INPUT_MIXER_VOLUME_L 0x62 +#define WM8350_INPUT_MIXER_VOLUME_R 0x63 +#define WM8350_INPUT_MIXER_VOLUME 0x64 +#define WM8350_LOUT1_VOLUME 0x68 +#define WM8350_ROUT1_VOLUME 0x69 +#define WM8350_LOUT2_VOLUME 0x6A +#define WM8350_ROUT2_VOLUME 0x6B +#define WM8350_BEEP_VOLUME 0x6F +#define WM8350_AI_FORMATING 0x70 +#define WM8350_ADC_DAC_COMP 0x71 +#define WM8350_AI_ADC_CONTROL 0x72 +#define WM8350_AI_DAC_CONTROL 0x73 +#define WM8350_AIF_TEST 0x74 +#define WM8350_JACK_PIN_STATUS 0xE7 + +/* Bit values for R08 (0x08) */ +#define WM8350_CODEC_ISEL_1_5 0/* x1.5 */ +#define WM8350_CODEC_ISEL_1_0 1/* x1.0 */ +#define WM8350_CODEC_ISEL_0_75 2/* x0.75 */ +#define WM8350_CODEC_ISEL_0_5 3/* x0.5 */ + +#define WM8350_VMID_OFF 0 +#define WM8350_VMID_500K 1 +#define WM8350_VMID_100K 2 +#define WM8350_VMID_10K 3 + +/* +* R40 (0x28) - Clock Control 1 +*/ +#define WM8350_TOCLK_RATE 0x4000 +#define WM8350_MCLK_SEL 0x0800 +#define WM8350_MCLK_DIV_MASK 0x0100 +#define WM8350_BCLK_DIV_MASK 0x00F0 +#define WM8350_OPCLK_DIV_MASK 0x0007 + +/* +* R41 (0x29) - Clock Control 2 +*/ +#define WM8350_LRC_ADC_SEL 0x8000 +#define WM8350_MCLK_DIR 0x0001 + +/* +* R42 (0x2A) - FLL Control 1 +*/ +#define WM8350_FLL_DITHER_WIDTH_MASK 0x3000 +#define WM8350_FLL_DITHER_HP 0x0800 +#define WM8350_FLL_OUTDIV_MASK 0x0700 +#define WM8350_FLL_RSP_RATE_MASK 0x00F0 +#define WM8350_FLL_RATE_MASK 0x0007 + +/* +* R43 (0x2B) - FLL Control 2 +*/ +#define WM8350_FLL_RATIO_MASK 0xF800 +#define WM8350_FLL_N_MASK 0x03FF + +/* +* R44 (0x2C) - FLL Control 3 +*/ +#define WM8350_FLL_K_MASK 0xFFFF + +/* +* R45 (0x2D) - FLL Control 4 +*/ +#define WM8350_FLL_FRAC 0x0020 +#define WM8350_FLL_SLOW_LOCK_REF 0x0010 +#define WM8350_FLL_CLK_SRC_MASK 0x0003 + +/* +* R48 (0x30) - DAC Control +*/ +#define WM8350_DAC_MONO 0x2000 +#define WM8350_AIF_LRCLKRATE 0x1000 +#define WM8350_DEEMP_MASK 0x0030 +#define WM8350_DACL_DATINV 0x0002 +#define WM8350_DACR_DATINV 0x0001 + +/* +* R50 (0x32) - DAC Digital Volume L +*/ +#define WM8350_DAC_VU 0x0100 +#define WM8350_DACL_VOL_MASK 0x00FF + +/* +* R51 (0x33) - DAC Digital Volume R +*/ +#define WM8350_DAC_VU 0x0100 +#define WM8350_DACR_VOL_MASK 0x00FF + +/* +* R53 (0x35) - DAC LR Rate +*/ +#define WM8350_DACLRC_ENA 0x0800 +#define WM8350_DACLRC_RATE_MASK 0x07FF + +/* +* R54 (0x36) - DAC Clock Control +*/ +#define WM8350_DACCLK_POL 0x0010 +#define WM8350_DAC_CLKDIV_MASK 0x0007 + +/* +* R58 (0x3A) - DAC Mute +*/ +#define WM8350_DAC_MUTE_ENA 0x4000 + +/* +* R59 (0x3B) - DAC Mute Volume +*/ +#define WM8350_DAC_MUTEMODE 0x4000 +#define WM8350_DAC_MUTERATE 0x2000 +#define WM8350_DAC_SB_FILT 0x1000 + +/* +* R60 (0x3C) - DAC Side +*/ +#define WM8350_ADC_TO_DACL_MASK 0x3000 +#define WM8350_ADC_TO_DACR_MASK 0x0C00 + +/* +* R64 (0x40) - ADC Control +*/ +#define WM8350_ADC_HPF_CUT_MASK 0x0300 +#define WM8350_ADCL_DATINV 0x0002 +#define WM8350_ADCR_DATINV 0x0001 + +/* +* R66 (0x42) - ADC Digital Volume L +*/ +#define WM8350_ADC_VU 0x0100 +#define WM8350_ADCL_VOL_MASK 0x00FF + +/* +* R67 (0x43) - ADC Digital Volume R +*/ +#define WM8350_ADC_VU 0x0100 +#define WM8350_ADCR_VOL_MASK 0x00FF + +/* +* R68 (0x44) - ADC Divider +*/ +#define WM8350_ADCL_DAC_SVOL_MASK 0x0F00 +#define WM8350_ADCR_DAC_SVOL_MASK 0x00F0 +#define WM8350_ADCCLK_POL 0x0008 +#define WM8350_ADC_CLKDIV_MASK 0x0007 + +/* +* R70 (0x46) - ADC LR Rate +*/ +#define WM8350_ADCLRC_ENA 0x0800 +#define WM8350_ADCLRC_RATE_MASK 0x07FF + +/* +* R72 (0x48) - Input Control +*/ +#define WM8350_IN2R_ENA 0x0400 +#define WM8350_IN1RN_ENA 0x0200 +#define WM8350_IN1RP_ENA 0x0100 +#define WM8350_IN2L_ENA 0x0004 +#define WM8350_IN1LN_ENA 0x0002 +#define WM8350_IN1LP_ENA 0x0001 + +/* +* R73 (0x49) - IN3 Input Control +*/ +#define WM8350_IN3R_SHORT 0x4000 +#define WM8350_IN3L_SHORT 0x0040 + +/* +* R74 (0x4A) - Mic Bias Control +*/ +#define WM8350_MICBSEL 0x4000 +#define WM8350_MCDTHR_MASK 0x001C +#define WM8350_MCDSCTHR_MASK 0x0003 + +/* +* R76 (0x4C) - Output Control +*/ +#define WM8350_OUT4_VROI 0x0800 +#define WM8350_OUT3_VROI 0x0400 +#define WM8350_OUT2_VROI 0x0200 +#define WM8350_OUT1_VROI 0x0100 +#define WM8350_OUT2_FB 0x0004 +#define WM8350_OUT1_FB 0x0001 + +/* +* R77 (0x4D) - Jack Detect +*/ +#define WM8350_JDL_ENA 0x8000 +#define WM8350_JDR_ENA 0x4000 + +/* +* R78 (0x4E) - Anti Pop Control +*/ +#define WM8350_ANTI_POP_MASK 0x0300 +#define WM8350_DIS_OP_LN4_MASK 0x00C0 +#define WM8350_DIS_OP_LN3_MASK 0x0030 +#define WM8350_DIS_OP_OUT2_MASK 0x000C +#define WM8350_DIS_OP_OUT1_MASK 0x0003 + +/* +* R80 (0x50) - Left Input Volume +*/ +#define WM8350_INL_MUTE 0x4000 +#define WM8350_INL_ZC 0x2000 +#define WM8350_IN_VU 0x0100 +#define WM8350_INL_VOL_MASK 0x00FC + +/* +* R81 (0x51) - Right Input Volume +*/ +#define WM8350_INR_MUTE 0x4000 +#define WM8350_INR_ZC 0x2000 +#define WM8350_IN_VU 0x0100 +#define WM8350_INR_VOL_MASK 0x00FC + +/* +* R88 (0x58) - Left Mixer Control +*/ +#define WM8350_DACR_TO_MIXOUTL 0x1000 +#define WM8350_DACL_TO_MIXOUTL 0x0800 +#define WM8350_IN3L_TO_MIXOUTL 0x0004 +#define WM8350_INR_TO_MIXOUTL 0x0002 +#define WM8350_INL_TO_MIXOUTL 0x0001 + +/* +* R89 (0x59) - Right Mixer Control +*/ +#define WM8350_DACR_TO_MIXOUTR 0x1000 +#define WM8350_DACL_TO_MIXOUTR 0x0800 +#define WM8350_IN3R_TO_MIXOUTR 0x0008 +#define WM8350_INR_TO_MIXOUTR 0x0002 +#define WM8350_INL_TO_MIXOUTR 0x0001 + +/* +* R92 (0x5C) - OUT3 Mixer Control +*/ +#define WM8350_DACL_TO_OUT3 0x0800 +#define WM8350_MIXINL_TO_OUT3 0x0100 +#define WM8350_OUT4_TO_OUT3 0x0008 +#define WM8350_MIXOUTL_TO_OUT3 0x0001 + +/* +* R93 (0x5D) - OUT4 Mixer Control +*/ +#define WM8350_DACR_TO_OUT4 0x1000 +#define WM8350_DACL_TO_OUT4 0x0800 +#define WM8350_OUT4_ATTN 0x0400 +#define WM8350_MIXINR_TO_OUT4 0x0200 +#define WM8350_OUT3_TO_OUT4 0x0004 +#define WM8350_MIXOUTR_TO_OUT4 0x0002 +#define WM8350_MIXOUTL_TO_OUT4 0x0001 + +/* +* R96 (0x60) - Output Left Mixer Volume +*/ +#define WM8350_IN3L_MIXOUTL_VOL_MASK 0x0E00 +#define WM8350_IN3L_MIXOUTL_VOL_SHIFT 9 +#define WM8350_INR_MIXOUTL_VOL_MASK 0x00E0 +#define WM8350_INR_MIXOUTL_VOL_SHIFT 5 +#define WM8350_INL_MIXOUTL_VOL_MASK 0x000E +#define WM8350_INL_MIXOUTL_VOL_SHIFT 1 + +/* Bit values for R96 (0x60) */ +#define WM8350_IN3L_MIXOUTL_VOL_OFF 0 +#define WM8350_IN3L_MIXOUTL_VOL_M12DB 1 +#define WM8350_IN3L_MIXOUTL_VOL_M9DB 2 +#define WM8350_IN3L_MIXOUTL_VOL_M6DB 3 +#define WM8350_IN3L_MIXOUTL_VOL_M3DB 4 +#define WM8350_IN3L_MIXOUTL_VOL_0DB 5 +#define WM8350_IN3L_MIXOUTL_VOL_3DB 6 +#define WM8350_IN3L_MIXOUTL_VOL_6DB 7 + +#define WM8350_INR_MIXOUTL_VOL_OFF 0 +#define WM8350_INR_MIXOUTL_VOL_M12DB 1 +#define WM8350_INR_MIXOUTL_VOL_M9DB 2 +#define WM8350_INR_MIXOUTL_VOL_M6DB 3 +#define WM8350_INR_MIXOUTL_VOL_M3DB 4 +#define WM8350_INR_MIXOUTL_VOL_0DB 5 +#define WM8350_INR_MIXOUTL_VOL_3DB 6 +#define WM8350_INR_MIXOUTL_VOL_6DB 7 + +#define WM8350_INL_MIXOUTL_VOL_OFF 0 +#define WM8350_INL_MIXOUTL_VOL_M12DB 1 +#define WM8350_INL_MIXOUTL_VOL_M9DB 2 +#define WM8350_INL_MIXOUTL_VOL_M6DB 3 +#define WM8350_INL_MIXOUTL_VOL_M3DB 4 +#define WM8350_INL_MIXOUTL_VOL_0DB 5 +#define WM8350_INL_MIXOUTL_VOL_3DB 6 +#define WM8350_INL_MIXOUTL_VOL_6DB 7 + +/* +* R97 (0x61) - Output Right Mixer Volume +*/ +#define WM8350_IN3R_MIXOUTR_VOL_MASK 0xE000 +#define WM8350_IN3R_MIXOUTR_VOL_SHIFT 13 +#define WM8350_INR_MIXOUTR_VOL_MASK 0x00E0 +#define WM8350_INR_MIXOUTR_VOL_SHIFT 5 +#define WM8350_INL_MIXOUTR_VOL_MASK 0x000E +#define WM8350_INL_MIXOUTR_VOL_SHIFT 1 + +/* Bit values for R96 (0x60) */ +#define WM8350_IN3R_MIXOUTR_VOL_OFF 0 +#define WM8350_IN3R_MIXOUTR_VOL_M12DB 1 +#define WM8350_IN3R_MIXOUTR_VOL_M9DB 2 +#define WM8350_IN3R_MIXOUTR_VOL_M6DB 3 +#define WM8350_IN3R_MIXOUTR_VOL_M3DB 4 +#define WM8350_IN3R_MIXOUTR_VOL_0DB 5 +#define WM8350_IN3R_MIXOUTR_VOL_3DB 6 +#define WM8350_IN3R_MIXOUTR_VOL_6DB 7 + +#define WM8350_INR_MIXOUTR_VOL_OFF 0 +#define WM8350_INR_MIXOUTR_VOL_M12DB 1 +#define WM8350_INR_MIXOUTR_VOL_M9DB 2 +#define WM8350_INR_MIXOUTR_VOL_M6DB 3 +#define WM8350_INR_MIXOUTR_VOL_M3DB 4 +#define WM8350_INR_MIXOUTR_VOL_0DB 5 +#define WM8350_INR_MIXOUTR_VOL_3DB 6 +#define WM8350_INR_MIXOUTR_VOL_6DB 7 + +#define WM8350_INL_MIXOUTR_VOL_OFF 0 +#define WM8350_INL_MIXOUTR_VOL_M12DB 1 +#define WM8350_INL_MIXOUTR_VOL_M9DB 2 +#define WM8350_INL_MIXOUTR_VOL_M6DB 3 +#define WM8350_INL_MIXOUTR_VOL_M3DB 4 +#define WM8350_INL_MIXOUTR_VOL_0DB 5 +#define WM8350_INL_MIXOUTR_VOL_3DB 6 +#define WM8350_INL_MIXOUTR_VOL_6DB 7 + +/* +* R98 (0x62) - Input Mixer Volume L +*/ +#define WM8350_IN3L_MIXINL_VOL_MASK 0x0E00 +#define WM8350_IN2L_MIXINL_VOL_MASK 0x000E +#define WM8350_INL_MIXINL_VOL 0x0001 + +/* +* R99 (0x63) - Input Mixer Volume R +*/ +#define WM8350_IN3R_MIXINR_VOL_MASK 0xE000 +#define WM8350_IN2R_MIXINR_VOL_MASK 0x00E0 +#define WM8350_INR_MIXINR_VOL 0x0001 + +/* +* R100 (0x64) - Input Mixer Volume +*/ +#define WM8350_OUT4_MIXIN_DST 0x8000 +#define WM8350_OUT4_MIXIN_VOL_MASK 0x000E + +/* +* R104 (0x68) - LOUT1 Volume +*/ +#define WM8350_OUT1L_MUTE 0x4000 +#define WM8350_OUT1L_ZC 0x2000 +#define WM8350_OUT1_VU 0x0100 +#define WM8350_OUT1L_VOL_MASK 0x00FC +#define WM8350_OUT1L_VOL_SHIFT 2 + +/* +* R105 (0x69) - ROUT1 Volume +*/ +#define WM8350_OUT1R_MUTE 0x4000 +#define WM8350_OUT1R_ZC 0x2000 +#define WM8350_OUT1_VU 0x0100 +#define WM8350_OUT1R_VOL_MASK 0x00FC +#define WM8350_OUT1R_VOL_SHIFT 2 + +/* +* R106 (0x6A) - LOUT2 Volume +*/ +#define WM8350_OUT2L_MUTE 0x4000 +#define WM8350_OUT2L_ZC 0x2000 +#define WM8350_OUT2_VU 0x0100 +#define WM8350_OUT2L_VOL_MASK 0x00FC + +/* +* R107 (0x6B) - ROUT2 Volume +*/ +#define WM8350_OUT2R_MUTE 0x4000 +#define WM8350_OUT2R_ZC 0x2000 +#define WM8350_OUT2R_INV 0x0400 +#define WM8350_OUT2R_INV_MUTE 0x0200 +#define WM8350_OUT2_VU 0x0100 +#define WM8350_OUT2R_VOL_MASK 0x00FC + +/* +* R111 (0x6F) - BEEP Volume +*/ +#define WM8350_IN3R_OUT2R_VOL_MASK 0x00E0 + +/* +* R112 (0x70) - AI Formating +*/ +#define WM8350_AIF_BCLK_INV 0x8000 +#define WM8350_AIF_TRI 0x2000 +#define WM8350_AIF_LRCLK_INV 0x1000 +#define WM8350_AIF_WL_MASK 0x0C00 +#define WM8350_AIF_FMT_MASK 0x0300 + +/* +* R113 (0x71) - ADC DAC COMP +*/ +#define WM8350_DAC_COMP 0x0080 +#define WM8350_DAC_COMPMODE 0x0040 +#define WM8350_ADC_COMP 0x0020 +#define WM8350_ADC_COMPMODE 0x0010 +#define WM8350_LOOPBACK 0x0001 + +/* +* R114 (0x72) - AI ADC Control +*/ +#define WM8350_AIFADC_PD 0x0080 +#define WM8350_AIFADCL_SRC 0x0040 +#define WM8350_AIFADCR_SRC 0x0020 +#define WM8350_AIFADC_TDM_CHAN 0x0010 +#define WM8350_AIFADC_TDM 0x0008 + +/* +* R115 (0x73) - AI DAC Control +*/ +#define WM8350_BCLK_MSTR 0x4000 +#define WM8350_AIFDAC_PD 0x0080 +#define WM8350_DACL_SRC 0x0040 +#define WM8350_DACR_SRC 0x0020 +#define WM8350_AIFDAC_TDM_CHAN 0x0010 +#define WM8350_AIFDAC_TDM 0x0008 +#define WM8350_DAC_BOOST_MASK 0x0003 + +/* +* R116 (0x74) - AIF Test +*/ +#define WM8350_CODEC_BYP 0x4000 +#define WM8350_AIFADC_WR_TST 0x2000 +#define WM8350_AIFADC_RD_TST 0x1000 +#define WM8350_AIFDAC_WR_TST 0x0800 +#define WM8350_AIFDAC_RD_TST 0x0400 +#define WM8350_AIFADC_ASYN 0x0020 +#define WM8350_AIFDAC_ASYN 0x0010 + +/* +* R231 (0xE7) - Jack Status +*/ +#define WM8350_JACK_R_LVL 0x0400 + +/* +* WM8350 Platform setup +*/ +#define WM8350_S_CURVE_NONE 0x0 +#define WM8350_S_CURVE_FAST 0x1 +#define WM8350_S_CURVE_MEDIUM 0x2 +#define WM8350_S_CURVE_SLOW 0x3 + +#define WM8350_DISCHARGE_OFF 0x0 +#define WM8350_DISCHARGE_FAST 0x1 +#define WM8350_DISCHARGE_MEDIUM 0x2 +#define WM8350_DISCHARGE_SLOW 0x3 + +#define WM8350_TIE_OFF_500R 0x0 +#define WM8350_TIE_OFF_30K 0x1 + +/* +* Clock sources & directions +*/ +#define WM8350_SYSCLK 0 + +#define WM8350_MCLK_SEL_PLL_MCLK 0 +#define WM8350_MCLK_SEL_PLL_DAC 1 +#define WM8350_MCLK_SEL_PLL_ADC 2 +#define WM8350_MCLK_SEL_PLL_32K 3 +#define WM8350_MCLK_SEL_MCLK 5 + +#define WM8350_MCLK_DIR_OUT 0 +#define WM8350_MCLK_DIR_IN 1 + +/* clock divider id's */ +#define WM8350_ADC_CLKDIV 0 +#define WM8350_DAC_CLKDIV 1 +#define WM8350_BCLK_CLKDIV 2 +#define WM8350_OPCLK_CLKDIV 3 +#define WM8350_TO_CLKDIV 4 +#define WM8350_SYS_CLKDIV 5 +#define WM8350_DACLR_CLKDIV 6 +#define WM8350_ADCLR_CLKDIV 7 + +/* ADC clock dividers */ +#define WM8350_ADCDIV_1 0x0 +#define WM8350_ADCDIV_1_5 0x1 +#define WM8350_ADCDIV_2 0x2 +#define WM8350_ADCDIV_3 0x3 +#define WM8350_ADCDIV_4 0x4 +#define WM8350_ADCDIV_5_5 0x5 +#define WM8350_ADCDIV_6 0x6 + +/* ADC clock dividers */ +#define WM8350_DACDIV_1 0x0 +#define WM8350_DACDIV_1_5 0x1 +#define WM8350_DACDIV_2 0x2 +#define WM8350_DACDIV_3 0x3 +#define WM8350_DACDIV_4 0x4 +#define WM8350_DACDIV_5_5 0x5 +#define WM8350_DACDIV_6 0x6 + +/* BCLK clock dividers */ +#define WM8350_BCLK_DIV_1 (0x0 << 4) +#define WM8350_BCLK_DIV_1_5 (0x1 << 4) +#define WM8350_BCLK_DIV_2 (0x2 << 4) +#define WM8350_BCLK_DIV_3 (0x3 << 4) +#define WM8350_BCLK_DIV_4 (0x4 << 4) +#define WM8350_BCLK_DIV_5_5 (0x5 << 4) +#define WM8350_BCLK_DIV_6 (0x6 << 4) +#define WM8350_BCLK_DIV_8 (0x7 << 4) +#define WM8350_BCLK_DIV_11 (0x8 << 4) +#define WM8350_BCLK_DIV_12 (0x9 << 4) +#define WM8350_BCLK_DIV_16 (0xa << 4) +#define WM8350_BCLK_DIV_22 (0xb << 4) +#define WM8350_BCLK_DIV_24 (0xc << 4) +#define WM8350_BCLK_DIV_32 (0xd << 4) +#define WM8350_BCLK_DIV_44 (0xe << 4) +#define WM8350_BCLK_DIV_48 (0xf << 4) + +/* Sys (MCLK) clock dividers */ +#define WM8350_MCLK_DIV_1 (0x0 << 8) +#define WM8350_MCLK_DIV_2 (0x1 << 8) + +/* OP clock dividers */ +#define WM8350_OPCLK_DIV_1 0x0 +#define WM8350_OPCLK_DIV_2 0x1 +#define WM8350_OPCLK_DIV_3 0x2 +#define WM8350_OPCLK_DIV_4 0x3 +#define WM8350_OPCLK_DIV_5_5 0x4 +#define WM8350_OPCLK_DIV_6 0x5 + +/* DAI ID */ +#define WM8350_HIFI_DAI 0 + +/* +* Audio interrupts. +*/ +#define WM8350_IRQ_CODEC_JCK_DET_L 39 +#define WM8350_IRQ_CODEC_JCK_DET_R 40 +#define WM8350_IRQ_CODEC_MICSCD 41 +#define WM8350_IRQ_CODEC_MICD 42 + +#endif
Signature · 1 line
1.5.6.5
PATCH 2/14 mfd: Add WM8350 GPIO register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/gpio.h | 326 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 326 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/gpio.h
include/linux/mfd/wm8350/gpio.h new file +326 -0
@@ -0,0 +1,326 @@ +/* +* gpio.h -- GPIO Driver for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +*/ + +#ifndef __LINUX_MFD_WM8350_GPIO_H_ +#define __LINUX_MFD_WM8350_GPIO_H_ + +/* +* GPIO Registers. +*/ +#define WM8350_GPIO_DEBOUNCE 0x80 +#define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81 +#define WM8350_GPIO_PULL_DOWN_CONTROL 0x82 +#define WM8350_GPIO_INT_MODE 0x83 +#define WM8350_GPIO_CONTROL 0x85 +#define WM8350_GPIO_CONFIGURATION_I_O 0x86 +#define WM8350_GPIO_PIN_POLARITY_TYPE 0x87 +#define WM8350_GPIO_FUNCTION_SELECT_1 0x8C +#define WM8350_GPIO_FUNCTION_SELECT_2 0x8D +#define WM8350_GPIO_FUNCTION_SELECT_3 0x8E +#define WM8350_GPIO_FUNCTION_SELECT_4 0x8F + +/* +* GPIO Functions +*/ +#define WM8350_GPIO0_GPIO_IN 0x0 +#define WM8350_GPIO0_GPIO_OUT 0x0 +#define WM8350_GPIO0_PWR_ON_IN 0x1 +#define WM8350_GPIO0_PWR_ON_OUT 0x1 +#define WM8350_GPIO0_LDO_EN_IN 0x2 +#define WM8350_GPIO0_VRTC_OUT 0x2 +#define WM8350_GPIO0_LPWR1_IN 0x3 +#define WM8350_GPIO0_POR_B_OUT 0x3 + +#define WM8350_GPIO1_GPIO_IN 0x0 +#define WM8350_GPIO1_GPIO_OUT 0x0 +#define WM8350_GPIO1_PWR_ON_IN 0x1 +#define WM8350_GPIO1_DO_CONF_OUT 0x1 +#define WM8350_GPIO1_LDO_EN_IN 0x2 +#define WM8350_GPIO1_RESET_OUT 0x2 +#define WM8350_GPIO1_LPWR2_IN 0x3 +#define WM8350_GPIO1_MEMRST_OUT 0x3 + +#define WM8350_GPIO2_GPIO_IN 0x0 +#define WM8350_GPIO2_GPIO_OUT 0x0 +#define WM8350_GPIO2_PWR_ON_IN 0x1 +#define WM8350_GPIO2_PWR_ON_OUT 0x1 +#define WM8350_GPIO2_WAKE_UP_IN 0x2 +#define WM8350_GPIO2_VRTC_OUT 0x2 +#define WM8350_GPIO2_32KHZ_IN 0x3 +#define WM8350_GPIO2_32KHZ_OUT 0x3 + +#define WM8350_GPIO3_GPIO_IN 0x0 +#define WM8350_GPIO3_GPIO_OUT 0x0 +#define WM8350_GPIO3_PWR_ON_IN 0x1 +#define WM8350_GPIO3_P_CLK_OUT 0x1 +#define WM8350_GPIO3_LDO_EN_IN 0x2 +#define WM8350_GPIO3_VRTC_OUT 0x2 +#define WM8350_GPIO3_PWR_OFF_IN 0x3 +#define WM8350_GPIO3_32KHZ_OUT 0x3 + +#define WM8350_GPIO4_GPIO_IN 0x0 +#define WM8350_GPIO4_GPIO_OUT 0x0 +#define WM8350_GPIO4_MR_IN 0x1 +#define WM8350_GPIO4_MEM_RST_OUT 0x1 +#define WM8350_GPIO4_FLASH_IN 0x2 +#define WM8350_GPIO4_ADA_OUT 0x2 +#define WM8350_GPIO4_HIBERNATE_IN 0x3 +#define WM8350_GPIO4_FLASH_OUT 0x3 +#define WM8350_GPIO4_MICDET_OUT 0x4 +#define WM8350_GPIO4_MICSHT_OUT 0x5 + +#define WM8350_GPIO5_GPIO_IN 0x0 +#define WM8350_GPIO5_GPIO_OUT 0x0 +#define WM8350_GPIO5_LPWR1_IN 0x1 +#define WM8350_GPIO5_P_CLK_OUT 0x1 +#define WM8350_GPIO5_ADCLRCLK_IN 0x2 +#define WM8350_GPIO5_ADCLRCLK_OUT 0x2 +#define WM8350_GPIO5_HIBERNATE_IN 0x3 +#define WM8350_GPIO5_32KHZ_OUT 0x3 +#define WM8350_GPIO5_MICDET_OUT 0x4 +#define WM8350_GPIO5_MICSHT_OUT 0x5 +#define WM8350_GPIO5_ADA_OUT 0x6 +#define WM8350_GPIO5_OPCLK_OUT 0x7 + +#define WM8350_GPIO6_GPIO_IN 0x0 +#define WM8350_GPIO6_GPIO_OUT 0x0 +#define WM8350_GPIO6_LPWR2_IN 0x1 +#define WM8350_GPIO6_MEMRST_OUT 0x1 +#define WM8350_GPIO6_FLASH_IN 0x2 +#define WM8350_GPIO6_ADA_OUT 0x2 +#define WM8350_GPIO6_HIBERNATE_IN 0x3 +#define WM8350_GPIO6_RTC_OUT 0x3 +#define WM8350_GPIO6_MICDET_OUT 0x4 +#define WM8350_GPIO6_MICSHT_OUT 0x5 +#define WM8350_GPIO6_ADCLRCLKB_OUT 0x6 +#define WM8350_GPIO6_SDOUT_OUT 0x7 + +#define WM8350_GPIO7_GPIO_IN 0x0 +#define WM8350_GPIO7_GPIO_OUT 0x0 +#define WM8350_GPIO7_LPWR3_IN 0x1 +#define WM8350_GPIO7_P_CLK_OUT 0x1 +#define WM8350_GPIO7_MASK_IN 0x2 +#define WM8350_GPIO7_VCC_FAULT_OUT 0x2 +#define WM8350_GPIO7_HIBERNATE_IN 0x3 +#define WM8350_GPIO7_BATT_FAULT_OUT 0x3 +#define WM8350_GPIO7_MICDET_OUT 0x4 +#define WM8350_GPIO7_MICSHT_OUT 0x5 +#define WM8350_GPIO7_ADA_OUT 0x6 +#define WM8350_GPIO7_CSB_IN 0x7 + +#define WM8350_GPIO8_GPIO_IN 0x0 +#define WM8350_GPIO8_GPIO_OUT 0x0 +#define WM8350_GPIO8_MR_IN 0x1 +#define WM8350_GPIO8_VCC_FAULT_OUT 0x1 +#define WM8350_GPIO8_ADCBCLK_IN 0x2 +#define WM8350_GPIO8_ADCBCLK_OUT 0x2 +#define WM8350_GPIO8_PWR_OFF_IN 0x3 +#define WM8350_GPIO8_BATT_FAULT_OUT 0x3 +#define WM8350_GPIO8_ALTSCL_IN 0xf + +#define WM8350_GPIO9_GPIO_IN 0x0 +#define WM8350_GPIO9_GPIO_OUT 0x0 +#define WM8350_GPIO9_HEARTBEAT_IN 0x1 +#define WM8350_GPIO9_VCC_FAULT_OUT 0x1 +#define WM8350_GPIO9_MASK_IN 0x2 +#define WM8350_GPIO9_LINE_GT_BATT_OUT 0x2 +#define WM8350_GPIO9_PWR_OFF_IN 0x3 +#define WM8350_GPIO9_BATT_FAULT_OUT 0x3 +#define WM8350_GPIO9_ALTSDA_OUT 0xf + +#define WM8350_GPIO10_GPIO_IN 0x0 +#define WM8350_GPIO10_GPIO_OUT 0x0 +#define WM8350_GPIO10_ISINKC_OUT 0x1 +#define WM8350_GPIO10_PWR_OFF_IN 0x2 +#define WM8350_GPIO10_LINE_GT_BATT_OUT 0x2 +#define WM8350_GPIO10_CHD_IND_IN 0x3 + +#define WM8350_GPIO11_GPIO_IN 0x0 +#define WM8350_GPIO11_GPIO_OUT 0x0 +#define WM8350_GPIO11_ISINKD_OUT 0x1 +#define WM8350_GPIO11_WAKEUP_IN 0x2 +#define WM8350_GPIO11_LINE_GT_BATT_OUT 0x2 +#define WM8350_GPIO11_CHD_IND_IN 0x3 + +#define WM8350_GPIO12_GPIO_IN 0x0 +#define WM8350_GPIO12_GPIO_OUT 0x0 +#define WM8350_GPIO12_ISINKE_OUT 0x1 +#define WM8350_GPIO12_LINE_GT_BATT_OUT 0x2 +#define WM8350_GPIO12_LINE_EN_OUT 0x3 +#define WM8350_GPIO12_32KHZ_OUT 0x4 + +#define WM8350_GPIO_DIR_IN 0 +#define WM8350_GPIO_DIR_OUT 1 +#define WM8350_GPIO_ACTIVE_LOW 0 +#define WM8350_GPIO_ACTIVE_HIGH 1 +#define WM8350_GPIO_PULL_NONE 0 +#define WM8350_GPIO_PULL_UP 1 +#define WM8350_GPIO_PULL_DOWN 2 +#define WM8350_GPIO_INVERT_OFF 0 +#define WM8350_GPIO_INVERT_ON 1 +#define WM8350_GPIO_DEBOUNCE_OFF 0 +#define WM8350_GPIO_DEBOUNCE_ON 1 + +/* +* R128 (0x80) - GPIO Debounce +*/ +#define WM8350_GP12_DB 0x1000 +#define WM8350_GP11_DB 0x0800 +#define WM8350_GP10_DB 0x0400 +#define WM8350_GP9_DB 0x0200 +#define WM8350_GP8_DB 0x0100 +#define WM8350_GP7_DB 0x0080 +#define WM8350_GP6_DB 0x0040 +#define WM8350_GP5_DB 0x0020 +#define WM8350_GP4_DB 0x0010 +#define WM8350_GP3_DB 0x0008 +#define WM8350_GP2_DB 0x0004 +#define WM8350_GP1_DB 0x0002 +#define WM8350_GP0_DB 0x0001 + +/* +* R129 (0x81) - GPIO Pin pull up Control +*/ +#define WM8350_GP12_PU 0x1000 +#define WM8350_GP11_PU 0x0800 +#define WM8350_GP10_PU 0x0400 +#define WM8350_GP9_PU 0x0200 +#define WM8350_GP8_PU 0x0100 +#define WM8350_GP7_PU 0x0080 +#define WM8350_GP6_PU 0x0040 +#define WM8350_GP5_PU 0x0020 +#define WM8350_GP4_PU 0x0010 +#define WM8350_GP3_PU 0x0008 +#define WM8350_GP2_PU 0x0004 +#define WM8350_GP1_PU 0x0002 +#define WM8350_GP0_PU 0x0001 + +/* +* R130 (0x82) - GPIO Pull down Control +*/ +#define WM8350_GP12_PD 0x1000 +#define WM8350_GP11_PD 0x0800 +#define WM8350_GP10_PD 0x0400 +#define WM8350_GP9_PD 0x0200 +#define WM8350_GP8_PD 0x0100 +#define WM8350_GP7_PD 0x0080 +#define WM8350_GP6_PD 0x0040 +#define WM8350_GP5_PD 0x0020 +#define WM8350_GP4_PD 0x0010 +#define WM8350_GP3_PD 0x0008 +#define WM8350_GP2_PD 0x0004 +#define WM8350_GP1_PD 0x0002 +#define WM8350_GP0_PD 0x0001 + +/* +* R131 (0x83) - GPIO Interrupt Mode +*/ +#define WM8350_GP12_INTMODE 0x1000 +#define WM8350_GP11_INTMODE 0x0800 +#define WM8350_GP10_INTMODE 0x0400 +#define WM8350_GP9_INTMODE 0x0200 +#define WM8350_GP8_INTMODE 0x0100 +#define WM8350_GP7_INTMODE 0x0080 +#define WM8350_GP6_INTMODE 0x0040 +#define WM8350_GP5_INTMODE 0x0020 +#define WM8350_GP4_INTMODE 0x0010 +#define WM8350_GP3_INTMODE 0x0008 +#define WM8350_GP2_INTMODE 0x0004 +#define WM8350_GP1_INTMODE 0x0002 +#define WM8350_GP0_INTMODE 0x0001 + +/* +* R133 (0x85) - GPIO Control +*/ +#define WM8350_GP_DBTIME_MASK 0x00C0 + +/* +* R134 (0x86) - GPIO Configuration (i/o) +*/ +#define WM8350_GP12_DIR 0x1000 +#define WM8350_GP11_DIR 0x0800 +#define WM8350_GP10_DIR 0x0400 +#define WM8350_GP9_DIR 0x0200 +#define WM8350_GP8_DIR 0x0100 +#define WM8350_GP7_DIR 0x0080 +#define WM8350_GP6_DIR 0x0040 +#define WM8350_GP5_DIR 0x0020 +#define WM8350_GP4_DIR 0x0010 +#define WM8350_GP3_DIR 0x0008 +#define WM8350_GP2_DIR 0x0004 +#define WM8350_GP1_DIR 0x0002 +#define WM8350_GP0_DIR 0x0001 + +/* +* R135 (0x87) - GPIO Pin Polarity / Type +*/ +#define WM8350_GP12_CFG 0x1000 +#define WM8350_GP11_CFG 0x0800 +#define WM8350_GP10_CFG 0x0400 +#define WM8350_GP9_CFG 0x0200 +#define WM8350_GP8_CFG 0x0100 +#define WM8350_GP7_CFG 0x0080 +#define WM8350_GP6_CFG 0x0040 +#define WM8350_GP5_CFG 0x0020 +#define WM8350_GP4_CFG 0x0010 +#define WM8350_GP3_CFG 0x0008 +#define WM8350_GP2_CFG 0x0004 +#define WM8350_GP1_CFG 0x0002 +#define WM8350_GP0_CFG 0x0001 + +/* +* R140 (0x8C) - GPIO Function Select 1 +*/ +#define WM8350_GP3_FN_MASK 0xF000 +#define WM8350_GP2_FN_MASK 0x0F00 +#define WM8350_GP1_FN_MASK 0x00F0 +#define WM8350_GP0_FN_MASK 0x000F + +/* +* R141 (0x8D) - GPIO Function Select 2 +*/ +#define WM8350_GP7_FN_MASK 0xF000 +#define WM8350_GP6_FN_MASK 0x0F00 +#define WM8350_GP5_FN_MASK 0x00F0 +#define WM8350_GP4_FN_MASK 0x000F + +/* +* R142 (0x8E) - GPIO Function Select 3 +*/ +#define WM8350_GP11_FN_MASK 0xF000 +#define WM8350_GP10_FN_MASK 0x0F00 +#define WM8350_GP9_FN_MASK 0x00F0 +#define WM8350_GP8_FN_MASK 0x000F + +/* +* R143 (0x8F) - GPIO Function Select 4 +*/ +#define WM8350_GP12_FN_MASK 0x000F + +/* +* R230 (0xE6) - GPIO Pin Status +*/ +#define WM8350_GP12_LVL 0x1000 +#define WM8350_GP11_LVL 0x0800 +#define WM8350_GP10_LVL 0x0400 +#define WM8350_GP9_LVL 0x0200 +#define WM8350_GP8_LVL 0x0100 +#define WM8350_GP7_LVL 0x0080 +#define WM8350_GP6_LVL 0x0040 +#define WM8350_GP5_LVL 0x0020 +#define WM8350_GP4_LVL 0x0010 +#define WM8350_GP3_LVL 0x0008 +#define WM8350_GP2_LVL 0x0004 +#define WM8350_GP1_LVL 0x0002 +#define WM8350_GP0_LVL 0x0001 + +#endif
Signature · 1 line
1.5.6.5
PATCH 3/14 mfd: Add WM8350 PMIC register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/pmic.h | 699 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 699 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/pmic.h
include/linux/mfd/wm8350/pmic.h new file +699 -0
@@ -0,0 +1,699 @@ +/* +* pmic.h -- Power Managment Driver for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +*/ + +#ifndef __LINUX_MFD_WM8350_PMIC_H +#define __LINUX_MFD_WM8350_PMIC_H + +/* +* Register values. +*/ + +#define WM8350_CURRENT_SINK_DRIVER_A 0xAC +#define WM8350_CSA_FLASH_CONTROL 0xAD +#define WM8350_CURRENT_SINK_DRIVER_B 0xAE +#define WM8350_CSB_FLASH_CONTROL 0xAF +#define WM8350_DCDC_LDO_REQUESTED 0xB0 +#define WM8350_DCDC_ACTIVE_OPTIONS 0xB1 +#define WM8350_DCDC_SLEEP_OPTIONS 0xB2 +#define WM8350_POWER_CHECK_COMPARATOR 0xB3 +#define WM8350_DCDC1_CONTROL 0xB4 +#define WM8350_DCDC1_TIMEOUTS 0xB5 +#define WM8350_DCDC1_LOW_POWER 0xB6 +#define WM8350_DCDC2_CONTROL 0xB7 +#define WM8350_DCDC2_TIMEOUTS 0xB8 +#define WM8350_DCDC3_CONTROL 0xBA +#define WM8350_DCDC3_TIMEOUTS 0xBB +#define WM8350_DCDC3_LOW_POWER 0xBC +#define WM8350_DCDC4_CONTROL 0xBD +#define WM8350_DCDC4_TIMEOUTS 0xBE +#define WM8350_DCDC4_LOW_POWER 0xBF +#define WM8350_DCDC5_CONTROL 0xC0 +#define WM8350_DCDC5_TIMEOUTS 0xC1 +#define WM8350_DCDC6_CONTROL 0xC3 +#define WM8350_DCDC6_TIMEOUTS 0xC4 +#define WM8350_DCDC6_LOW_POWER 0xC5 +#define WM8350_LIMIT_SWITCH_CONTROL 0xC7 +#define WM8350_LDO1_CONTROL 0xC8 +#define WM8350_LDO1_TIMEOUTS 0xC9 +#define WM8350_LDO1_LOW_POWER 0xCA +#define WM8350_LDO2_CONTROL 0xCB +#define WM8350_LDO2_TIMEOUTS 0xCC +#define WM8350_LDO2_LOW_POWER 0xCD +#define WM8350_LDO3_CONTROL 0xCE +#define WM8350_LDO3_TIMEOUTS 0xCF +#define WM8350_LDO3_LOW_POWER 0xD0 +#define WM8350_LDO4_CONTROL 0xD1 +#define WM8350_LDO4_TIMEOUTS 0xD2 +#define WM8350_LDO4_LOW_POWER 0xD3 +#define WM8350_VCC_FAULT_MASKS 0xD7 +#define WM8350_MAIN_BANDGAP_CONTROL 0xD8 +#define WM8350_OSC_CONTROL 0xD9 +#define WM8350_RTC_TICK_CONTROL 0xDA +#define WM8350_SECURITY 0xDB +#define WM8350_RAM_BIST_1 0xDC +#define WM8350_DCDC_LDO_STATUS 0xE1 +#define WM8350_GPIO_PIN_STATUS 0xE6 + +#define WM8350_DCDC1_FORCE_PWM 0xF8 +#define WM8350_DCDC3_FORCE_PWM 0xFA +#define WM8350_DCDC4_FORCE_PWM 0xFB +#define WM8350_DCDC6_FORCE_PWM 0xFD + +/* +* R172 (0xAC) - Current Sink Driver A +*/ +#define WM8350_CS1_HIB_MODE 0x1000 +#define WM8350_CS1_HIB_MODE_MASK 0x1000 +#define WM8350_CS1_HIB_MODE_SHIFT 12 +#define WM8350_CS1_ISEL_MASK 0x003F +#define WM8350_CS1_ISEL_SHIFT 0 + +/* Bit values for R172 (0xAC) */ +#define WM8350_CS1_HIB_MODE_DISABLE 0 +#define WM8350_CS1_HIB_MODE_LEAVE 1 + +#define WM8350_CS1_ISEL_220M 0x3F + +/* +* R173 (0xAD) - CSA Flash control +*/ +#define WM8350_CS1_FLASH_MODE 0x8000 +#define WM8350_CS1_TRIGSRC 0x4000 +#define WM8350_CS1_DRIVE 0x2000 +#define WM8350_CS1_FLASH_DUR_MASK 0x0300 +#define WM8350_CS1_OFF_RAMP_MASK 0x0030 +#define WM8350_CS1_ON_RAMP_MASK 0x0003 + +/* +* R174 (0xAE) - Current Sink Driver B +*/ +#define WM8350_CS2_HIB_MODE 0x1000 +#define WM8350_CS2_ISEL_MASK 0x003F + +/* +* R175 (0xAF) - CSB Flash control +*/ +#define WM8350_CS2_FLASH_MODE 0x8000 +#define WM8350_CS2_TRIGSRC 0x4000 +#define WM8350_CS2_DRIVE 0x2000 +#define WM8350_CS2_FLASH_DUR_MASK 0x0300 +#define WM8350_CS2_OFF_RAMP_MASK 0x0030 +#define WM8350_CS2_ON_RAMP_MASK 0x0003 + +/* +* R176 (0xB0) - DCDC/LDO requested +*/ +#define WM8350_LS_ENA 0x8000 +#define WM8350_LDO4_ENA 0x0800 +#define WM8350_LDO3_ENA 0x0400 +#define WM8350_LDO2_ENA 0x0200 +#define WM8350_LDO1_ENA 0x0100 +#define WM8350_DC6_ENA 0x0020 +#define WM8350_DC5_ENA 0x0010 +#define WM8350_DC4_ENA 0x0008 +#define WM8350_DC3_ENA 0x0004 +#define WM8350_DC2_ENA 0x0002 +#define WM8350_DC1_ENA 0x0001 + +/* +* R177 (0xB1) - DCDC Active options +*/ +#define WM8350_PUTO_MASK 0x3000 +#define WM8350_PWRUP_DELAY_MASK 0x0300 +#define WM8350_DC6_ACTIVE 0x0020 +#define WM8350_DC4_ACTIVE 0x0008 +#define WM8350_DC3_ACTIVE 0x0004 +#define WM8350_DC1_ACTIVE 0x0001 + +/* +* R178 (0xB2) - DCDC Sleep options +*/ +#define WM8350_DC6_SLEEP 0x0020 +#define WM8350_DC4_SLEEP 0x0008 +#define WM8350_DC3_SLEEP 0x0004 +#define WM8350_DC1_SLEEP 0x0001 + +/* +* R179 (0xB3) - Power-check comparator +*/ +#define WM8350_PCCMP_ERRACT 0x4000 +#define WM8350_PCCMP_RAIL 0x0100 +#define WM8350_PCCMP_OFF_THR_MASK 0x0070 +#define WM8350_PCCMP_ON_THR_MASK 0x0007 + +/* +* R180 (0xB4) - DCDC1 Control +*/ +#define WM8350_DC1_OPFLT 0x0400 +#define WM8350_DC1_VSEL_MASK 0x007F +#define WM8350_DC1_VSEL_SHIFT 0 + +/* +* R181 (0xB5) - DCDC1 Timeouts +*/ +#define WM8350_DC1_ERRACT_MASK 0xC000 +#define WM8350_DC1_ERRACT_SHIFT 14 +#define WM8350_DC1_ENSLOT_MASK 0x3C00 +#define WM8350_DC1_ENSLOT_SHIFT 10 +#define WM8350_DC1_SDSLOT_MASK 0x03C0 +#define WM8350_DC1_UVTO_MASK 0x0030 +#define WM8350_DC1_SDSLOT_SHIFT 6 + +/* Bit values for R181 (0xB5) */ +#define WM8350_DC1_ERRACT_NONE 0 +#define WM8350_DC1_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_DC1_ERRACT_SHUTDOWN_SYS 2 + +/* +* R182 (0xB6) - DCDC1 Low Power +*/ +#define WM8350_DC1_HIB_MODE_MASK 0x7000 +#define WM8350_DC1_HIB_TRIG_MASK 0x0300 +#define WM8350_DC1_VIMG_MASK 0x007F + +/* +* R183 (0xB7) - DCDC2 Control +*/ +#define WM8350_DC2_MODE 0x4000 +#define WM8350_DC2_MODE_MASK 0x4000 +#define WM8350_DC2_MODE_SHIFT 14 +#define WM8350_DC2_HIB_MODE 0x1000 +#define WM8350_DC2_HIB_MODE_MASK 0x1000 +#define WM8350_DC2_HIB_MODE_SHIFT 12 +#define WM8350_DC2_HIB_TRIG_MASK 0x0300 +#define WM8350_DC2_HIB_TRIG_SHIFT 8 +#define WM8350_DC2_ILIM 0x0040 +#define WM8350_DC2_ILIM_MASK 0x0040 +#define WM8350_DC2_ILIM_SHIFT 6 +#define WM8350_DC2_RMP_MASK 0x0018 +#define WM8350_DC2_RMP_SHIFT 3 +#define WM8350_DC2_FBSRC_MASK 0x0003 +#define WM8350_DC2_FBSRC_SHIFT 0 + +/* Bit values for R183 (0xB7) */ +#define WM8350_DC2_MODE_BOOST 0 +#define WM8350_DC2_MODE_SWITCH 1 + +#define WM8350_DC2_HIB_MODE_ACTIVE 1 +#define WM8350_DC2_HIB_MODE_DISABLE 0 + +#define WM8350_DC2_HIB_TRIG_NONE 0 +#define WM8350_DC2_HIB_TRIG_LPWR1 1 +#define WM8350_DC2_HIB_TRIG_LPWR2 2 +#define WM8350_DC2_HIB_TRIG_LPWR3 3 + +#define WM8350_DC2_ILIM_HIGH 0 +#define WM8350_DC2_ILIM_LOW 1 + +#define WM8350_DC2_RMP_30V 0 +#define WM8350_DC2_RMP_20V 1 +#define WM8350_DC2_RMP_10V 2 +#define WM8350_DC2_RMP_5V 3 + +#define WM8350_DC2_FBSRC_FB2 0 +#define WM8350_DC2_FBSRC_ISINKA 1 +#define WM8350_DC2_FBSRC_ISINKB 2 +#define WM8350_DC2_FBSRC_USB 3 + +/* +* R184 (0xB8) - DCDC2 Timeouts +*/ +#define WM8350_DC2_ERRACT_MASK 0xC000 +#define WM8350_DC2_ERRACT_SHIFT 14 +#define WM8350_DC2_ENSLOT_MASK 0x3C00 +#define WM8350_DC2_ENSLOT_SHIFT 10 +#define WM8350_DC2_SDSLOT_MASK 0x03C0 +#define WM8350_DC2_UVTO_MASK 0x0030 + +/* Bit values for R184 (0xB8) */ +#define WM8350_DC2_ERRACT_NONE 0 +#define WM8350_DC2_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_DC2_ERRACT_SHUTDOWN_SYS 2 + +/* +* R186 (0xBA) - DCDC3 Control +*/ +#define WM8350_DC3_OPFLT 0x0400 +#define WM8350_DC3_VSEL_MASK 0x007F +#define WM8350_DC3_VSEL_SHIFT 0 + +/* +* R187 (0xBB) - DCDC3 Timeouts +*/ +#define WM8350_DC3_ERRACT_MASK 0xC000 +#define WM8350_DC3_ERRACT_SHIFT 14 +#define WM8350_DC3_ENSLOT_MASK 0x3C00 +#define WM8350_DC3_ENSLOT_SHIFT 10 +#define WM8350_DC3_SDSLOT_MASK 0x03C0 +#define WM8350_DC3_UVTO_MASK 0x0030 +#define WM8350_DC3_SDSLOT_SHIFT 6 + +/* Bit values for R187 (0xBB) */ +#define WM8350_DC3_ERRACT_NONE 0 +#define WM8350_DC3_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_DC3_ERRACT_SHUTDOWN_SYS 2 +/* +* R188 (0xBC) - DCDC3 Low Power +*/ +#define WM8350_DC3_HIB_MODE_MASK 0x7000 +#define WM8350_DC3_HIB_TRIG_MASK 0x0300 +#define WM8350_DC3_VIMG_MASK 0x007F + +/* +* R189 (0xBD) - DCDC4 Control +*/ +#define WM8350_DC4_OPFLT 0x0400 +#define WM8350_DC4_VSEL_MASK 0x007F +#define WM8350_DC4_VSEL_SHIFT 0 + +/* +* R190 (0xBE) - DCDC4 Timeouts +*/ +#define WM8350_DC4_ERRACT_MASK 0xC000 +#define WM8350_DC4_ERRACT_SHIFT 14 +#define WM8350_DC4_ENSLOT_MASK 0x3C00 +#define WM8350_DC4_ENSLOT_SHIFT 10 +#define WM8350_DC4_SDSLOT_MASK 0x03C0 +#define WM8350_DC4_UVTO_MASK 0x0030 +#define WM8350_DC4_SDSLOT_SHIFT 6 + +/* Bit values for R190 (0xBE) */ +#define WM8350_DC4_ERRACT_NONE 0 +#define WM8350_DC4_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_DC4_ERRACT_SHUTDOWN_SYS 2 + +/* +* R191 (0xBF) - DCDC4 Low Power +*/ +#define WM8350_DC4_HIB_MODE_MASK 0x7000 +#define WM8350_DC4_HIB_TRIG_MASK 0x0300 +#define WM8350_DC4_VIMG_MASK 0x007F + +/* +* R192 (0xC0) - DCDC5 Control +*/ +#define WM8350_DC5_MODE 0x4000 +#define WM8350_DC5_MODE_MASK 0x4000 +#define WM8350_DC5_MODE_SHIFT 14 +#define WM8350_DC5_HIB_MODE 0x1000 +#define WM8350_DC5_HIB_MODE_MASK 0x1000 +#define WM8350_DC5_HIB_MODE_SHIFT 12 +#define WM8350_DC5_HIB_TRIG_MASK 0x0300 +#define WM8350_DC5_HIB_TRIG_SHIFT 8 +#define WM8350_DC5_ILIM 0x0040 +#define WM8350_DC5_ILIM_MASK 0x0040 +#define WM8350_DC5_ILIM_SHIFT 6 +#define WM8350_DC5_RMP_MASK 0x0018 +#define WM8350_DC5_RMP_SHIFT 3 +#define WM8350_DC5_FBSRC_MASK 0x0003 +#define WM8350_DC5_FBSRC_SHIFT 0 + +/* Bit values for R192 (0xC0) */ +#define WM8350_DC5_MODE_BOOST 0 +#define WM8350_DC5_MODE_SWITCH 1 + +#define WM8350_DC5_HIB_MODE_ACTIVE 1 +#define WM8350_DC5_HIB_MODE_DISABLE 0 + +#define WM8350_DC5_HIB_TRIG_NONE 0 +#define WM8350_DC5_HIB_TRIG_LPWR1 1 +#define WM8350_DC5_HIB_TRIG_LPWR2 2 +#define WM8350_DC5_HIB_TRIG_LPWR3 3 + +#define WM8350_DC5_ILIM_HIGH 0 +#define WM8350_DC5_ILIM_LOW 1 + +#define WM8350_DC5_RMP_30V 0 +#define WM8350_DC5_RMP_20V 1 +#define WM8350_DC5_RMP_10V 2 +#define WM8350_DC5_RMP_5V 3 + +#define WM8350_DC5_FBSRC_FB2 0 +#define WM8350_DC5_FBSRC_ISINKA 1 +#define WM8350_DC5_FBSRC_ISINKB 2 +#define WM8350_DC5_FBSRC_USB 3 + +/* +* R193 (0xC1) - DCDC5 Timeouts +*/ +#define WM8350_DC5_ERRACT_MASK 0xC000 +#define WM8350_DC5_ERRACT_SHIFT 14 +#define WM8350_DC5_ENSLOT_MASK 0x3C00 +#define WM8350_DC5_ENSLOT_SHIFT 10 +#define WM8350_DC5_SDSLOT_MASK 0x03C0 +#define WM8350_DC5_UVTO_MASK 0x0030 +#define WM8350_DC5_SDSLOT_SHIFT 6 + +/* Bit values for R193 (0xC1) */ +#define WM8350_DC5_ERRACT_NONE 0 +#define WM8350_DC5_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_DC5_ERRACT_SHUTDOWN_SYS 2 + +/* +* R195 (0xC3) - DCDC6 Control +*/ +#define WM8350_DC6_OPFLT 0x0400 +#define WM8350_DC6_VSEL_MASK 0x007F +#define WM8350_DC6_VSEL_SHIFT 0 + +/* +* R196 (0xC4) - DCDC6 Timeouts +*/ +#define WM8350_DC6_ERRACT_MASK 0xC000 +#define WM8350_DC6_ERRACT_SHIFT 14 +#define WM8350_DC6_ENSLOT_MASK 0x3C00 +#define WM8350_DC6_ENSLOT_SHIFT 10 +#define WM8350_DC6_SDSLOT_MASK 0x03C0 +#define WM8350_DC6_UVTO_MASK 0x0030 +#define WM8350_DC6_SDSLOT_SHIFT 6 + +/* Bit values for R196 (0xC4) */ +#define WM8350_DC6_ERRACT_NONE 0 +#define WM8350_DC6_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_DC6_ERRACT_SHUTDOWN_SYS 2 + +/* +* R197 (0xC5) - DCDC6 Low Power +*/ +#define WM8350_DC6_HIB_MODE_MASK 0x7000 +#define WM8350_DC6_HIB_TRIG_MASK 0x0300 +#define WM8350_DC6_VIMG_MASK 0x007F + +/* +* R199 (0xC7) - Limit Switch Control +*/ +#define WM8350_LS_ERRACT_MASK 0xC000 +#define WM8350_LS_ERRACT_SHIFT 14 +#define WM8350_LS_ENSLOT_MASK 0x3C00 +#define WM8350_LS_ENSLOT_SHIFT 10 +#define WM8350_LS_SDSLOT_MASK 0x03C0 +#define WM8350_LS_SDSLOT_SHIFT 6 +#define WM8350_LS_HIB_MODE 0x0010 +#define WM8350_LS_HIB_MODE_MASK 0x0010 +#define WM8350_LS_HIB_MODE_SHIFT 4 +#define WM8350_LS_HIB_PROT 0x0002 +#define WM8350_LS_HIB_PROT_MASK 0x0002 +#define WM8350_LS_HIB_PROT_SHIFT 1 +#define WM8350_LS_PROT 0x0001 +#define WM8350_LS_PROT_MASK 0x0001 +#define WM8350_LS_PROT_SHIFT 0 + +/* Bit values for R199 (0xC7) */ +#define WM8350_LS_ERRACT_NONE 0 +#define WM8350_LS_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_LS_ERRACT_SHUTDOWN_SYS 2 + +/* +* R200 (0xC8) - LDO1 Control +*/ +#define WM8350_LDO1_SWI 0x4000 +#define WM8350_LDO1_OPFLT 0x0400 +#define WM8350_LDO1_VSEL_MASK 0x001F +#define WM8350_LDO1_VSEL_SHIFT 0 + +/* +* R201 (0xC9) - LDO1 Timeouts +*/ +#define WM8350_LDO1_ERRACT_MASK 0xC000 +#define WM8350_LDO1_ERRACT_SHIFT 14 +#define WM8350_LDO1_ENSLOT_MASK 0x3C00 +#define WM8350_LDO1_ENSLOT_SHIFT 10 +#define WM8350_LDO1_SDSLOT_MASK 0x03C0 +#define WM8350_LDO1_UVTO_MASK 0x0030 +#define WM8350_LDO1_SDSLOT_SHIFT 6 + +/* Bit values for R201 (0xC9) */ +#define WM8350_LDO1_ERRACT_NONE 0 +#define WM8350_LDO1_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_LDO1_ERRACT_SHUTDOWN_SYS 2 + +/* +* R202 (0xCA) - LDO1 Low Power +*/ +#define WM8350_LDO1_HIB_MODE_MASK 0x3000 +#define WM8350_LDO1_HIB_TRIG_MASK 0x0300 +#define WM8350_LDO1_VIMG_MASK 0x001F +#define WM8350_LDO1_HIB_MODE_DIS (0x1 << 12) + + +/* +* R203 (0xCB) - LDO2 Control +*/ +#define WM8350_LDO2_SWI 0x4000 +#define WM8350_LDO2_OPFLT 0x0400 +#define WM8350_LDO2_VSEL_MASK 0x001F +#define WM8350_LDO2_VSEL_SHIFT 0 + +/* +* R204 (0xCC) - LDO2 Timeouts +*/ +#define WM8350_LDO2_ERRACT_MASK 0xC000 +#define WM8350_LDO2_ERRACT_SHIFT 14 +#define WM8350_LDO2_ENSLOT_MASK 0x3C00 +#define WM8350_LDO2_ENSLOT_SHIFT 10 +#define WM8350_LDO2_SDSLOT_MASK 0x03C0 +#define WM8350_LDO2_SDSLOT_SHIFT 6 + +/* Bit values for R204 (0xCC) */ +#define WM8350_LDO2_ERRACT_NONE 0 +#define WM8350_LDO2_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_LDO2_ERRACT_SHUTDOWN_SYS 2 + +/* +* R205 (0xCD) - LDO2 Low Power +*/ +#define WM8350_LDO2_HIB_MODE_MASK 0x3000 +#define WM8350_LDO2_HIB_TRIG_MASK 0x0300 +#define WM8350_LDO2_VIMG_MASK 0x001F + +/* +* R206 (0xCE) - LDO3 Control +*/ +#define WM8350_LDO3_SWI 0x4000 +#define WM8350_LDO3_OPFLT 0x0400 +#define WM8350_LDO3_VSEL_MASK 0x001F +#define WM8350_LDO3_VSEL_SHIFT 0 + +/* +* R207 (0xCF) - LDO3 Timeouts +*/ +#define WM8350_LDO3_ERRACT_MASK 0xC000 +#define WM8350_LDO3_ERRACT_SHIFT 14 +#define WM8350_LDO3_ENSLOT_MASK 0x3C00 +#define WM8350_LDO3_ENSLOT_SHIFT 10 +#define WM8350_LDO3_SDSLOT_MASK 0x03C0 +#define WM8350_LDO3_UVTO_MASK 0x0030 +#define WM8350_LDO3_SDSLOT_SHIFT 6 + +/* Bit values for R207 (0xCF) */ +#define WM8350_LDO3_ERRACT_NONE 0 +#define WM8350_LDO3_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_LDO3_ERRACT_SHUTDOWN_SYS 2 + +/* +* R208 (0xD0) - LDO3 Low Power +*/ +#define WM8350_LDO3_HIB_MODE_MASK 0x3000 +#define WM8350_LDO3_HIB_TRIG_MASK 0x0300 +#define WM8350_LDO3_VIMG_MASK 0x001F + +/* +* R209 (0xD1) - LDO4 Control +*/ +#define WM8350_LDO4_SWI 0x4000 +#define WM8350_LDO4_OPFLT 0x0400 +#define WM8350_LDO4_VSEL_MASK 0x001F +#define WM8350_LDO4_VSEL_SHIFT 0 + +/* +* R210 (0xD2) - LDO4 Timeouts +*/ +#define WM8350_LDO4_ERRACT_MASK 0xC000 +#define WM8350_LDO4_ERRACT_SHIFT 14 +#define WM8350_LDO4_ENSLOT_MASK 0x3C00 +#define WM8350_LDO4_ENSLOT_SHIFT 10 +#define WM8350_LDO4_SDSLOT_MASK 0x03C0 +#define WM8350_LDO4_UVTO_MASK 0x0030 +#define WM8350_LDO4_SDSLOT_SHIFT 6 + +/* Bit values for R210 (0xD2) */ +#define WM8350_LDO4_ERRACT_NONE 0 +#define WM8350_LDO4_ERRACT_SHUTDOWN_CONV 1 +#define WM8350_LDO4_ERRACT_SHUTDOWN_SYS 2 + +/* +* R211 (0xD3) - LDO4 Low Power +*/ +#define WM8350_LDO4_HIB_MODE_MASK 0x3000 +#define WM8350_LDO4_HIB_TRIG_MASK 0x0300 +#define WM8350_LDO4_VIMG_MASK 0x001F + +/* +* R215 (0xD7) - VCC_FAULT Masks +*/ +#define WM8350_LS_FAULT 0x8000 +#define WM8350_LDO4_FAULT 0x0800 +#define WM8350_LDO3_FAULT 0x0400 +#define WM8350_LDO2_FAULT 0x0200 +#define WM8350_LDO1_FAULT 0x0100 +#define WM8350_DC6_FAULT 0x0020 +#define WM8350_DC5_FAULT 0x0010 +#define WM8350_DC4_FAULT 0x0008 +#define WM8350_DC3_FAULT 0x0004 +#define WM8350_DC2_FAULT 0x0002 +#define WM8350_DC1_FAULT 0x0001 + +/* +* R216 (0xD8) - Main Bandgap Control +*/ +#define WM8350_MBG_LOAD_FUSES 0x8000 +#define WM8350_MBG_FUSE_WPREP 0x4000 +#define WM8350_MBG_FUSE_WRITE 0x2000 +#define WM8350_MBG_FUSE_TRIM_MASK 0x1F00 +#define WM8350_MBG_TRIM_SRC 0x0020 +#define WM8350_MBG_USER_TRIM_MASK 0x001F + +/* +* R217 (0xD9) - OSC Control +*/ +#define WM8350_OSC_LOAD_FUSES 0x8000 +#define WM8350_OSC_FUSE_WPREP 0x4000 +#define WM8350_OSC_FUSE_WRITE 0x2000 +#define WM8350_OSC_FUSE_TRIM_MASK 0x0F00 +#define WM8350_OSC_TRIM_SRC 0x0020 +#define WM8350_OSC_USER_TRIM_MASK 0x000F + +/* +* R248 (0xF8) - DCDC1 Force PWM +*/ +#define WM8350_DCDC1_FORCE_PWM_ENA 0x0010 + +/* +* R250 (0xFA) - DCDC3 Force PWM +*/ +#define WM8350_DCDC3_FORCE_PWM_ENA 0x0010 + +/* +* R251 (0xFB) - DCDC4 Force PWM +*/ +#define WM8350_DCDC4_FORCE_PWM_ENA 0x0010 + +/* +* R253 (0xFD) - DCDC1 Force PWM +*/ +#define WM8350_DCDC6_FORCE_PWM_ENA 0x0010 + +/* +* DCDC's +*/ +#define WM8350_DCDC_1 0 +#define WM8350_DCDC_2 1 +#define WM8350_DCDC_3 2 +#define WM8350_DCDC_4 3 +#define WM8350_DCDC_5 4 +#define WM8350_DCDC_6 5 + +/* DCDC modes */ +#define WM8350_DCDC_ACTIVE_STANDBY 0 +#define WM8350_DCDC_ACTIVE_PULSE 1 +#define WM8350_DCDC_SLEEP_NORMAL 0 +#define WM8350_DCDC_SLEEP_LOW 1 + +/* DCDC Low power (Hibernate) mode */ +#define WM8350_DCDC_HIB_MODE_CUR (0 << 12) +#define WM8350_DCDC_HIB_MODE_IMAGE (1 << 12) +#define WM8350_DCDC_HIB_MODE_STANDBY (2 << 12) +#define WM8350_DCDC_HIB_MODE_LDO (4 << 12) +#define WM8350_DCDC_HIB_MODE_LDO_IM (5 << 12) +#define WM8350_DCDC_HIB_MODE_DIS (7 << 12) +#define WM8350_DCDC_HIB_MODE_MASK (7 << 12) + +/* DCDC Low Power (Hibernate) signal */ +#define WM8350_DCDC_HIB_SIG_REG (0 << 8) +#define WM8350_DCDC_HIB_SIG_LPWR1 (1 << 8) +#define WM8350_DCDC_HIB_SIG_LPWR2 (2 << 8) +#define WM8350_DCDC_HIB_SIG_LPWR3 (3 << 8) + +/* LDO Low power (Hibernate) mode */ +#define WM8350_LDO_HIB_MODE_IMAGE (0 << 0) +#define WM8350_LDO_HIB_MODE_DIS (1 << 0) + +/* LDO Low Power (Hibernate) signal */ +#define WM8350_LDO_HIB_SIG_REG (0 << 8) +#define WM8350_LDO_HIB_SIG_LPWR1 (1 << 8) +#define WM8350_LDO_HIB_SIG_LPWR2 (2 << 8) +#define WM8350_LDO_HIB_SIG_LPWR3 (3 << 8) + +/* +* LDOs +*/ +#define WM8350_LDO_1 6 +#define WM8350_LDO_2 7 +#define WM8350_LDO_3 8 +#define WM8350_LDO_4 9 + +/* +* ISINKs +*/ +#define WM8350_ISINK_A 10 +#define WM8350_ISINK_B 11 + +#define WM8350_ISINK_MODE_BOOST 0 +#define WM8350_ISINK_MODE_SWITCH 1 +#define WM8350_ISINK_ILIM_NORMAL 0 +#define WM8350_ISINK_ILIM_LOW 1 + +#define WM8350_ISINK_FLASH_DISABLE 0 +#define WM8350_ISINK_FLASH_ENABLE 1 +#define WM8350_ISINK_FLASH_TRIG_BIT 0 +#define WM8350_ISINK_FLASH_TRIG_GPIO 1 +#define WM8350_ISINK_FLASH_MODE_EN (1 << 13) +#define WM8350_ISINK_FLASH_MODE_DIS (0 << 13) +#define WM8350_ISINK_FLASH_DUR_32MS (0 << 8) +#define WM8350_ISINK_FLASH_DUR_64MS (1 << 8) +#define WM8350_ISINK_FLASH_DUR_96MS (2 << 8) +#define WM8350_ISINK_FLASH_DUR_1024MS (3 << 8) +#define WM8350_ISINK_FLASH_ON_INSTANT (0 << 4) +#define WM8350_ISINK_FLASH_ON_0_25S (1 << 4) +#define WM8350_ISINK_FLASH_ON_0_50S (2 << 4) +#define WM8350_ISINK_FLASH_ON_1_00S (3 << 4) +#define WM8350_ISINK_FLASH_ON_1_95S (1 << 4) +#define WM8350_ISINK_FLASH_ON_3_91S (2 << 4) +#define WM8350_ISINK_FLASH_ON_7_80S (3 << 4) +#define WM8350_ISINK_FLASH_OFF_INSTANT (0 << 0) +#define WM8350_ISINK_FLASH_OFF_0_25S (1 << 0) +#define WM8350_ISINK_FLASH_OFF_0_50S (2 << 0) +#define WM8350_ISINK_FLASH_OFF_1_00S (3 << 0) +#define WM8350_ISINK_FLASH_OFF_1_95S (1 << 0) +#define WM8350_ISINK_FLASH_OFF_3_91S (2 << 0) +#define WM8350_ISINK_FLASH_OFF_7_80S (3 << 0) + +/* +* Regulator Interrupts. +*/ +#define WM8350_IRQ_CS1 13 +#define WM8350_IRQ_CS2 14 +#define WM8350_IRQ_UV_LDO4 25 +#define WM8350_IRQ_UV_LDO3 26 +#define WM8350_IRQ_UV_LDO2 27 +#define WM8350_IRQ_UV_LDO1 28 +#define WM8350_IRQ_UV_DC6 29 +#define WM8350_IRQ_UV_DC5 30 +#define WM8350_IRQ_UV_DC4 31 +#define WM8350_IRQ_UV_DC3 32 +#define WM8350_IRQ_UV_DC2 33 +#define WM8350_IRQ_UV_DC1 34 +#define WM8350_IRQ_OC_LS 35 + +#define NUM_WM8350_REGULATORS 12 + +#endif
Signature · 1 line
1.5.6.5
PATCH 4/14 mfd: Add WM8350 PMU register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/supply.h | 105 +++++++++++++++++++++++++++++++++++++ 1 files changed, 105 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/supply.h
include/linux/mfd/wm8350/supply.h new file +105 -0
@@ -0,0 +1,105 @@ +/* +* supply.h -- Power Supply Driver for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +*/ + +#ifndef __LINUX_MFD_WM8350_SUPPLY_H_ +#define __LINUX_MFD_WM8350_SUPPLY_H_ + +/* +* Charger registers +*/ +#define WM8350_BATTERY_CHARGER_CONTROL_1 0xA8 +#define WM8350_BATTERY_CHARGER_CONTROL_2 0xA9 +#define WM8350_BATTERY_CHARGER_CONTROL_3 0xAA + +/* +* R168 (0xA8) - Battery Charger Control 1 +*/ +#define WM8350_CHG_ENA_R168 0x8000 +#define WM8350_CHG_THR 0x2000 +#define WM8350_CHG_EOC_SEL_MASK 0x1C00 +#define WM8350_CHG_TRICKLE_TEMP_CHOKE 0x0200 +#define WM8350_CHG_TRICKLE_USB_CHOKE 0x0100 +#define WM8350_CHG_RECOVER_T 0x0080 +#define WM8350_CHG_END_ACT 0x0040 +#define WM8350_CHG_FAST 0x0020 +#define WM8350_CHG_FAST_USB_THROTTLE 0x0010 +#define WM8350_CHG_NTC_MON 0x0008 +#define WM8350_CHG_BATT_HOT_MON 0x0004 +#define WM8350_CHG_BATT_COLD_MON 0x0002 +#define WM8350_CHG_CHIP_TEMP_MON 0x0001 + +/* +* R169 (0xA9) - Battery Charger Control 2 +*/ +#define WM8350_CHG_ACTIVE 0x8000 +#define WM8350_CHG_PAUSE 0x4000 +#define WM8350_CHG_STS_MASK 0x3000 +#define WM8350_CHG_TIME_MASK 0x0F00 +#define WM8350_CHG_MASK_WALL_FB 0x0080 +#define WM8350_CHG_TRICKLE_SEL 0x0040 +#define WM8350_CHG_VSEL_MASK 0x0030 +#define WM8350_CHG_ISEL_MASK 0x000F +#define WM8350_CHG_STS_OFF 0x0000 +#define WM8350_CHG_STS_TRICKLE 0x1000 +#define WM8350_CHG_STS_FAST 0x2000 + +/* +* R170 (0xAA) - Battery Charger Control 3 +*/ +#define WM8350_CHG_THROTTLE_T_MASK 0x0060 +#define WM8350_CHG_SMART 0x0010 +#define WM8350_CHG_TIMER_ADJT_MASK 0x000F + +/* +* Charger Interrupts +*/ +#define WM8350_IRQ_CHG_BAT_HOT 0 +#define WM8350_IRQ_CHG_BAT_COLD 1 +#define WM8350_IRQ_CHG_BAT_FAIL 2 +#define WM8350_IRQ_CHG_TO 3 +#define WM8350_IRQ_CHG_END 4 +#define WM8350_IRQ_CHG_START 5 +#define WM8350_IRQ_CHG_FAST_RDY 6 +#define WM8350_IRQ_CHG_VBATT_LT_3P9 10 +#define WM8350_IRQ_CHG_VBATT_LT_3P1 11 +#define WM8350_IRQ_CHG_VBATT_LT_2P85 12 + +/* +* Charger Policy +*/ +#define WM8350_CHG_TRICKLE_50mA (0 << 6) +#define WM8350_CHG_TRICKLE_100mA (1 << 6) +#define WM8350_CHG_4_05V (0 << 4) +#define WM8350_CHG_4_10V (1 << 4) +#define WM8350_CHG_4_15V (2 << 4) +#define WM8350_CHG_4_20V (3 << 4) +#define WM8350_CHG_FAST_LIMIT_mA (x) ((x / 50) & 0xf) +#define WM8350_CHG_EOC_mA (x) (((x - 10) & 0x7) << 10) +#define WM8350_CHG_TRICKLE_3_1V (0 << 13) +#define WM8350_CHG_TRICKLE_3_9V (1 << 13) + +/* +* Supply Registers. +*/ +#define WM8350_USB_VOLTAGE_READBACK 0x9C +#define WM8350_LINE_VOLTAGE_READBACK 0x9D +#define WM8350_BATT_VOLTAGE_READBACK 0x9E + +/* +* Supply Interrupts. +*/ +#define WM8350_IRQ_USB_LIMIT 15 +#define WM8350_IRQ_EXT_USB_FB 36 +#define WM8350_IRQ_EXT_WALL_FB 37 +#define WM8350_IRQ_EXT_BAT_FB 38 + +#endif
Signature · 1 line
1.5.6.5
PATCH 5/14 mfd: Add WM8350 comparator register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/comparator.h | 167 +++++++++++++++++++++++++++++++++ 1 files changed, 167 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/comparator.h
include/linux/mfd/wm8350/comparator.h new file +167 -0
@@ -0,0 +1,167 @@ +/* +* comparator.h -- Comparator Aux ADC for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +*/ + +#ifndef __LINUX_MFD_WM8350_COMPARATOR_H_ +#define __LINUX_MFD_WM8350_COMPARATOR_H_ + +/* +* Registers +*/ + +#define WM8350_DIGITISER_CONTROL_1 0x90 +#define WM8350_DIGITISER_CONTROL_2 0x91 +#define WM8350_AUX1_READBACK 0x98 +#define WM8350_AUX2_READBACK 0x99 +#define WM8350_AUX3_READBACK 0x9A +#define WM8350_AUX4_READBACK 0x9B +#define WM8350_CHIP_TEMP_READBACK 0x9F +#define WM8350_GENERIC_COMPARATOR_CONTROL 0xA3 +#define WM8350_GENERIC_COMPARATOR_1 0xA4 +#define WM8350_GENERIC_COMPARATOR_2 0xA5 +#define WM8350_GENERIC_COMPARATOR_3 0xA6 +#define WM8350_GENERIC_COMPARATOR_4 0xA7 + +/* +* R144 (0x90) - Digitiser Control (1) +*/ +#define WM8350_AUXADC_CTC 0x4000 +#define WM8350_AUXADC_POLL 0x2000 +#define WM8350_AUXADC_HIB_MODE 0x1000 +#define WM8350_AUXADC_SEL8 0x0080 +#define WM8350_AUXADC_SEL7 0x0040 +#define WM8350_AUXADC_SEL6 0x0020 +#define WM8350_AUXADC_SEL5 0x0010 +#define WM8350_AUXADC_SEL4 0x0008 +#define WM8350_AUXADC_SEL3 0x0004 +#define WM8350_AUXADC_SEL2 0x0002 +#define WM8350_AUXADC_SEL1 0x0001 + +/* +* R145 (0x91) - Digitiser Control (2) +*/ +#define WM8350_AUXADC_MASKMODE_MASK 0x3000 +#define WM8350_AUXADC_CRATE_MASK 0x0700 +#define WM8350_AUXADC_CAL 0x0004 +#define WM8350_AUX_RBMODE 0x0002 +#define WM8350_AUXADC_WAIT 0x0001 + +/* +* R152 (0x98) - AUX1 Readback +*/ +#define WM8350_AUXADC_SCALE1_MASK 0x6000 +#define WM8350_AUXADC_REF1 0x1000 +#define WM8350_AUXADC_DATA1_MASK 0x0FFF + +/* +* R153 (0x99) - AUX2 Readback +*/ +#define WM8350_AUXADC_SCALE2_MASK 0x6000 +#define WM8350_AUXADC_REF2 0x1000 +#define WM8350_AUXADC_DATA2_MASK 0x0FFF + +/* +* R154 (0x9A) - AUX3 Readback +*/ +#define WM8350_AUXADC_SCALE3_MASK 0x6000 +#define WM8350_AUXADC_REF3 0x1000 +#define WM8350_AUXADC_DATA3_MASK 0x0FFF + +/* +* R155 (0x9B) - AUX4 Readback +*/ +#define WM8350_AUXADC_SCALE4_MASK 0x6000 +#define WM8350_AUXADC_REF4 0x1000 +#define WM8350_AUXADC_DATA4_MASK 0x0FFF + +/* +* R156 (0x9C) - USB Voltage Readback +*/ +#define WM8350_AUXADC_DATA_USB_MASK 0x0FFF + +/* +* R157 (0x9D) - LINE Voltage Readback +*/ +#define WM8350_AUXADC_DATA_LINE_MASK 0x0FFF + +/* +* R158 (0x9E) - BATT Voltage Readback +*/ +#define WM8350_AUXADC_DATA_BATT_MASK 0x0FFF + +/* +* R159 (0x9F) - Chip Temp Readback +*/ +#define WM8350_AUXADC_DATA_CHIPTEMP_MASK 0x0FFF + +/* +* R163 (0xA3) - Generic Comparator Control +*/ +#define WM8350_DCMP4_ENA 0x0008 +#define WM8350_DCMP3_ENA 0x0004 +#define WM8350_DCMP2_ENA 0x0002 +#define WM8350_DCMP1_ENA 0x0001 + +/* +* R164 (0xA4) - Generic comparator 1 +*/ +#define WM8350_DCMP1_SRCSEL_MASK 0xE000 +#define WM8350_DCMP1_GT 0x1000 +#define WM8350_DCMP1_THR_MASK 0x0FFF + +/* +* R165 (0xA5) - Generic comparator 2 +*/ +#define WM8350_DCMP2_SRCSEL_MASK 0xE000 +#define WM8350_DCMP2_GT 0x1000 +#define WM8350_DCMP2_THR_MASK 0x0FFF + +/* +* R166 (0xA6) - Generic comparator 3 +*/ +#define WM8350_DCMP3_SRCSEL_MASK 0xE000 +#define WM8350_DCMP3_GT 0x1000 +#define WM8350_DCMP3_THR_MASK 0x0FFF + +/* +* R167 (0xA7) - Generic comparator 4 +*/ +#define WM8350_DCMP4_SRCSEL_MASK 0xE000 +#define WM8350_DCMP4_GT 0x1000 +#define WM8350_DCMP4_THR_MASK 0x0FFF + +/* +* Interrupts. +*/ +#define WM8350_IRQ_AUXADC_DATARDY 16 +#define WM8350_IRQ_AUXADC_DCOMP4 17 +#define WM8350_IRQ_AUXADC_DCOMP3 18 +#define WM8350_IRQ_AUXADC_DCOMP2 19 +#define WM8350_IRQ_AUXADC_DCOMP1 20 +#define WM8350_IRQ_SYS_HYST_COMP_FAIL 21 +#define WM8350_IRQ_SYS_CHIP_GT115 22 +#define WM8350_IRQ_SYS_CHIP_GT140 23 + +/* +* USB/2, LINE & BATT = ((VRTC * 2) / 4095)) * 10e6 uV +* Where VRTC = 2.7 V +*/ +#define WM8350_AUX_COEFF 1319 + +#define WM8350_AUXADC_AUX1 0 +#define WM8350_AUXADC_AUX2 1 +#define WM8350_AUXADC_AUX3 2 +#define WM8350_AUXADC_AUX4 3 +#define WM8350_AUXADC_USB 4 +#define WM8350_AUXADC_LINE 5 +#define WM8350_AUXADC_BATT 6 +#define WM8350_AUXADC_TEMP 7 + +#endif
Signature · 1 line
1.5.6.5
PATCH 6/14 mfd: Add WM8350 RTC register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/rtc.h | 260 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 260 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/rtc.h
include/linux/mfd/wm8350/rtc.h new file +260 -0
@@ -0,0 +1,260 @@ +/* +* rtc.h -- RTC driver for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +*/ + +#ifndef __LINUX_MFD_WM8350_RTC_H +#define __LINUX_MFD_WM8350_RTC_H + +/* +* Register values. +*/ +#define WM8350_RTC_SECONDS_MINUTES 0x10 +#define WM8350_RTC_HOURS_DAY 0x11 +#define WM8350_RTC_DATE_MONTH 0x12 +#define WM8350_RTC_YEAR 0x13 +#define WM8350_ALARM_SECONDS_MINUTES 0x14 +#define WM8350_ALARM_HOURS_DAY 0x15 +#define WM8350_ALARM_DATE_MONTH 0x16 +#define WM8350_RTC_TIME_CONTROL 0x17 + +/* +* R16 (0x10) - RTC Seconds/Minutes +*/ +#define WM8350_RTC_MINS_MASK 0x7F00 +#define WM8350_RTC_MINS_SHIFT 8 +#define WM8350_RTC_SECS_MASK 0x007F +#define WM8350_RTC_SECS_SHIFT 0 + +/* +* R17 (0x11) - RTC Hours/Day +*/ +#define WM8350_RTC_DAY_MASK 0x0700 +#define WM8350_RTC_DAY_SHIFT 8 +#define WM8350_RTC_HPM_MASK 0x0020 +#define WM8350_RTC_HPM_SHIFT 5 +#define WM8350_RTC_HRS_MASK 0x001F +#define WM8350_RTC_HRS_SHIFT 0 + +/* Bit values for R21 (0x15) */ +#define WM8350_RTC_DAY_SUN 1 +#define WM8350_RTC_DAY_MON 2 +#define WM8350_RTC_DAY_TUE 3 +#define WM8350_RTC_DAY_WED 4 +#define WM8350_RTC_DAY_THU 5 +#define WM8350_RTC_DAY_FRI 6 +#define WM8350_RTC_DAY_SAT 7 + +#define WM8350_RTC_HPM_AM 0 +#define WM8350_RTC_HPM_PM 1 + +/* +* R18 (0x12) - RTC Date/Month +*/ +#define WM8350_RTC_MTH_MASK 0x1F00 +#define WM8350_RTC_MTH_SHIFT 8 +#define WM8350_RTC_DATE_MASK 0x003F +#define WM8350_RTC_DATE_SHIFT 0 + +/* Bit values for R22 (0x16) */ +#define WM8350_RTC_MTH_JAN 1 +#define WM8350_RTC_MTH_FEB 2 +#define WM8350_RTC_MTH_MAR 3 +#define WM8350_RTC_MTH_APR 4 +#define WM8350_RTC_MTH_MAY 5 +#define WM8350_RTC_MTH_JUN 6 +#define WM8350_RTC_MTH_JUL 7 +#define WM8350_RTC_MTH_AUG 8 +#define WM8350_RTC_MTH_SEP 9 +#define WM8350_RTC_MTH_OCT 10 +#define WM8350_RTC_MTH_NOV 11 +#define WM8350_RTC_MTH_DEC 12 +#define WM8350_RTC_MTH_JAN_BCD 0x01 +#define WM8350_RTC_MTH_FEB_BCD 0x02 +#define WM8350_RTC_MTH_MAR_BCD 0x03 +#define WM8350_RTC_MTH_APR_BCD 0x04 +#define WM8350_RTC_MTH_MAY_BCD 0x05 +#define WM8350_RTC_MTH_JUN_BCD 0x06 +#define WM8350_RTC_MTH_JUL_BCD 0x07 +#define WM8350_RTC_MTH_AUG_BCD 0x08 +#define WM8350_RTC_MTH_SEP_BCD 0x09 +#define WM8350_RTC_MTH_OCT_BCD 0x10 +#define WM8350_RTC_MTH_NOV_BCD 0x11 +#define WM8350_RTC_MTH_DEC_BCD 0x12 + +/* +* R19 (0x13) - RTC Year +*/ +#define WM8350_RTC_YHUNDREDS_MASK 0x3F00 +#define WM8350_RTC_YHUNDREDS_SHIFT 8 +#define WM8350_RTC_YUNITS_MASK 0x00FF +#define WM8350_RTC_YUNITS_SHIFT 0 + +/* +* R20 (0x14) - Alarm Seconds/Minutes +*/ +#define WM8350_RTC_ALMMINS_MASK 0x7F00 +#define WM8350_RTC_ALMMINS_SHIFT 8 +#define WM8350_RTC_ALMSECS_MASK 0x007F +#define WM8350_RTC_ALMSECS_SHIFT 0 + +/* Bit values for R20 (0x14) */ +#define WM8350_RTC_ALMMINS_DONT_CARE -1 +#define WM8350_RTC_ALMSECS_DONT_CARE -1 + +/* +* R21 (0x15) - Alarm Hours/Day +*/ +#define WM8350_RTC_ALMDAY_MASK 0x0F00 +#define WM8350_RTC_ALMDAY_SHIFT 8 +#define WM8350_RTC_ALMHPM_MASK 0x0020 +#define WM8350_RTC_ALMHPM_SHIFT 5 +#define WM8350_RTC_ALMHRS_MASK 0x001F +#define WM8350_RTC_ALMHRS_SHIFT 0 + +/* Bit values for R21 (0x15) */ +#define WM8350_RTC_ALMDAY_DONT_CARE -1 +#define WM8350_RTC_ALMDAY_SUN 1 +#define WM8350_RTC_ALMDAY_MON 2 +#define WM8350_RTC_ALMDAY_TUE 3 +#define WM8350_RTC_ALMDAY_WED 4 +#define WM8350_RTC_ALMDAY_THU 5 +#define WM8350_RTC_ALMDAY_FRI 6 +#define WM8350_RTC_ALMDAY_SAT 7 + +#define WM8350_RTC_ALMHPM_AM 0 +#define WM8350_RTC_ALMHPM_PM 1 + +#define WM8350_RTC_ALMHRS_DONT_CARE -1 + +/* +* R22 (0x16) - Alarm Date/Month +*/ +#define WM8350_RTC_ALMMTH_MASK 0x1F00 +#define WM8350_RTC_ALMMTH_SHIFT 8 +#define WM8350_RTC_ALMDATE_MASK 0x003F +#define WM8350_RTC_ALMDATE_SHIFT 0 + +/* Bit values for R22 (0x16) */ +#define WM8350_RTC_ALMDATE_DONT_CARE -1 + +#define WM8350_RTC_ALMMTH_DONT_CARE -1 +#define WM8350_RTC_ALMMTH_JAN 1 +#define WM8350_RTC_ALMMTH_FEB 2 +#define WM8350_RTC_ALMMTH_MAR 3 +#define WM8350_RTC_ALMMTH_APR 4 +#define WM8350_RTC_ALMMTH_MAY 5 +#define WM8350_RTC_ALMMTH_JUN 6 +#define WM8350_RTC_ALMMTH_JUL 7 +#define WM8350_RTC_ALMMTH_AUG 8 +#define WM8350_RTC_ALMMTH_SEP 9 +#define WM8350_RTC_ALMMTH_OCT 10 +#define WM8350_RTC_ALMMTH_NOV 11 +#define WM8350_RTC_ALMMTH_DEC 12 +#define WM8350_RTC_ALMMTH_JAN_BCD 0x01 +#define WM8350_RTC_ALMMTH_FEB_BCD 0x02 +#define WM8350_RTC_ALMMTH_MAR_BCD 0x03 +#define WM8350_RTC_ALMMTH_APR_BCD 0x04 +#define WM8350_RTC_ALMMTH_MAY_BCD 0x05 +#define WM8350_RTC_ALMMTH_JUN_BCD 0x06 +#define WM8350_RTC_ALMMTH_JUL_BCD 0x07 +#define WM8350_RTC_ALMMTH_AUG_BCD 0x08 +#define WM8350_RTC_ALMMTH_SEP_BCD 0x09 +#define WM8350_RTC_ALMMTH_OCT_BCD 0x10 +#define WM8350_RTC_ALMMTH_NOV_BCD 0x11 +#define WM8350_RTC_ALMMTH_DEC_BCD 0x12 + +/* +* R23 (0x17) - RTC Time Control +*/ +#define WM8350_RTC_BCD 0x8000 +#define WM8350_RTC_BCD_MASK 0x8000 +#define WM8350_RTC_BCD_SHIFT 15 +#define WM8350_RTC_12HR 0x4000 +#define WM8350_RTC_12HR_MASK 0x4000 +#define WM8350_RTC_12HR_SHIFT 14 +#define WM8350_RTC_DST 0x2000 +#define WM8350_RTC_DST_MASK 0x2000 +#define WM8350_RTC_DST_SHIFT 13 +#define WM8350_RTC_SET 0x0800 +#define WM8350_RTC_SET_MASK 0x0800 +#define WM8350_RTC_SET_SHIFT 11 +#define WM8350_RTC_STS 0x0400 +#define WM8350_RTC_STS_MASK 0x0400 +#define WM8350_RTC_STS_SHIFT 10 +#define WM8350_RTC_ALMSET 0x0200 +#define WM8350_RTC_ALMSET_MASK 0x0200 +#define WM8350_RTC_ALMSET_SHIFT 9 +#define WM8350_RTC_ALMSTS 0x0100 +#define WM8350_RTC_ALMSTS_MASK 0x0100 +#define WM8350_RTC_ALMSTS_SHIFT 8 +#define WM8350_RTC_PINT 0x0070 +#define WM8350_RTC_PINT_MASK 0x0070 +#define WM8350_RTC_PINT_SHIFT 4 +#define WM8350_RTC_DSW 0x000F +#define WM8350_RTC_DSW_MASK 0x000F +#define WM8350_RTC_DSW_SHIFT 0 + +/* Bit values for R23 (0x17) */ +#define WM8350_RTC_BCD_BINARY 0 +#define WM8350_RTC_BCD_BCD 1 + +#define WM8350_RTC_12HR_24HR 0 +#define WM8350_RTC_12HR_12HR 1 + +#define WM8350_RTC_DST_DISABLED 0 +#define WM8350_RTC_DST_ENABLED 1 + +#define WM8350_RTC_SET_RUN 0 +#define WM8350_RTC_SET_SET 1 + +#define WM8350_RTC_STS_RUNNING 0 +#define WM8350_RTC_STS_STOPPED 1 + +#define WM8350_RTC_ALMSET_RUN 0 +#define WM8350_RTC_ALMSET_SET 1 + +#define WM8350_RTC_ALMSTS_RUNNING 0 +#define WM8350_RTC_ALMSTS_STOPPED 1 + +#define WM8350_RTC_PINT_DISABLED 0 +#define WM8350_RTC_PINT_SECS 1 +#define WM8350_RTC_PINT_MINS 2 +#define WM8350_RTC_PINT_HRS 3 +#define WM8350_RTC_PINT_DAYS 4 +#define WM8350_RTC_PINT_MTHS 5 + +#define WM8350_RTC_DSW_DISABLED 0 +#define WM8350_RTC_DSW_1HZ 1 +#define WM8350_RTC_DSW_2HZ 2 +#define WM8350_RTC_DSW_4HZ 3 +#define WM8350_RTC_DSW_8HZ 4 +#define WM8350_RTC_DSW_16HZ 5 +#define WM8350_RTC_DSW_32HZ 6 +#define WM8350_RTC_DSW_64HZ 7 +#define WM8350_RTC_DSW_128HZ 8 +#define WM8350_RTC_DSW_256HZ 9 +#define WM8350_RTC_DSW_512HZ 10 +#define WM8350_RTC_DSW_1024HZ 11 + +/* +* R218 (0xDA) - RTC Tick Control +*/ +#define WM8350_RTC_TICKSTS 0x4000 +#define WM8350_RTC_CLKSRC 0x2000 +#define WM8350_RTC_TRIM_MASK 0x03FF + +/* +* RTC Interrupts. +*/ +#define WM8350_IRQ_RTC_PER 7 +#define WM8350_IRQ_RTC_SEC 8 +#define WM8350_IRQ_RTC_ALM 9 + +#endif
Signature · 1 line
1.5.6.5
PATCH 7/14 mfd: Add WM8350 watchdog register definitions
Signed-off-by Mark Brown <[email protected]>
--- include/linux/mfd/wm8350/wdt.h | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+), 0 deletions(-) create mode 100644 include/linux/mfd/wm8350/wdt.h
include/linux/mfd/wm8350/wdt.h new file +22 -0
@@ -0,0 +1,22 @@ +/* +* wdt.h -- Watchdog Driver for Wolfson WM8350 PMIC +* +* Copyright 2007 Wolfson Microelectronics PLC +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +*/ + +#ifndef __LINUX_MFD_WM8350_WDT_H_ +#define __LINUX_MFD_WM8350_WDT_H_ + +#define WM8350_WDOG_HIB_MODE 0x0080 +#define WM8350_WDOG_DEBUG 0x0040 +#define WM8350_WDOG_MODE_MASK 0x0030 +#define WM8350_WDOG_TO_MASK 0x0007 + +#define WM8350_IRQ_SYS_WDOG_TO 24 + +#endif
Signature · 1 line
1.5.6.5
PATCH 8/14 mfd: Core support for the WM8350 AudioPlus PMIC
The WM8350 is an integrated audio and power management subsystem intended for use as the primary PMIC in mobile multimedia applications. The WM8350 can be controlled via either I2C or SPI - the control interface is provided by a separate module in order to allow greatest flexibility in configuring the kernel.
This driver was originally written by Liam Girdwood and has since been updated to current kernel APIs and split up for submission by me. All the heavy lifting here was done by Liam.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/Kconfig | 19 + drivers/mfd/Makefile | 2 + drivers/mfd/wm8350-core.c | 456 +++++++++++++ drivers/mfd/wm8350-regmap.c | 1347 +++++++++++++++++++++++++++++++++++++++ include/linux/mfd/wm8350/core.h | 585 +++++++++++++++++ 5 files changed, 2409 insertions(+), 0 deletions(-) create mode 100644 drivers/mfd/wm8350-core.c create mode 100644 drivers/mfd/wm8350-regmap.c create mode 100644 include/linux/mfd/wm8350/core.h
drivers/mfd/Kconfig +19 -0
@@ -86,6 +86,25 @@ config MFD_WM8400 the device, additional drivers must be enabled in order to use the functionality of the device. +config MFD_WM8350 + tristate + +config MFD_WM8350_CONFIG_MODE_0 + bool + depends on MFD_WM8350 + +config MFD_WM8350_CONFIG_MODE_1 + bool + depends on MFD_WM8350 + +config MFD_WM8350_CONFIG_MODE_2 + bool + depends on MFD_WM8350 + +config MFD_WM8350_CONFIG_MODE_3 + bool + depends on MFD_WM8350 + endmenu menu "Multimedia Capabilities Port drivers"
drivers/mfd/Makefile +2 -0
@@ -13,6 +13,8 @@ obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o obj-$(CONFIG_MFD_WM8400) += wm8400-core.o +wm8350-objs := wm8350-core.o wm8350-regmap.o +obj-$(CONFIG_MFD_WM8350) += wm8350.o obj-$(CONFIG_MFD_CORE) += mfd-core.o
drivers/mfd/wm8350-core.c new file +456 -0
456 lines not on this page · raw message
drivers/mfd/wm8350-regmap.c new file +1347 -0
1,347 lines not on this page · raw message
include/linux/mfd/wm8350/core.h new file +585 -0
585 lines not on this page · raw message
Signature · 1 line
1.5.6.5
PATCH 9/14 mfd: Add I2C control support for WM8350
Implement the I2C control interface for the WM8350. This code was originally written by Liam Girdwood and has been updated for submission by Mark Brown.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/Kconfig | 11 ++++ drivers/mfd/Makefile | 1 + drivers/mfd/wm8350-i2c.c | 120 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+), 0 deletions(-) create mode 100644 drivers/mfd/wm8350-i2c.c
drivers/mfd/Kconfig +11 -0
@@ -105,6 +105,17 @@ config MFD_WM8350_CONFIG_MODE_3 bool depends on MFD_WM8350 +config MFD_WM8350_I2C + tristate "Support Wolfson Microelectronics WM8350 with I2C" + select MFD_WM8350 + depends on I2C + help + The WM8350 is an integrated audio and power management + subsystem with watchdog and RTC functionality for embedded + systems. This option enables core support for the WM8350 with + I2C as the control interface. Additional options must be + selected to enable support for the functionality of the chip. + endmenu menu "Multimedia Capabilities Port drivers"
drivers/mfd/Makefile +1 -0
@@ -15,6 +15,7 @@ obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o obj-$(CONFIG_MFD_WM8400) += wm8400-core.o wm8350-objs := wm8350-core.o wm8350-regmap.o obj-$(CONFIG_MFD_WM8350) += wm8350.o +obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o obj-$(CONFIG_MFD_CORE) += mfd-core.o
drivers/mfd/wm8350-i2c.c new file +120 -0
120 lines not on this page · raw message
Signature · 1 line
1.5.6.5
PATCH 10/14 mfd: Add GPIO pin configuration support for WM8350
The WM8350 provides a number of user-configurable pins providing access to various signals generated by the functions on the chip. These are referred to as GPIO pins in the device documentation but in Linux terms they are more general than that, providing configuration of alternate functions.
This patch implements support for selecting the alternate functions for these pins. They can also be used as GPIOs in the normal Linux sense - a subsequent patch will add support for doing so.
This code was all written by Liam Girdwood and has had minor updates and rearrangements by Mark Brown.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/Makefile | 2 +- drivers/mfd/wm8350-gpio.c | 222 +++++++++++++++++++++++++++++++++++++++ include/linux/mfd/wm8350/gpio.h | 10 ++ 3 files changed, 233 insertions(+), 1 deletions(-) create mode 100644 drivers/mfd/wm8350-gpio.c
drivers/mfd/Makefile +1 -1
@@ -13,7 +13,7 @@ obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o obj-$(CONFIG_MFD_WM8400) += wm8400-core.o -wm8350-objs := wm8350-core.o wm8350-regmap.o +wm8350-objs := wm8350-core.o wm8350-regmap.o wm8350-gpio.o obj-$(CONFIG_MFD_WM8350) += wm8350.o obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o
drivers/mfd/wm8350-gpio.c new file +222 -0
222 lines not on this page · raw message
include/linux/mfd/wm8350/gpio.h +10 -0
@@ -323,4 +323,14 @@#define WM8350_GP1_LVL 0x0002#define WM8350_GP0_LVL 0x0001 +struct wm8350 ; + +int wm8350_gpio_config (struct wm8350 *wm8350,int gpio,int dir,int func, +int pol,int pull,int invert,int debounce); + +/* +* GPIO Interrupts +*/ +#define WM8350_IRQ_GPIO (x) (50 + x) +#endif
Signature · 1 line
1.5.6.5
PATCH 11/14 mfd: Add initialisation callback for WM8350
Some functions of the WM8350 require board-specific initialisation on startup. Provide a callback to the WM8350 driver in platform data for platforms to use to configure the chip. Use of a callback allows platforms to control the ordering of initialisation which can be important.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/wm8350-core.c | 12 +++++++++++- drivers/mfd/wm8350-i2c.c | 2 +- include/linux/mfd/wm8350/core.h | 14 +++++++++++++- 3 files changed, 25 insertions(+), 3 deletions(-)
drivers/mfd/wm8350-core.c +11 -1
@@ -388,7 +388,8 @@ out: }EXPORT_SYMBOL_GPL (wm8350_create_cache); -int wm8350_device_init (struct wm8350 *wm8350) +int wm8350_device_init (struct wm8350 *wm8350, +struct wm8350_platform_data *pdata) {int ret = -EINVAL ;u16 id1, id2, mask, mode;
@@ -439,6 +440,15 @@ int wm8350_device_init(struct wm8350 *wm8350)return ret; } +if (pdata->init) { + ret = pdata->init (wm8350); +if (ret !=0 ) { +dev_err (wm8350->dev,"Platform init() failed: %d\n" , + ret); + goto err; + } + } +return 0 ; err:
drivers/mfd/wm8350-i2c.c +1 -1
@@ -65,7 +65,7 @@ static int wm8350_i2c_probe(struct i2c_client *i2c, wm8350->read_dev = wm8350_i2c_read_device; wm8350->write_dev = wm8350_i2c_write_device; - ret =wm8350_device_init (wm8350); + ret =wm8350_device_init (wm8350, i2c->dev.platform_data);if (ret <0 ) goto err;
include/linux/mfd/wm8350/core.h +13 -1
@@ -564,10 +564,22 @@ struct wm8350 {u16 *reg_cache; }; +/** +* Data to be supplied by the platform to initialise the WM8350. +* +* @init: Function called during driver initialisation. Should be +* used by the platform to configure GPIO functions and similar. +*/ +struct wm8350_platform_data { +int (*init)(struct wm8350 *wm8350); +}; + +/* * WM8350 device initialisation and exit. */ -int wm8350_device_init (struct wm8350 *wm8350); +int wm8350_device_init (struct wm8350 *wm8350, +struct wm8350_platform_data *pdata);void wm8350_device_exit (struct wm8350 *wm8350);/*
Signature · 1 line
1.5.6.5
PATCH 12/14 mfd: Add WM8350 interrupt support
The WM8350 has an interrupt line to the CPU which is shared by the devices on the CPU. This patch adds support for the interrupt controller within the WM8350 which identifies which identifies the interrupt cause. In common with other similar chips this is done outside the standard interrupt framework due to the need to access the interrupt controller over an interrupt-driven bus.
This code was all originally written by Liam Girdwood with updates for submission by me.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/wm8350-core.c | 770 ++++++++++++++++++++++++++++++++++++++- drivers/mfd/wm8350-i2c.c | 2 +- include/linux/mfd/wm8350/core.h | 21 +- 3 files changed, 787 insertions(+), 6 deletions(-)
drivers/mfd/wm8350-core.c +766 -4
@@ -15,15 +15,20 @@#include <linux/kernel.h> #include <linux/module.h> #include <linux/init.h> +#include <linux/bug.h> #include <linux/device.h> #include <linux/delay.h> #include <linux/interrupt.h> +#include <linux/workqueue.h> #include <linux/mfd/wm8350/core.h> #include <linux/mfd/wm8350/audio.h> +#include <linux/mfd/wm8350/comparator.h> #include <linux/mfd/wm8350/gpio.h> #include <linux/mfd/wm8350/pmic.h> +#include <linux/mfd/wm8350/rtc.h> #include <linux/mfd/wm8350/supply.h> +#include <linux/mfd/wm8350/wdt.h> #define WM8350_UNLOCK_KEY 0x0013#define WM8350_LOCK_KEY 0x0000
@@ -321,6 +326,743 @@ int wm8350_reg_unlock(struct wm8350 *wm8350) }EXPORT_SYMBOL_GPL (wm8350_reg_unlock); +static void wm8350_irq_call_handler (struct wm8350 *wm8350,int irq) +{ +mutex_lock (&wm8350->irq_mutex); + +if (wm8350->irq[irq].handler) + wm8350->irq[irq].handler (wm8350, irq, wm8350->irq[irq].data); +else { +dev_err (wm8350->dev,"irq %d nobody cared. now masked.\n" , + irq); +wm8350_mask_irq (wm8350, irq); + } + +mutex_unlock (&wm8350->irq_mutex); +} + +/* +* wm8350_irq_worker actually handles the interrupts. Since all +* interrupts are clear on read the IRQ line will be reasserted and +* the physical IRQ will be handled again if another interrupt is +* asserted while we run - in the normal course of events this is a +* rare occurrence so we save I2C/SPI reads. +*/ +static void wm8350_irq_worker (struct work_struct *work) +{ + struct wm8350 *wm8350 = container_of(work, struct wm8350, irq_work); +u16 level_one, status1, status2, comp; + +/* TODO: Use block reads to improve performance? */ + level_one =wm8350_reg_read (wm8350,WM8350_SYSTEM_INTERRUPTS ) + & ~wm8350_reg_read (wm8350,WM8350_SYSTEM_INTERRUPTS_MASK ); + status1 =wm8350_reg_read (wm8350,WM8350_INT_STATUS_1 ) + & ~wm8350_reg_read (wm8350,WM8350_INT_STATUS_1_MASK ); + status2 =wm8350_reg_read (wm8350,WM8350_INT_STATUS_2 ) + & ~wm8350_reg_read (wm8350,WM8350_INT_STATUS_2_MASK ); + comp =wm8350_reg_read (wm8350,WM8350_COMPARATOR_INT_STATUS ) + & ~wm8350_reg_read (wm8350,WM8350_COMPARATOR_INT_STATUS_MASK ); + +/* over current */ +if (level_one &WM8350_OC_INT ) { +u16 oc; + + oc =wm8350_reg_read (wm8350,WM8350_OVER_CURRENT_INT_STATUS ); + oc &= ~wm8350_reg_read (wm8350, +WM8350_OVER_CURRENT_INT_STATUS_MASK ); + +if (oc &WM8350_OC_LS_EINT )/* limit switch */ +wm8350_irq_call_handler (wm8350,WM8350_IRQ_OC_LS ); + } + +/* under voltage */ +if (level_one &WM8350_UV_INT ) { +u16 uv; + + uv =wm8350_reg_read (wm8350,WM8350_UNDER_VOLTAGE_INT_STATUS ); + uv &= ~wm8350_reg_read (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK ); + +if (uv &WM8350_UV_DC1_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_DC1 ); +if (uv &WM8350_UV_DC2_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_DC2 ); +if (uv &WM8350_UV_DC3_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_DC3 ); +if (uv &WM8350_UV_DC4_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_DC4 ); +if (uv &WM8350_UV_DC5_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_DC5 ); +if (uv &WM8350_UV_DC6_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_DC6 ); +if (uv &WM8350_UV_LDO1_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_LDO1 ); +if (uv &WM8350_UV_LDO2_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_LDO2 ); +if (uv &WM8350_UV_LDO3_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_LDO3 ); +if (uv &WM8350_UV_LDO4_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_UV_LDO4 ); + } + +/* charger, RTC */ +if (status1) { +if (status1 &WM8350_CHG_BAT_HOT_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_BAT_HOT ); +if (status1 &WM8350_CHG_BAT_COLD_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_BAT_COLD ); +if (status1 &WM8350_CHG_BAT_FAIL_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_BAT_FAIL ); +if (status1 &WM8350_CHG_TO_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_CHG_TO ); +if (status1 &WM8350_CHG_END_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_CHG_END ); +if (status1 &WM8350_CHG_START_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_CHG_START ); +if (status1 &WM8350_CHG_FAST_RDY_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_FAST_RDY ); +if (status1 &WM8350_CHG_VBATT_LT_3P9_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_VBATT_LT_3P9 ); +if (status1 &WM8350_CHG_VBATT_LT_3P1_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_VBATT_LT_3P1 ); +if (status1 &WM8350_CHG_VBATT_LT_2P85_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CHG_VBATT_LT_2P85 ); +if (status1 &WM8350_RTC_ALM_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_RTC_ALM ); +if (status1 &WM8350_RTC_SEC_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_RTC_SEC ); +if (status1 &WM8350_RTC_PER_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_RTC_PER ); + } + +/* current sink, system, aux adc */ +if (status2) { +if (status2 &WM8350_CS1_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_CS1 ); +if (status2 &WM8350_CS2_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_CS2 ); + +if (status2 &WM8350_SYS_HYST_COMP_FAIL_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_SYS_HYST_COMP_FAIL ); +if (status2 &WM8350_SYS_CHIP_GT115_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_SYS_CHIP_GT115 ); +if (status2 &WM8350_SYS_CHIP_GT140_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_SYS_CHIP_GT140 ); +if (status2 &WM8350_SYS_WDOG_TO_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_SYS_WDOG_TO ); + +if (status2 &WM8350_AUXADC_DATARDY_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_AUXADC_DATARDY ); +if (status2 &WM8350_AUXADC_DCOMP4_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_AUXADC_DCOMP4 ); +if (status2 &WM8350_AUXADC_DCOMP3_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_AUXADC_DCOMP3 ); +if (status2 &WM8350_AUXADC_DCOMP2_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_AUXADC_DCOMP2 ); +if (status2 &WM8350_AUXADC_DCOMP1_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_AUXADC_DCOMP1 ); + +if (status2 &WM8350_USB_LIMIT_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_USB_LIMIT ); + } + +/* wake, codec, ext */ +if (comp) { +if (comp &WM8350_WKUP_OFF_STATE_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_WKUP_OFF_STATE ); +if (comp &WM8350_WKUP_HIB_STATE_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_WKUP_HIB_STATE ); +if (comp &WM8350_WKUP_CONV_FAULT_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_WKUP_CONV_FAULT ); +if (comp &WM8350_WKUP_WDOG_RST_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_WKUP_WDOG_RST ); +if (comp &WM8350_WKUP_GP_PWR_ON_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_WKUP_GP_PWR_ON ); +if (comp &WM8350_WKUP_ONKEY_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_WKUP_ONKEY ); +if (comp &WM8350_WKUP_GP_WAKEUP_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_WKUP_GP_WAKEUP ); + +if (comp &WM8350_CODEC_JCK_DET_L_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CODEC_JCK_DET_L ); +if (comp &WM8350_CODEC_JCK_DET_R_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CODEC_JCK_DET_R ); +if (comp &WM8350_CODEC_MICSCD_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_CODEC_MICSCD ); +if (comp &WM8350_CODEC_MICD_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_CODEC_MICD ); + +if (comp &WM8350_EXT_USB_FB_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_EXT_USB_FB ); +if (comp &WM8350_EXT_WALL_FB_EINT ) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_EXT_WALL_FB ); +if (comp &WM8350_EXT_BAT_FB_EINT ) +wm8350_irq_call_handler (wm8350,WM8350_IRQ_EXT_BAT_FB ); + } + +if (level_one &WM8350_GP_INT ) { +int i; +u16 gpio; + + gpio =wm8350_reg_read (wm8350,WM8350_GPIO_INT_STATUS ); + gpio &= ~wm8350_reg_read (wm8350, +WM8350_GPIO_INT_STATUS_MASK ); + +for (i =0 ; i <12 ; i++) { +if (gpio & (1 << i)) +wm8350_irq_call_handler (wm8350, +WM8350_IRQ_GPIO (i)); + } + } + +enable_irq (wm8350->chip_irq); +} + +static irqreturn_t wm8350_irq (int irq,void *data) +{ +struct wm8350 *wm8350 = data; + +disable_irq_nosync (irq); +schedule_work (&wm8350->irq_work); + +return IRQ_HANDLED ; +} + +int wm8350_register_irq (struct wm8350 *wm8350,int irq, +void (*handler) (struct wm8350 *,int ,void *), +void *data) +{ +if (irq <0 || irq >WM8350_NUM_IRQ || !handler) +return -EINVAL ; + +if (wm8350->irq[irq].handler) +return -EBUSY ; + +mutex_lock (&wm8350->irq_mutex); + wm8350->irq[irq].handler = handler; + wm8350->irq[irq].data = data; +mutex_unlock (&wm8350->irq_mutex); + +return 0 ; +} +EXPORT_SYMBOL_GPL (wm8350_register_irq); + +int wm8350_free_irq (struct wm8350 *wm8350,int irq) +{ +if (irq <0 || irq >WM8350_NUM_IRQ ) +return -EINVAL ; + +mutex_lock (&wm8350->irq_mutex); + wm8350->irq[irq].handler =NULL ; +mutex_unlock (&wm8350->irq_mutex); +return 0 ; +} +EXPORT_SYMBOL_GPL (wm8350_free_irq); + +int wm8350_mask_irq (struct wm8350 *wm8350,int irq) +{ +switch (irq) { +case WM8350_IRQ_CHG_BAT_HOT : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_BAT_HOT_EINT ); +case WM8350_IRQ_CHG_BAT_COLD : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_BAT_COLD_EINT ); +case WM8350_IRQ_CHG_BAT_FAIL : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_BAT_FAIL_EINT ); +case WM8350_IRQ_CHG_TO : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_TO_EINT ); +case WM8350_IRQ_CHG_END : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_END_EINT ); +case WM8350_IRQ_CHG_START : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_START_EINT ); +case WM8350_IRQ_CHG_FAST_RDY : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_FAST_RDY_EINT ); +case WM8350_IRQ_RTC_PER : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_RTC_PER_EINT ); +case WM8350_IRQ_RTC_SEC : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_RTC_SEC_EINT ); +case WM8350_IRQ_RTC_ALM : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_RTC_ALM_EINT ); +case WM8350_IRQ_CHG_VBATT_LT_3P9 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_VBATT_LT_3P9_EINT ); +case WM8350_IRQ_CHG_VBATT_LT_3P1 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_VBATT_LT_3P1_EINT ); +case WM8350_IRQ_CHG_VBATT_LT_2P85 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_VBATT_LT_2P85_EINT ); +case WM8350_IRQ_CS1 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_CS1_EINT ); +case WM8350_IRQ_CS2 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_CS2_EINT ); +case WM8350_IRQ_USB_LIMIT : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_USB_LIMIT_EINT ); +case WM8350_IRQ_AUXADC_DATARDY : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DATARDY_EINT ); +case WM8350_IRQ_AUXADC_DCOMP4 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP4_EINT ); +case WM8350_IRQ_AUXADC_DCOMP3 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP3_EINT ); +case WM8350_IRQ_AUXADC_DCOMP2 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP2_EINT ); +case WM8350_IRQ_AUXADC_DCOMP1 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP1_EINT ); +case WM8350_IRQ_SYS_HYST_COMP_FAIL : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_HYST_COMP_FAIL_EINT ); +case WM8350_IRQ_SYS_CHIP_GT115 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_CHIP_GT115_EINT ); +case WM8350_IRQ_SYS_CHIP_GT140 : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_CHIP_GT140_EINT ); +case WM8350_IRQ_SYS_WDOG_TO : +return wm8350_set_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_WDOG_TO_EINT ); +case WM8350_IRQ_UV_LDO4 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO4_EINT ); +case WM8350_IRQ_UV_LDO3 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO3_EINT ); +case WM8350_IRQ_UV_LDO2 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO2_EINT ); +case WM8350_IRQ_UV_LDO1 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO1_EINT ); +case WM8350_IRQ_UV_DC6 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC6_EINT ); +case WM8350_IRQ_UV_DC5 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC5_EINT ); +case WM8350_IRQ_UV_DC4 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC4_EINT ); +case WM8350_IRQ_UV_DC3 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC3_EINT ); +case WM8350_IRQ_UV_DC2 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC2_EINT ); +case WM8350_IRQ_UV_DC1 : +return wm8350_set_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC1_EINT ); +case WM8350_IRQ_OC_LS : +return wm8350_set_bits (wm8350, +WM8350_OVER_CURRENT_INT_STATUS_MASK , +WM8350_IM_OC_LS_EINT ); +case WM8350_IRQ_EXT_USB_FB : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_EXT_USB_FB_EINT ); +case WM8350_IRQ_EXT_WALL_FB : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_EXT_WALL_FB_EINT ); +case WM8350_IRQ_EXT_BAT_FB : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_EXT_BAT_FB_EINT ); +case WM8350_IRQ_CODEC_JCK_DET_L : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_JCK_DET_L_EINT ); +case WM8350_IRQ_CODEC_JCK_DET_R : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_JCK_DET_R_EINT ); +case WM8350_IRQ_CODEC_MICSCD : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_MICSCD_EINT ); +case WM8350_IRQ_CODEC_MICD : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_MICD_EINT ); +case WM8350_IRQ_WKUP_OFF_STATE : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_OFF_STATE_EINT ); +case WM8350_IRQ_WKUP_HIB_STATE : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_HIB_STATE_EINT ); +case WM8350_IRQ_WKUP_CONV_FAULT : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_CONV_FAULT_EINT ); +case WM8350_IRQ_WKUP_WDOG_RST : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_OFF_STATE_EINT ); +case WM8350_IRQ_WKUP_GP_PWR_ON : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_GP_PWR_ON_EINT ); +case WM8350_IRQ_WKUP_ONKEY : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_ONKEY_EINT ); +case WM8350_IRQ_WKUP_GP_WAKEUP : +return wm8350_set_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_GP_WAKEUP_EINT ); +case WM8350_IRQ_GPIO (0 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP0_EINT ); +case WM8350_IRQ_GPIO (1 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP1_EINT ); +case WM8350_IRQ_GPIO (2 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP2_EINT ); +case WM8350_IRQ_GPIO (3 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP3_EINT ); +case WM8350_IRQ_GPIO (4 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP4_EINT ); +case WM8350_IRQ_GPIO (5 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP5_EINT ); +case WM8350_IRQ_GPIO (6 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP6_EINT ); +case WM8350_IRQ_GPIO (7 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP7_EINT ); +case WM8350_IRQ_GPIO (8 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP8_EINT ); +case WM8350_IRQ_GPIO (9 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP9_EINT ); +case WM8350_IRQ_GPIO (10 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP10_EINT ); +case WM8350_IRQ_GPIO (11 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP11_EINT ); +case WM8350_IRQ_GPIO (12 ): +return wm8350_set_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP12_EINT ); +default : +dev_warn (wm8350->dev,"Attempting to mask unknown IRQ %d\n" , + irq); +return -EINVAL ; + } +return 0 ; +} +EXPORT_SYMBOL_GPL (wm8350_mask_irq); + +int wm8350_unmask_irq (struct wm8350 *wm8350,int irq) +{ +switch (irq) { +case WM8350_IRQ_CHG_BAT_HOT : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_BAT_HOT_EINT ); +case WM8350_IRQ_CHG_BAT_COLD : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_BAT_COLD_EINT ); +case WM8350_IRQ_CHG_BAT_FAIL : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_BAT_FAIL_EINT ); +case WM8350_IRQ_CHG_TO : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_TO_EINT ); +case WM8350_IRQ_CHG_END : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_END_EINT ); +case WM8350_IRQ_CHG_START : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_START_EINT ); +case WM8350_IRQ_CHG_FAST_RDY : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_FAST_RDY_EINT ); +case WM8350_IRQ_RTC_PER : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_RTC_PER_EINT ); +case WM8350_IRQ_RTC_SEC : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_RTC_SEC_EINT ); +case WM8350_IRQ_RTC_ALM : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_RTC_ALM_EINT ); +case WM8350_IRQ_CHG_VBATT_LT_3P9 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_VBATT_LT_3P9_EINT ); +case WM8350_IRQ_CHG_VBATT_LT_3P1 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_VBATT_LT_3P1_EINT ); +case WM8350_IRQ_CHG_VBATT_LT_2P85 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_1_MASK , +WM8350_IM_CHG_VBATT_LT_2P85_EINT ); +case WM8350_IRQ_CS1 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_CS1_EINT ); +case WM8350_IRQ_CS2 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_CS2_EINT ); +case WM8350_IRQ_USB_LIMIT : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_USB_LIMIT_EINT ); +case WM8350_IRQ_AUXADC_DATARDY : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DATARDY_EINT ); +case WM8350_IRQ_AUXADC_DCOMP4 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP4_EINT ); +case WM8350_IRQ_AUXADC_DCOMP3 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP3_EINT ); +case WM8350_IRQ_AUXADC_DCOMP2 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP2_EINT ); +case WM8350_IRQ_AUXADC_DCOMP1 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_AUXADC_DCOMP1_EINT ); +case WM8350_IRQ_SYS_HYST_COMP_FAIL : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_HYST_COMP_FAIL_EINT ); +case WM8350_IRQ_SYS_CHIP_GT115 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_CHIP_GT115_EINT ); +case WM8350_IRQ_SYS_CHIP_GT140 : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_CHIP_GT140_EINT ); +case WM8350_IRQ_SYS_WDOG_TO : +return wm8350_clear_bits (wm8350,WM8350_INT_STATUS_2_MASK , +WM8350_IM_SYS_WDOG_TO_EINT ); +case WM8350_IRQ_UV_LDO4 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO4_EINT ); +case WM8350_IRQ_UV_LDO3 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO3_EINT ); +case WM8350_IRQ_UV_LDO2 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO2_EINT ); +case WM8350_IRQ_UV_LDO1 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_LDO1_EINT ); +case WM8350_IRQ_UV_DC6 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC6_EINT ); +case WM8350_IRQ_UV_DC5 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC5_EINT ); +case WM8350_IRQ_UV_DC4 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC4_EINT ); +case WM8350_IRQ_UV_DC3 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC3_EINT ); +case WM8350_IRQ_UV_DC2 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC2_EINT ); +case WM8350_IRQ_UV_DC1 : +return wm8350_clear_bits (wm8350, +WM8350_UNDER_VOLTAGE_INT_STATUS_MASK , +WM8350_IM_UV_DC1_EINT ); +case WM8350_IRQ_OC_LS : +return wm8350_clear_bits (wm8350, +WM8350_OVER_CURRENT_INT_STATUS_MASK , +WM8350_IM_OC_LS_EINT ); +case WM8350_IRQ_EXT_USB_FB : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_EXT_USB_FB_EINT ); +case WM8350_IRQ_EXT_WALL_FB : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_EXT_WALL_FB_EINT ); +case WM8350_IRQ_EXT_BAT_FB : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_EXT_BAT_FB_EINT ); +case WM8350_IRQ_CODEC_JCK_DET_L : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_JCK_DET_L_EINT ); +case WM8350_IRQ_CODEC_JCK_DET_R : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_JCK_DET_R_EINT ); +case WM8350_IRQ_CODEC_MICSCD : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_MICSCD_EINT ); +case WM8350_IRQ_CODEC_MICD : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_CODEC_MICD_EINT ); +case WM8350_IRQ_WKUP_OFF_STATE : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_OFF_STATE_EINT ); +case WM8350_IRQ_WKUP_HIB_STATE : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_HIB_STATE_EINT ); +case WM8350_IRQ_WKUP_CONV_FAULT : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_CONV_FAULT_EINT ); +case WM8350_IRQ_WKUP_WDOG_RST : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_OFF_STATE_EINT ); +case WM8350_IRQ_WKUP_GP_PWR_ON : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_GP_PWR_ON_EINT ); +case WM8350_IRQ_WKUP_ONKEY : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_ONKEY_EINT ); +case WM8350_IRQ_WKUP_GP_WAKEUP : +return wm8350_clear_bits (wm8350, +WM8350_COMPARATOR_INT_STATUS_MASK , +WM8350_IM_WKUP_GP_WAKEUP_EINT ); +case WM8350_IRQ_GPIO (0 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP0_EINT ); +case WM8350_IRQ_GPIO (1 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP1_EINT ); +case WM8350_IRQ_GPIO (2 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP2_EINT ); +case WM8350_IRQ_GPIO (3 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP3_EINT ); +case WM8350_IRQ_GPIO (4 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP4_EINT ); +case WM8350_IRQ_GPIO (5 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP5_EINT ); +case WM8350_IRQ_GPIO (6 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP6_EINT ); +case WM8350_IRQ_GPIO (7 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP7_EINT ); +case WM8350_IRQ_GPIO (8 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP8_EINT ); +case WM8350_IRQ_GPIO (9 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP9_EINT ); +case WM8350_IRQ_GPIO (10 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP10_EINT ); +case WM8350_IRQ_GPIO (11 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP11_EINT ); +case WM8350_IRQ_GPIO (12 ): +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_STATUS_MASK , +WM8350_IM_GP12_EINT ); +default : +dev_warn (wm8350->dev,"Attempting to unmask unknown IRQ %d\n" , + irq); +return -EINVAL ; + } +return 0 ; +} +EXPORT_SYMBOL_GPL (wm8350_unmask_irq); +/* * Cache is always host endian. */
@@ -388,11 +1130,12 @@ out: }EXPORT_SYMBOL_GPL (wm8350_create_cache); -int wm8350_device_init (struct wm8350 *wm8350, +int wm8350_device_init (struct wm8350 *wm8350,int irq,struct wm8350_platform_data *pdata) {int ret = -EINVAL ;u16 id1, id2, mask, mode; +int i;/* get WM8350 revision and config mode */ wm8350->read_dev (wm8350,WM8350_RESET_ID ,sizeof (id1), &id1);
@@ -401,9 +1144,7 @@ int wm8350_device_init(struct wm8350 *wm8350, id1 =be16_to_cpu (id1); id2 =be16_to_cpu (id2); -if (id1 ==0x0 ) -dev_info (wm8350->dev,"Found Rev C device\n" ); -else if (id1 ==0x6143 ) { +if (id1 ==0x6143 ) {switch ((id2 &WM8350_CHIP_REV_MASK ) >>12 ) {case WM8350_REV_E :dev_info (wm8350->dev,"Found Rev E device\n" );
@@ -449,6 +1190,24 @@ int wm8350_device_init(struct wm8350 *wm8350, } } +mutex_init (&wm8350->irq_mutex); +INIT_WORK (&wm8350->irq_work, wm8350_irq_worker); +if (irq !=NO_IRQ ) { + ret =request_irq (irq, wm8350_irq,0 , +"wm8350" , wm8350); +if (ret !=0 ) { +dev_err (wm8350->dev,"Failed to request IRQ: %d\n" , + ret); + goto err; + } + }else { +dev_err (wm8350->dev,"No IRQ configured\n" ); + goto err; + } + wm8350->chip_irq = irq; + +wm8350_reg_write (wm8350,WM8350_SYSTEM_INTERRUPTS_MASK ,0x0 ); +return 0 ; err:
@@ -459,8 +1218,11 @@ EXPORT_SYMBOL_GPL(wm8350_device_init);void wm8350_device_exit (struct wm8350 *wm8350) { +free_irq (wm8350->chip_irq, wm8350); +flush_work (&wm8350->irq_work);kfree (wm8350->reg_cache); }EXPORT_SYMBOL_GPL (wm8350_device_exit); +MODULE_DESCRIPTION ("WM8350 AudioPlus PMIC core driver" );MODULE_LICENSE ("GPL" );
drivers/mfd/wm8350-i2c.c +1 -1
@@ -65,7 +65,7 @@ static int wm8350_i2c_probe(struct i2c_client *i2c, wm8350->read_dev = wm8350_i2c_read_device; wm8350->write_dev = wm8350_i2c_write_device; - ret =wm8350_device_init (wm8350, i2c->dev.platform_data); + ret =wm8350_device_init (wm8350, i2c->irq, i2c->dev.platform_data);if (ret <0 ) goto err;
include/linux/mfd/wm8350/core.h +20 -1
@@ -530,6 +530,8 @@#define WM8350_REV_F 0x5#define WM8350_REV_G 0x6 +#define WM8350_NUM_IRQ 63 +struct wm8350_reg_access {u16 readable;/* Mask of readable bits */ u16 writable;/* Mask of writable bits */
@@ -562,6 +564,12 @@ struct wm8350 {int (*write_dev)(struct wm8350 *wm8350,char reg,int size,void *src);u16 *reg_cache; + +/* Interrupt handling */ +struct work_struct irq_work; +struct mutex irq_mutex;/* IRQ table mutex */ +struct wm8350_irq irq[WM8350_NUM_IRQ ]; +int chip_irq; };/**
@@ -578,7 +586,7 @@ struct wm8350_platform_data {/* * WM8350 device initialisation and exit. */ -int wm8350_device_init (struct wm8350 *wm8350, +int wm8350_device_init (struct wm8350 *wm8350,int irq,struct wm8350_platform_data *pdata);void wm8350_device_exit (struct wm8350 *wm8350);
@@ -594,4 +602,15 @@ int wm8350_reg_unlock(struct wm8350 *wm8350);int wm8350_block_read (struct wm8350 *wm8350,int reg,int size,u16 *dest);int wm8350_block_write (struct wm8350 *wm8350,int reg,int size,u16 *src); +/* +* WM8350 internal interrupts +*/ +int wm8350_register_irq (struct wm8350 *wm8350,int irq, +void (*handler) (struct wm8350 *,int ,void *), +void *data); +int wm8350_free_irq (struct wm8350 *wm8350,int irq); +int wm8350_mask_irq (struct wm8350 *wm8350,int irq); +int wm8350_unmask_irq (struct wm8350 *wm8350,int irq); + +#endif
Signature · 1 line
1.5.6.5
PATCH 13/14 regulator: Add WM8350 regulator support
The WM8350 features six DCDC convertors (four buck and two boost), four LDO voltage regulators and two constant current sinks. This driver adds support for these through the regulator API.
This driver was written by Liam Girdwood with updates for submission from Mark Brown.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/wm8350-core.c | 6 + drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/wm8350-regulator.c | 1431 ++++++++++++++++++++++++++++++++++ include/linux/mfd/wm8350/core.h | 5 + include/linux/mfd/wm8350/pmic.h | 42 + 6 files changed, 1494 insertions(+), 0 deletions(-) create mode 100644 drivers/regulator/wm8350-regulator.c
drivers/mfd/wm8350-core.c +6 -0
@@ -1218,6 +1218,12 @@ EXPORT_SYMBOL_GPL(wm8350_device_init);void wm8350_device_exit (struct wm8350 *wm8350) { +int i; + +for (i =0 ; i <ARRAY_SIZE (wm8350->pmic.pdev); i++) +if (wm8350->pmic.pdev[i] !=NULL ) +platform_device_unregister (wm8350->pmic.pdev[i]); +free_irq (wm8350->chip_irq, wm8350);flush_work (&wm8350->irq_work);kfree (wm8350->reg_cache);
drivers/regulator/Kconfig +9 -0
@@ -56,6 +56,14 @@ config REGULATOR_BQ24022 charging select between 100 mA and 500 mA charging current limit. +config REGULATOR_WM8350 + tristate "Wolfson Microelectroncis WM8350 AudioPlus PMIC" + depends on MFD_WM8350 + select REGULATOR + help + This driver provides support for the voltage and current regulators + of the WM8350 AudioPlus PMIC. + config REGULATOR_WM8400 tristate "Wolfson Microelectroncis WM8400 AudioPlus PMIC" depends on MFD_WM8400
@@ -63,4 +71,5 @@ config REGULATOR_WM8400 help This driver provides support for the voltage regulators of the WM8400 AudioPlus PMIC. + endmenu
drivers/regulator/Makefile +1 -0
@@ -8,6 +8,7 @@ obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += fixed.o obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o +obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
drivers/regulator/wm8350-regulator.c new file +1431 -0
1,431 lines not on this page · raw message
include/linux/mfd/wm8350/core.h +5 -0
@@ -17,6 +17,8 @@#include <linux/mutex.h> #include <linux/workqueue.h> +#include <linux/mfd/wm8350/pmic.h> +/* * Register values. */
@@ -570,6 +572,9 @@ struct wm8350 {struct mutex irq_mutex;/* IRQ table mutex */ struct wm8350_irq irq[WM8350_NUM_IRQ ];int chip_irq; + +/* Client devices */ +struct wm8350_pmic pmic; };/**
include/linux/mfd/wm8350/pmic.h +42 -0
46 lines not on this page · raw message
Signature · 1 line
1.5.6.5
PATCH 14/14 mfd: Add WM8350 subdevice registration helper
Most of the subdevices for the WM8350 code are registered in the same fashion so factor out the code to do the initial registration.
Signed-off-by Mark Brown <[email protected]>
--- drivers/mfd/wm8350-core.c | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-)
drivers/mfd/wm8350-core.c +26 -0
@@ -1130,6 +1130,32 @@ out: }EXPORT_SYMBOL_GPL (wm8350_create_cache); +/* +* Register a client device. This is non-fatal since there is no need to +* fail the entire device init due to a single platform device failing. +*/ +static void wm8350_client_dev_register (struct wm8350 *wm8350, +const char *name, +struct platform_device **pdev) +{ +int ret; + + *pdev =platform_device_alloc (name,-1 ); +if (pdev ==NULL ) { +dev_err (wm8350->dev,"Failed to allocate %s\n" , name); +return ; + } + + (*pdev)->dev.parent = wm8350->dev; +platform_set_drvdata (*pdev, wm8350); + ret =platform_device_add (*pdev); +if (ret !=0 ) { +dev_err (wm8350->dev,"Failed to register %s: %d\n" , name, ret); +platform_device_put (*pdev); + *pdev =NULL ; + } +} +int wm8350_device_init (struct wm8350 *wm8350,int irq,struct wm8350_platform_data *pdata) {
Signature · 1 line
1.5.6.5
Re: [PATCH 14/14] mfd: Add WM8350 subdevice registration helper
Quoted 2 lines · Mark Brown
Most of the subdevices for the WM8350 code are registered in the same fashion so factor out the code to do the initial registration.
Out of curiosity (and also because I would like to start working on improving mfd-core), why didnt you consider using the mfd-core API ?
Cheers,
Samuel.
Quoted 45 lines
Signed-off-by Mark Brown <[email protected]>--- drivers/mfd/wm8350-core.c | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-)drivers/mfd/wm8350-core.c +26
-0@@ -1130,6 +1130,32 @@ out: }EXPORT_SYMBOL_GPL (wm8350_create_cache); +/* +* Register a client device. This is non-fatal since there is no need to +* fail the entire device init due to a single platform device failing. +*/ +static void wm8350_client_dev_register (struct wm8350 *wm8350, +const char *name, +struct platform_device **pdev) +{ +int ret; + + *pdev =platform_device_alloc (name,-1 ); +if (pdev ==NULL ) { +dev_err (wm8350->dev,"Failed to allocate %s\n" , name); +return ; + } + + (*pdev)->dev.parent = wm8350->dev; +platform_set_drvdata (*pdev, wm8350); + ret =platform_device_add (*pdev); +if (ret !=0 ) { +dev_err (wm8350->dev,"Failed to register %s: %d\n" , name, ret); +platform_device_put (*pdev); + *pdev =NULL ; + } +} +int wm8350_device_init (struct wm8350 *wm8350,int irq,struct wm8350_platform_data *pdata) {Signature · 1 line
1.5.6.5
Signature · 2 lines
Intel Open Source Technology Centre http://oss.intel.com/
Re: [PATCH 14/14] mfd: Add WM8350 subdevice registration helper
Quoted 7 lines · Samuel Ortiz
Quoted 2 lines · Mark Brown
Most of the subdevices for the WM8350 code are registered in the same fashion so factor out the code to do the initial registration.
Out of curiosity (and also because I would like to start working on improving mfd-core), why didnt you consider using the mfd-core API ?
I did actually consider that - if it hadn't been so near the merge window it'd have got a bit more attention but I'd been going for a minimally invasive approach.
Originally the major issue was that the MFD API only worked for platform devices but that has now been resolved. Now the main issue for the WM8350 is that the MFD core API uses platform_device_add_resources() unconditionally but that fails if the device has no resources as will be the case for anything on the WM8350, at least until I integrate the
interrupt controller with the standard interrupt interface. The MFD
core does ignore the result of the call currently but it probably shouldn't and I didn't want to rely on it continuing to do so. The patch below ought to address that, though it's tested with my "Hey, look! It compiles!" test plan - if it looks sane to you I'll give it a test and repost with a proper changelog.
It's not an issue for the WM8350 but some devices with interrupt controllers may have issues since currently the MFD API wants to put all the interrupts within a per-device range but for some devices there will be interrupts exposed via separate IRQ lines (so you don't have to take the hit of working with an I2C/SPI interrupt controller) meaning that some of the interrupts for subdevices may be in different ranges. For the WM8350 this isn't such a problem since everything *can* go via the main interrupt controller and overrides can be provided via platform data (as they are at present, though the main interrupt controller doesn't use the standard API) but if use of a separate interrupt line were non-optional it'd be a problem.
There's also the issue of passing over the pointer to the shared device data for arbitration - you can use platform data but the MFD API wants to copy it so it's a bit fiddly. I'm thinking that the sensible thing may just be to have the child devices use the parent link in the device tree for this which is already fine with the MFD core.
drivers/mfd/mfd-core.c +6 -1
@@ -60,7 +60,12 @@ static int mfd_add_device(struct device *parent, int id, } } -platform_device_add_resources (pdev, res, cell->num_resources); +if (cell->num_resources) { + ret =platform_device_add_resources (pdev, res, + cell->num_resources); +if (ret) + goto fail_device; + } ret =platform_device_add (pdev);if (ret)
Re: [PATCH 10/14] mfd: Add GPIO pin configuration support for WM8350
In reply to Mark BrownQuoted 9 lines · Mark Brown
The WM8350 provides a number of user-configurable pins providing access to various signals generated by the functions on the chip. These are referred to as GPIO pins in the device documentation but in Linux terms they are more general than that, providing configuration of alternate functions.
This patch implements support for selecting the alternate functions for these pins. They can also be used as GPIOs in the normal Linux sense - a subsequent patch will add support for doing so.
I expect it to implement the giolib interface, right ?
Cheers,
Samuel.
Quoted 274 lines
This code was all written by Liam Girdwood and has had minor updates and rearrangements by Mark Brown.
Signed-off-by Mark Brown <[email protected]>--- drivers/mfd/Makefile | 2 +- drivers/mfd/wm8350-gpio.c | 222 +++++++++++++++++++++++++++++++++++++++ include/linux/mfd/wm8350/gpio.h | 10 ++ 3 files changed, 233 insertions(+), 1 deletions(-) create mode 100644 drivers/mfd/wm8350-gpio.cdrivers/mfd/Makefile +1
-1@@ -13,7 +13,7 @@ obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o obj-$(CONFIG_MFD_WM8400) += wm8400-core.o -wm8350-objs := wm8350-core.o wm8350-regmap.o +wm8350-objs := wm8350-core.o wm8350-regmap.o wm8350-gpio.o obj-$(CONFIG_MFD_WM8350) += wm8350.o obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.odrivers/mfd/wm8350-gpio.c new file +222
-0@@ -0,0 +1,222 @@ +/* +* wm8350-core.c -- Device access for Wolfson WM8350 +* +* Copyright 2007, 2008 Wolfson Microelectronics PLC. +* +* Author: Liam Girdwood +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +*/ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/errno.h> + +#include <linux/mfd/wm8350/core.h> +#include <linux/mfd/wm8350/gpio.h> +#include <linux/mfd/wm8350/pmic.h> + +static int gpio_set_dir (struct wm8350 *wm8350,int gpio,int dir) +{ +int ret; + +wm8350_reg_unlock (wm8350); +if (dir ==WM8350_GPIO_DIR_OUT ) + ret =wm8350_clear_bits (wm8350, +WM8350_GPIO_CONFIGURATION_I_O , +1 << gpio); +else + ret =wm8350_set_bits (wm8350, +WM8350_GPIO_CONFIGURATION_I_O , +1 << gpio); +wm8350_reg_lock (wm8350); +return ret; +} + +static int gpio_set_debounce (struct wm8350 *wm8350,int gpio,int db) +{ +if (db ==WM8350_GPIO_DEBOUNCE_ON ) +return wm8350_set_bits (wm8350,WM8350_GPIO_DEBOUNCE , +1 << gpio); +else +return wm8350_clear_bits (wm8350, +WM8350_GPIO_DEBOUNCE ,1 << gpio); +} + +static int gpio_set_func (struct wm8350 *wm8350,int gpio,int func) +{ +u16 reg; + +wm8350_reg_unlock (wm8350); +switch (gpio) { +case 0 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_1 ) + & ~WM8350_GP0_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_1 , + reg | ((func &0xf ) <<0 )); +break ; +case 1 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_1 ) + & ~WM8350_GP1_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_1 , + reg | ((func &0xf ) <<4 )); +break ; +case 2 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_1 ) + & ~WM8350_GP2_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_1 , + reg | ((func &0xf ) <<8 )); +break ; +case 3 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_1 ) + & ~WM8350_GP3_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_1 , + reg | ((func &0xf ) <<12 )); +break ; +case 4 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_2 ) + & ~WM8350_GP4_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_2 , + reg | ((func &0xf ) <<0 )); +break ; +case 5 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_2 ) + & ~WM8350_GP5_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_2 , + reg | ((func &0xf ) <<4 )); +break ; +case 6 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_2 ) + & ~WM8350_GP6_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_2 , + reg | ((func &0xf ) <<8 )); +break ; +case 7 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_2 ) + & ~WM8350_GP7_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_2 , + reg | ((func &0xf ) <<12 )); +break ; +case 8 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_3 ) + & ~WM8350_GP8_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_3 , + reg | ((func &0xf ) <<0 )); +break ; +case 9 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_3 ) + & ~WM8350_GP9_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_3 , + reg | ((func &0xf ) <<4 )); +break ; +case 10 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_3 ) + & ~WM8350_GP10_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_3 , + reg | ((func &0xf ) <<8 )); +break ; +case 11 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_3 ) + & ~WM8350_GP11_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_3 , + reg | ((func &0xf ) <<12 )); +break ; +case 12 : + reg =wm8350_reg_read (wm8350,WM8350_GPIO_FUNCTION_SELECT_4 ) + & ~WM8350_GP12_FN_MASK ; +wm8350_reg_write (wm8350,WM8350_GPIO_FUNCTION_SELECT_4 , + reg | ((func &0xf ) <<0 )); +break ; +default : +wm8350_reg_lock (wm8350); +return -EINVAL ; + } + +wm8350_reg_lock (wm8350); +return 0 ; +} + +static int gpio_set_pull_up (struct wm8350 *wm8350,int gpio,int up) +{ +if (up) +return wm8350_set_bits (wm8350, +WM8350_GPIO_PIN_PULL_UP_CONTROL , +1 << gpio); +else +return wm8350_clear_bits (wm8350, +WM8350_GPIO_PIN_PULL_UP_CONTROL , +1 << gpio); +} + +static int gpio_set_pull_down (struct wm8350 *wm8350,int gpio,int down) +{ +if (down) +return wm8350_set_bits (wm8350, +WM8350_GPIO_PULL_DOWN_CONTROL , +1 << gpio); +else +return wm8350_clear_bits (wm8350, +WM8350_GPIO_PULL_DOWN_CONTROL , +1 << gpio); +} + +static int gpio_set_polarity (struct wm8350 *wm8350,int gpio,int pol) +{ +if (pol ==WM8350_GPIO_ACTIVE_HIGH ) +return wm8350_set_bits (wm8350, +WM8350_GPIO_PIN_POLARITY_TYPE , +1 << gpio); +else +return wm8350_clear_bits (wm8350, +WM8350_GPIO_PIN_POLARITY_TYPE , +1 << gpio); +} + +static int gpio_set_invert (struct wm8350 *wm8350,int gpio,int invert) +{ +if (invert ==WM8350_GPIO_INVERT_ON ) +return wm8350_set_bits (wm8350,WM8350_GPIO_INT_MODE ,1 << gpio); +else +return wm8350_clear_bits (wm8350, +WM8350_GPIO_INT_MODE ,1 << gpio); +} + +int wm8350_gpio_config (struct wm8350 *wm8350,int gpio,int dir,int func, +int pol,int pull,int invert,int debounce) +{ +/* make sure we never pull up and down at the same time */ +if (pull ==WM8350_GPIO_PULL_NONE ) { +if (gpio_set_pull_up (wm8350, gpio,0 )) + goto err; +if (gpio_set_pull_down (wm8350, gpio,0 )) + goto err; + }else if (pull ==WM8350_GPIO_PULL_UP ) { +if (gpio_set_pull_down (wm8350, gpio,0 )) + goto err; +if (gpio_set_pull_up (wm8350, gpio,1 )) + goto err; + }else if (pull ==WM8350_GPIO_PULL_DOWN ) { +if (gpio_set_pull_up (wm8350, gpio,0 )) + goto err; +if (gpio_set_pull_down (wm8350, gpio,1 )) + goto err; + } + +if (gpio_set_invert (wm8350, gpio, invert)) + goto err; +if (gpio_set_polarity (wm8350, gpio, pol)) + goto err; +if (gpio_set_debounce (wm8350, gpio, debounce)) + goto err; +if (gpio_set_dir (wm8350, gpio, dir)) + goto err; +return gpio_set_func (wm8350, gpio, func); + +err: +return -EIO ; +} +EXPORT_SYMBOL_GPL (wm8350_gpio_config);include/linux/mfd/wm8350/gpio.h +10
-0@@ -323,4 +323,14 @@#define WM8350_GP1_LVL 0x0002#define WM8350_GP0_LVL 0x0001 +struct wm8350 ; + +int wm8350_gpio_config (struct wm8350 *wm8350,int gpio,int dir,int func, +int pol,int pull,int invert,int debounce); + +/* +* GPIO Interrupts +*/ +#define WM8350_IRQ_GPIO (x) (50 + x) +#endif Signature · 1 line
1.5.6.5
Re: [PATCH 10/14] mfd: Add GPIO pin configuration support for WM8350
Quoted 6 lines · Samuel Ortiz
Quoted 2 lines · Mark Brown
these pins. They can also be used as GPIOs in the normal Linux sense - a subsequent patch will add support for doing so.
I expect it to implement the giolib interface, right ?
Yes, that's the intention.
Hi Liam,
Quoted 7 lines · Liam Girdwood
Quoted 6 lines · Mark Brown
Quoted 3 lines · Samuel Ortiz
Sorry guys, but I havent had time to look at those patches yet. Liam, when would be the last moment for me to ACK/NACK them ? I expect to be able to do so during this weekend.
Quoted 7 lines
Quoted 5 lines
I've done some updates since the original posting incorporating feedback from Liam and an update for the regulator API - do you want me to repost with those? They're sitting in:
git://opensource.wolfsonmicro.com/linux-2.6-audioplusfor-lrgYes please.
I'm fine with Mark's mfd patches going upstream via your tree. Please add an "Acked-by: Samuel Ortiz <[email protected]>" line to all the mfd patches (i.e. all of them except patch #13).
Thanks to Mark and you for those.
Cheers,
Samuel.
Quoted 4 lines
Thanks
Liam
Signature · 2 lines
Intel Open Source Technology Centre http://oss.intel.com/
Quoted 11 lines · Mark Brown
Quoted 3 lines · Samuel Ortiz
Sorry guys, but I havent had time to look at those patches yet. Liam, when would be the last moment for me to ACK/NACK them ? I expect to be able to do so during this weekend.
I've done some updates since the original posting incorporating feedback from Liam and an update for the regulator API - do you want me to repost with those? They're sitting in:
git://opensource.wolfsonmicro.com/linux-2.6-audioplusfor-lrg
I'm fine with the git URL for now, thanks.
Cheers,
Samuel.
Signature · 2 lines
Intel Open Source Technology Centre http://oss.intel.com/
Quoted 13 lines · Samuel Ortiz
Quoted 12 lines · Liam Girdwood
Quoted 11 lines · Mark Brown
These patches against the regulator tree add initial support for the WM8350, a multi-function device with several subsystems targetted at embedded systems. This series adds a core driver providing device acess under
drivers/mfdand support for the PMIC functionality of the device via the regulator API. Due to their use in the core some definitions for other parts of the device are also included - drivers for these will follow.All the WM8350 drivers submitted here were originally written by Liam Girdwood with some updates from me for submission to mainline.
Quoted 7 lines
Quoted 4 lines
Quoted 2 lines
Samuel, as with the WM8400 are you OK with merging this via the regulator tree?
Samuel, are fine to Ack the MFD parts ?
Sorry guys, but I havent had time to look at those patches yet. Liam, when would be the last moment for me to ACK/NACK them ? I expect to be able to do so during this weekend.
That would be fine. The intention is to do a pull request later next week. Fwiw, most of the MFD stuff in this series is headers so should be quick.
Cheers
Liam