85xx/85xx pci cleanup

PATCH New Kumar Gala 5 participants 20 messages Oct 23, 2008 – Oct 24, 2008 PCI

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Kumar Gala

author

2008-10-23 06:26 UTC #0 lore raw

cover 85xx/85xx pci cleanup

This patch series adds the ability to support 64-bit PCI addresses as well as refactors the fsl_pci_init code and cleans up its users.

Finally it adds some help functions that the board code calls to set dma-ranges in device trees.

If the particular maintainers could ack the patches that would be great (Andy, Jon, Jerry).

- k

Kumar Gala

author

2008-10-23 06:26 UTC #1 lore raw

PATCH 1/10 pci: Allow for PCI addresses to be 64-bit

PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT.

Signed-off-by Kumar Gala <[email protected]>

---
 drivers/pci/pci.c      |   37 ++++++++++++++------
 drivers/pci/pci_auto.c |   88 ++++++++++++++++++++++++++++-------------------
 include/pci.h          |   40 +++++++++++++---------
 3 files changed, 102 insertions(+), 63 deletions(-)

drivers/pci/pci.c +26 ~~-11~~

index 41780db..e2b05d8 100644
@@ -218,12 +218,12 @@ pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
  *
  */
 
-unsigned long pci_hose_phys_to_bus (struct pci_controller *hose,
+pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
 				    phys_addr_t phys_addr,
 				    unsigned long flags)
 {
 	struct pci_region *res;
-	unsigned long bus_addr;
+	pci_addr_t bus_addr;
 	int i;
 
 	if (!hose) {

@@ -252,7 +252,7 @@ Done:
 }
 
 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
-				 unsigned long bus_addr,
+				 pci_addr_t bus_addr,
 				 unsigned long flags)
 {
 	struct pci_region *res;

@@ -288,15 +288,17 @@ Done:
 int pci_hose_config_device(struct pci_controller *hose,
 			   pci_dev_t dev,
 			   unsigned long io,
-			   unsigned long mem,
+			   pci_addr_t mem,
 			   unsigned long command)
 {
-	unsigned int bar_response, bar_size, bar_value, old_command;
+	unsigned int bar_response, old_command;
+	pci_addr_t bar_value;
+	pci_size_t bar_size;
 	unsigned char pin;
 	int bar, found_mem64;
 
-	debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
-		io, mem, command);
+	debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
+		io, (u64)mem, command);
 
 	pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);

@@ -319,10 +321,19 @@ int pci_hose_config_device(struct pci_controller *hose,
 			io = io + bar_size;
 		} else {
 			if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
-				PCI_BASE_ADDRESS_MEM_TYPE_64)
-				found_mem64 = 1;
+				PCI_BASE_ADDRESS_MEM_TYPE_64) {
+				u32 bar_response_upper;
+				u64 bar64;
+				pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
+				pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
 
-			bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+				bar64 = ((u64)bar_response_upper << 32) | bar_response;
+
+				bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+				found_mem64 = 1;
+			} else {
+				bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
+			}
 
 			/* round up region base address to multiple of size */
 			mem = ((mem - 1) | (bar_size - 1)) + 1;

@@ -332,11 +343,15 @@ int pci_hose_config_device(struct pci_controller *hose,
 		}
 
 		/* Write it out and update our limit */
-		pci_hose_write_config_dword (hose, dev, bar, bar_value);
+		pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
 
 		if (found_mem64) {
 			bar += 4;
+#ifdef CONFIG_SYS_PCI_64BIT
+			pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
+#else
 			pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
+#endif
 		}
 	}

drivers/pci/pci_auto.c +52 ~~-36~~

154 lines not on this page · raw message

include/pci.h +24 ~~-16~~

index 1c8e216..eebe8a8 100644
@@ -101,8 +101,8 @@
 #define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
 #define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
 #define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
-#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
-#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
+#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fULL)
+#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03ULL)
 /* bit 1 is reserved if address_space = 1 */
 
 /* Header type 0 (normal devices) */

@@ -111,7 +111,7 @@
 #define PCI_SUBSYSTEM_ID	0x2e
 #define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
 #define  PCI_ROM_ADDRESS_ENABLE 0x01
-#define PCI_ROM_ADDRESS_MASK	(~0x7ffUL)
+#define PCI_ROM_ADDRESS_MASK	(~0x7ffULL)
 
 #define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */

@@ -312,13 +312,21 @@
 
 #include <pci_ids.h>
 
+#ifdef CONFIG_SYS_PCI_64BIT
+typedef u64 pci_addr_t;
+typedef u64 pci_size_t;
+#else
+typedef u32 pci_addr_t;
+typedef u32 pci_size_t;
+#endif
+
 struct pci_region {
-	unsigned long bus_start;		/* Start on the bus */
-	phys_addr_t phys_start;			/* Start in physical address space */
-	unsigned long size;			/* Size */
-	unsigned long flags;			/* Resource flags */
+	pci_addr_t bus_start;	/* Start on the bus */
+	phys_addr_t phys_start;	/* Start in physical address space */
+	pci_size_t size;	/* Size */
+	unsigned long flags;	/* Resource flags */
 
-	unsigned long bus_lower;
+	pci_addr_t bus_lower;
 };
 
 #define PCI_REGION_MEM		0x00000000	/* PCI memory space */

@@ -330,9 +338,9 @@ struct pci_region {
 #define PCI_REGION_RO		0x00000200	/* Read-only memory */
 
 extern __inline__ void pci_set_region(struct pci_region *reg,
-				      unsigned long bus_start,
+				      pci_addr_t bus_start,
 				      phys_addr_t phys_start,
-				      unsigned long size,
+				      pci_size_t size,
 				      unsigned long flags) {
 	reg->bus_start	= bus_start;
 	reg->phys_start = phys_start;

@@ -433,9 +441,9 @@ extern __inline__ void pci_set_ops(struct pci_controller *hose,
 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
 
 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
-					unsigned long addr, unsigned long flags);
-extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
-					  phys_addr_t addr, unsigned long flags);
+					pci_addr_t addr, unsigned long flags);
+extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
+					phys_addr_t addr, unsigned long flags);
 
 #define pci_phys_to_bus(dev, addr, flags) \
 	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))

@@ -483,8 +491,8 @@ extern int pci_hose_scan(struct pci_controller *hose);
 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
 
 extern void pciauto_region_init(struct pci_region* res);
-extern void pciauto_region_align(struct pci_region *res, unsigned long size);
-extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
+extern void pciauto_region_align(struct pci_region *res, pci_size_t size);
+extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar);
 extern void pciauto_setup_device(struct pci_controller *hose,
 				 pci_dev_t dev, int bars_num,
 				 struct pci_region *mem,

@@ -500,7 +508,7 @@ extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
 extern int pci_hose_config_device(struct pci_controller *hose,
 				  pci_dev_t dev,
 				  unsigned long io,
-				  unsigned long mem,
+				  pci_addr_t mem,
 				  unsigned long command);
 
 #ifdef CONFIG_MPC824X

Signature · 1 line

1.5.5.1

Kumar Gala

author

2008-10-23 06:26 UTC #2 lore raw

PATCH 2/10 85xx: Enable 64-bit PCI resources on all Freescale boards

Signed-off-by Kumar Gala <[email protected]>

---
 include/configs/MPC8536DS.h  |    1 +
 include/configs/MPC8540ADS.h |    1 +
 include/configs/MPC8541CDS.h |    1 +
 include/configs/MPC8544DS.h  |    1 +
 include/configs/MPC8548CDS.h |    1 +
 include/configs/MPC8555CDS.h |    1 +
 include/configs/MPC8560ADS.h |    1 +
 include/configs/MPC8568MDS.h |    1 +
 include/configs/MPC8572DS.h  |    1 +
 9 files changed, 9 insertions(+), 0 deletions(-)

include/configs/MPC8536DS.h +1 -0

index 38be10d..d990f11 100644
@@ -41,6 +41,7 @@
 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */

include/configs/MPC8540ADS.h +1 -0

index 5a14969..79a52d9 100644
@@ -46,6 +46,7 @@
 #endif
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */

include/configs/MPC8541CDS.h +1 -0

index eede26a..7ada8a2 100644
@@ -38,6 +38,7 @@
 #define CONFIG_MPC8541CDS	1	/* MPC8541CDS board specific */
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE

include/configs/MPC8544DS.h +1 -0

index 0987448..c47374a 100644
@@ -41,6 +41,7 @@
 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */

include/configs/MPC8548CDS.h +1 -0

index 892c52e..b67de56 100644
@@ -43,6 +43,7 @@
 #undef CONFIG_PCI2
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE

include/configs/MPC8555CDS.h +1 -0

index 41870f1..f9419cc 100644
@@ -38,6 +38,7 @@
 #define CONFIG_MPC8555CDS	1	/* MPC8555CDS board specific */
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */

include/configs/MPC8560ADS.h +1 -0

index 0d3a500..f67d489 100644
@@ -43,6 +43,7 @@
 #define CONFIG_MPC8560		1
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE

include/configs/MPC8568MDS.h +1 -0

index ba2f152..c4d4374 100644
@@ -38,6 +38,7 @@
 #define CONFIG_PCIE1		1	/* PCIE controller */
 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE

include/configs/MPC8572DS.h +1 -0

index 5688589..06696f0 100644
@@ -42,6 +42,7 @@
 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */

Signature · 1 line

1.5.5.1

Kumar Gala

author

2008-10-23 06:26 UTC #3 lore raw

PATCH 3/10 86xx: Enable 64-bit PCI resources on all Freescale boards

Signed-off-by Kumar Gala <[email protected]>

---
 include/configs/MPC8610HPCD.h |    1 +
 include/configs/MPC8641HPCN.h |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

include/configs/MPC8610HPCD.h +1 -0

index 678e1e1..0492274 100644
@@ -41,6 +41,7 @@
 #define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
 #define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 #define CONFIG_ENV_OVERWRITE

include/configs/MPC8641HPCN.h +1 -0

index e5710c0..ceb2c69 100644
@@ -49,6 +49,7 @@
 #define CONFIG_PCI1		1	/* PCIE controler 1 (ULI bridge) */
 #define CONFIG_PCI2		1	/* PCIE controler 2 (slot) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */

Signature · 1 line

1.5.5.1

Kumar Gala

author

2008-10-23 06:26 UTC #4 lore raw

PATCH 4/10 fdt: Add fdt_sizecell & fdt_addrcell helpers

Add helper functions to return top level #size-cell and #address-cell info

Signed-off-by Kumar Gala <[email protected]>

---
 include/fdt_support.h |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

include/fdt_support.h +18 -0

index ceaadc2..aa9d86b 100644
@@ -28,6 +28,24 @@
 
 #include <fdt.h>
 
+static inline int fdt_addrcell(void *blob) {
+	const u32 *addrcell = fdt_getprop(blob, 0, "#address-cells", NULL);
+
+	if (addrcell)
+		return *addrcell;
+	else
+		return 1;
+}
+
+static inline int fdt_sizecell(void *blob) {
+	const u32 *sizecell = fdt_getprop(blob, 0, "#size-cells", NULL);
+
+	if (sizecell)
+		return *sizecell;
+	else
+		return 1;
+}
+
 int fdt_chosen(void *fdt, int force);
 int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
 void do_fixup_by_path(void *fdt, const char *path, const char *prop,

Signature · 1 line

1.5.5.1

Kumar Gala

author

2008-10-23 06:26 UTC #5 lore raw

PATCH 5/10 fdt: Added helper to set PCI dma-ranges property

Added fdt_pci_dma_ranges() that parses the pci_region info from the struct pci_controller and populates the dma-ranges based on it.

The max # of windws/dma-ranges we support is 3 since on embedded PowerPC based systems this is the max number of windows.

Signed-off-by Kumar Gala <[email protected]>

---
 common/fdt_support.c  |   69 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/fdt_support.h |    5 +++
 2 files changed, 74 insertions(+), 0 deletions(-)

common/fdt_support.c +69 -0

index 8ceeb0f..9f1cc3d 100644
@@ -593,3 +593,72 @@ int fdt_resize(void *blob)
 
 	return actualsize;
 }
+
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_PCI_NR_INBOUND_WIN 3
+
+#define FDT_PCI_PREFETCH	(0x40000000)
+#define FDT_PCI_MEM32		(0x02000000)
+#define FDT_PCI_IO		(0x01000000)
+#define FDT_PCI_MEM64		(0x03000000)
+
+int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) {
+
+	int addrcell, sizecell, len, r;
+	u32 *dma_range;
+	/* sized based on pci addr cells, size-cells, & address-cells */
+	u32 dma_ranges[(3 + 2 + 2) * CONFIG_SYS_PCI_NR_INBOUND_WIN];
+
+	addrcell = fdt_addrcell(blob);
+	sizecell = fdt_sizecell(blob);
+
+	dma_range = &dma_ranges[0];
+	for (r = 0; r < hose->region_count; r++) {
+		u64 bus_start, phys_start, size;
+
+		/* skip if !PCI_REGION_MEMORY */
+		if (!(hose->regions[r].flags & PCI_REGION_MEMORY))
+			continue;
+
+		bus_start = (u64)hose->regions[r].bus_start;
+		phys_start = (u64)hose->regions[r].phys_start;
+		size = (u64)hose->regions[r].size;
+
+		dma_range[0] = 0;
+		if (size > 0x100000000ull)
+			dma_range[0] |= FDT_PCI_MEM64;
+		else
+			dma_range[0] |= FDT_PCI_MEM32;
+		if (hose->regions[r].flags & PCI_REGION_PREFETCH)
+			dma_range[0] |= FDT_PCI_PREFETCH;
+#ifdef CONFIG_SYS_PCI_64BIT
+		dma_range[1] = bus_start >> 32;
+#else
+		dma_range[1] = 0;
+#endif
+		dma_range[2] = bus_start & 0xffffffff;
+
+		if (addrcell == 2) {
+			dma_range[3] = phys_start >> 32;
+			dma_range[4] = phys_start & 0xffffffff;
+		} else {
+			dma_range[3] = phys_start & 0xffffffff;
+		}
+
+		if (sizecell == 2) {
+			dma_range[3 + addrcell + 0] = size >> 32;
+			dma_range[3 + addrcell + 1] = size & 0xffffffff;
+		} else {
+			dma_range[3 + addrcell + 0] = size & 0xffffffff;
+		}
+
+		dma_range += (3 + addrcell + sizecell);
+	}
+
+	len = dma_range - &dma_ranges[0];
+	if (len)
+		fdt_setprop(blob, phb_off, "dma-ranges", &dma_ranges[0], len*4);
+
+	return 0;
+}
+#endif

include/fdt_support.h +5 -0

index aa9d86b..5c932de 100644
@@ -81,6 +81,11 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev);
 static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
 #endif
 
+#ifdef CONFIG_PCI
+#include <pci.h>
+int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
+#endif
+
 #ifdef CONFIG_OF_BOARD_SETUP
 void ft_board_setup(void *blob, bd_t *bd);
 void ft_cpu_setup(void *blob, bd_t *bd);

Signature · 1 line

1.5.5.1

Kumar Gala

author

2008-10-23 06:26 UTC #6 lore raw

PATCH 6/10 pci/fsl_pci_init: Enable larger address and setting inbound windows properly

* PCI Inbound window was setup incorrectly. The PCI address and system address were swapped. The PCI address should be setting piwar/piwbear and the system address should be setting pitar.

* Removed masking of addresses to allow for system address to support system address & PCI address >32-bits

* Set PIWBEAR & POTEAR to allow for full 64-bit PCI addresses

* Respect the PCI_REGION_PREFETCH for inbound windows

Signed-off-by Kumar Gala <[email protected]>

---
 drivers/pci/fsl_pci_init.c |   38 ++++++++++++++++++++++++--------------
 1 files changed, 24 insertions(+), 14 deletions(-)

drivers/pci/fsl_pci_init.c +24 ~~-14~~

index 38a16e5..f41c8aa 100644
@@ -39,10 +39,9 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 				pci_dev_t dev, int sub_bus);
 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 				pci_dev_t dev, int sub_bus);
-
 void pciauto_config_init(struct pci_controller *hose);
-void
-fsl_pci_init(struct pci_controller *hose)
+
+void fsl_pci_init(struct pci_controller *hose)
 {
 	u16 temp16;
 	u32 temp32;

@@ -65,25 +64,36 @@ fsl_pci_init(struct pci_controller *hose)
 #endif
 
 	for (r=0; r<hose->region_count; r++) {
+		u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
 		if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
-			pi->pitar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
-			pi->piwbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
+			u32 flag = PIWAR_EN | PIWAR_LOCAL | \
+					PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+			pi->pitar = (hose->regions[r].phys_start >> 12);
+			pi->piwbar = (hose->regions[r].bus_start >> 12);
+#ifdef CONFIG_SYS_PCI_64BIT
+			pi->piwbear = (hose->regions[r].bus_start >> 44);
+#else
 			pi->piwbear = 0;
-			pi->piwar = PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
-				PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP |
-				(__ilog2(hose->regions[r].size) - 1);
+#endif
+			if (hose->regions[r].flags & PCI_REGION_PREFETCH)
+				flag |= PIWAR_PF;
+			pi->piwar = flag | sz;
 			pi++;
 			inbound = hose->regions[r].size > 0;
 		} else { /* Outbound */
-			po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
-			po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
+			po->powbar = (hose->regions[r].phys_start >> 12);
+			po->potar = (hose->regions[r].bus_start >> 12);
+#ifdef CONFIG_SYS_PCI_64BIT
+			po->potear = (hose->regions[r].bus_start >> 44);
+#else
 			po->potear = 0;
+#endif
 			if (hose->regions[r].flags & PCI_REGION_IO)
-				po->powar = POWAR_EN | POWAR_IO_READ | POWAR_IO_WRITE |
-					(__ilog2(hose->regions[r].size) - 1);
+				po->powar = POWAR_EN | sz | \
+					POWAR_IO_READ | POWAR_IO_WRITE;
 			else
-				po->powar = POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE |
-					(__ilog2(hose->regions[r].size) - 1);
+				po->powar = POWAR_EN | sz | \
+					POWAR_MEM_READ | POWAR_MEM_WRITE;
 			po++;
 		}
 	}

Signature · 1 line

1.5.5.1

Kumar Gala

author

2008-10-23 06:26 UTC #7 lore raw

PATCH 7/10 pci/fsl_pci_init: Add a common PCI inbound setup function

Add a common setup function that determines the pci_region(s) based on how much memory we have in the system.

Signed-off-by Kumar Gala <[email protected]>

---
 drivers/pci/fsl_pci_init.c |   81 ++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 81 insertions(+), 0 deletions(-)

drivers/pci/fsl_pci_init.c +81 -0

index f41c8aa..564459c 100644
@@ -18,6 +18,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  *

@@ -41,6 +43,85 @@ void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 				pci_dev_t dev, int sub_bus);
 void pciauto_config_init(struct pci_controller *hose);
 
+#ifndef CONFIG_SYS_PCI_MEMORY_BUS
+#define CONFIG_SYS_PCI_MEMORY_BUS 0
+#endif
+
+#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
+#define CONFIG_SYS_PCI_MEMORY_PHYS 0
+#endif
+
+#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
+#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
+#endif
+
+int fsl_pci_setup_inbound_windows(struct pci_region *r)
+{
+	struct pci_region *rgn_base = r;
+	u64 sz = min((u64)gd->ram_size, 1ull << 32);
+
+	phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
+	pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
+	pci_size_t pci_sz = 1ull << __ilog2_u64(sz);
+
+	debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
+		(u64)bus_start, (u64)phys_start, (u64)pci_sz);
+	pci_set_region(r++, bus_start, phys_start, pci_sz,
+			PCI_REGION_MEM | PCI_REGION_MEMORY | \
+			PCI_REGION_PREFETCH);
+
+	sz -= pci_sz;
+	bus_start += pci_sz;
+	phys_start += pci_sz;
+
+	pci_sz = 1ull << __ilog2_u64(sz);
+	if (sz) {
+		debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
+			(u64)bus_start, (u64)phys_start, (u64)pci_sz);
+		pci_set_region(r++, bus_start, phys_start, pci_sz,
+				PCI_REGION_MEM | PCI_REGION_MEMORY | \
+				PCI_REGION_PREFETCH);
+		sz -= pci_sz;
+		bus_start += pci_sz;
+		phys_start += pci_sz;
+	}
+
+#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
+	pci_sz = 1ull << __ilog2_u64(gd->ram_size);
+	/* round up to the next largest power of two */
+	if (gd->ram_size > pci_sz)
+		sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
+	debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
+		(u64)CONFIG_SYS_PCI_MEMORY_BUS,
+		(u64)CONFIG_SYS_PCI_MEMORY_PHYS,
+		(u64)pci_sz);
+	pci_set_region(r++,
+			CONFIG_SYS_PCI_MEMORY_BUS,
+			CONFIG_SYS_PCI_MEMORY_PHYS,
+			pci_sz,
+			PCI_REGION_MEM | PCI_REGION_MEMORY | \
+			PCI_REGION_PREFETCH);
+#else
+	pci_sz = 1ull << __ilog2_u64(sz);
+	if (sz) {
+		debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
+			(u64)bus_start, (u64)phys_start, (u64)pci_sz);
+		pci_set_region(r++, bus_start, phys_start, pci_sz,
+				PCI_REGION_MEM | PCI_REGION_MEMORY | \
+				PCI_REGION_PREFETCH);
+		sz -= pci_sz;
+		bus_start += pci_sz;
+		phys_start += pci_sz;
+	}
+#endif
+
+	if (sz && (((u64)gd->ram_size) < (1ull << 32)))
+		printf("Was not able to map all of memory via "
+			"inbound windows -- %lld remaining\n", sz);
+
+	return r - rgn_base;
+}
+
 void fsl_pci_init(struct pci_controller *hose)
 {
 	u16 temp16;

Signature · 1 line

1.5.5.1

Kumar Gala

author

2008-10-23 06:26 UTC #8 lore raw

PATCH 8/10 pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges

Signed-off-by Kumar Gala <[email protected]>

---
 drivers/pci/fsl_pci_init.c |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

drivers/pci/fsl_pci_init.c +20 -0

index 564459c..b5d868f 100644
@@ -299,3 +299,23 @@ void fsl_pci_init(struct pci_controller *hose)
 		pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
 	}
 }
+
+#ifdef CONFIG_OF_BOARD_SETUP
+#include <libfdt.h>
+#include <fdt_support.h>
+
+void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+			struct pci_controller *hose)
+{
+	int off = fdt_path_offset(blob, pci_alias);
+
+	if (off >= 0) {
+		u32 bus_range[2];
+
+		bus_range[0] = 0;
+		bus_range[1] = hose->last_busno - hose->first_busno;
+		fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
+		fdt_pci_dma_ranges(blob, off, hose);
+	}
+}
+#endif

Signature · 1 line

1.5.5.1

Kumar Gala

author

2008-10-23 06:26 UTC #9 lore raw

PATCH 9/10 85xx: Convert all fsl_pci_init users to new APIs

Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup().

With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards.

Signed-off-by Kumar Gala <[email protected]>

---
 board/atum8548/atum8548.c               |   77 +++++++---------------
 board/freescale/mpc8536ds/mpc8536ds.c   |  110 ++++++++++--------------------
 board/freescale/mpc8544ds/mpc8544ds.c   |  109 ++++++++++--------------------
 board/freescale/mpc8548cds/mpc8548cds.c |   57 +++++-----------
 board/freescale/mpc8568mds/mpc8568mds.c |   56 +++++----------
 board/freescale/mpc8572ds/mpc8572ds.c   |   72 +++++++-------------
 board/sbc8548/sbc8548.c                 |   66 ++++++-------------
 board/tqc/tqm85xx/tqm85xx.c             |   58 ++++++-----------
 include/configs/ATUM8548.h              |    5 --
 include/configs/MPC8536DS.h             |    5 --
 include/configs/MPC8544DS.h             |    5 --
 include/configs/MPC8548CDS.h            |    5 --
 include/configs/MPC8568MDS.h            |    5 --
 include/configs/MPC8572DS.h             |    5 --
 include/configs/TQM85xx.h               |    5 --
 include/configs/sbc8548.h               |    5 --
 16 files changed, 200 insertions(+), 445 deletions(-)

board/atum8548/atum8548.c +25 ~~-52~~

index 2ef19ce..7b7a968 100644
@@ -182,6 +182,9 @@ static struct pci_controller pcie1_hose;
 
 int first_free_busno=0;
 
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
 void
 pci_init_board(void)
 {

@@ -211,10 +214,10 @@ pci_init_board(void)
 #ifdef CONFIG_PCIE1
  {
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_ep = (host_agent == 5);
 	int pcie_configured  = io_sel & 6;
+	struct pci_region *r = hose->regions;
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 		printf ("\n    PCIE1 connected to slot as %s (base address %x)",

@@ -227,36 +230,31 @@ pci_init_board(void)
 		printf ("\n");
 
 		/* inbound */
-		pci_set_region(hose->regions + 0,
-			       CONFIG_SYS_PCI_MEMORY_BUS,
-			       CONFIG_SYS_PCI_MEMORY_PHYS,
-			       CONFIG_SYS_PCI_MEMORY_SIZE,
-			       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		r += fsl_pci_setup_inbound_windows(r);
 
 		/* outbound memory */
-		pci_set_region(hose->regions + 1,
+		pci_set_region(r++,
 			       CONFIG_SYS_PCIE1_MEM_BASE,
 			       CONFIG_SYS_PCIE1_MEM_PHYS,
 			       CONFIG_SYS_PCIE1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
-		pci_set_region(hose->regions + 2,
+		pci_set_region(r++,
 			       CONFIG_SYS_PCIE1_IO_BASE,
 			       CONFIG_SYS_PCIE1_IO_PHYS,
 			       CONFIG_SYS_PCIE1_IO_SIZE,
 			       PCI_REGION_IO);
 
-		hose->region_count = 3;
 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2
 		/* outbound memory */
-		pci_set_region(hose->regions + 3,
+		pci_set_region(r++,
 			       CONFIG_SYS_PCIE1_MEM_BASE2,
 			       CONFIG_SYS_PCIE1_MEM_PHYS2,
 			       CONFIG_SYS_PCIE1_MEM_SIZE2,
 			       PCI_REGION_MEM);
-		hose->region_count++;
 #endif
+		hose->region_count = r - hose->regions;
 		hose->first_busno=first_free_busno;
 
 		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

@@ -279,8 +277,8 @@ pci_init_board(void)
 #ifdef CONFIG_PCI1
 {
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
-	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
+	struct pci_region *r = hose->regions;
 
 	uint pci_agent = (host_agent == 6);
 	uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */

@@ -300,26 +298,22 @@ pci_init_board(void)
 			);
 
 		/* inbound */
-		pci_set_region(hose->regions + 0,
-			       CONFIG_SYS_PCI_MEMORY_BUS,
-			       CONFIG_SYS_PCI_MEMORY_PHYS,
-			       CONFIG_SYS_PCI_MEMORY_SIZE,
-			       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		r += fsl_pci_setup_inbound_windows(r);
 
 		/* outbound memory */
-		pci_set_region(hose->regions + 1,
+		pci_set_region(r++,
 			       CONFIG_SYS_PCI1_MEM_BASE,
 			       CONFIG_SYS_PCI1_MEM_PHYS,
 			       CONFIG_SYS_PCI1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
-		pci_set_region(hose->regions + 2,
+		pci_set_region(r++,
 			       CONFIG_SYS_PCI1_IO_BASE,
 			       CONFIG_SYS_PCI1_IO_PHYS,
 			       CONFIG_SYS_PCI1_IO_SIZE,
 			       PCI_REGION_IO);
-		hose->region_count = 3;
+		hose->region_count = r - hose->regions;
 		hose->first_busno=first_free_busno;
 		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

@@ -340,26 +334,23 @@ pci_init_board(void)
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci2_hose;
+	struct pci_region *r = hose->regions;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
-		pci_set_region(hose->regions + 0,
-			       CONFIG_SYS_PCI_MEMORY_BUS,
-			       CONFIG_SYS_PCI_MEMORY_PHYS,
-			       CONFIG_SYS_PCI_MEMORY_SIZE,
-			       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		r += fsl_pci_setup_inbound_windows(r);
 
-		pci_set_region(hose->regions + 1,
+		pci_set_region(r++,
 			       CONFIG_SYS_PCI2_MEM_BASE,
 			       CONFIG_SYS_PCI2_MEM_PHYS,
 			       CONFIG_SYS_PCI2_MEM_SIZE,
 			       PCI_REGION_MEM);
 
-		pci_set_region(hose->regions + 2,
+		pci_set_region(r++,
 			       CONFIG_SYS_PCI2_IO_BASE,
 			       CONFIG_SYS_PCI2_IO_PHYS,
 			       CONFIG_SYS_PCI2_IO_SIZE,
 			       PCI_REGION_IO);
-		hose->region_count = 3;
+		hose->region_count = r - hose->regions;
 		hose->first_busno=first_free_busno;
 		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

@@ -385,39 +376,21 @@ int last_stage_init(void)
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+                        struct pci_controller *hose);
 
-void
-ft_board_setup(void *blob, bd_t *bd)
+void ft_board_setup(void *blob, bd_t *bd)
 {
-	int node, tmp[2];
-	const char *path;
-
 	ft_cpu_setup(blob, bd);
 
-	node = fdt_path_offset(blob, "/aliases");
-	tmp[0] = 0;
-	if (node >= 0) {
 #ifdef CONFIG_PCI1
-		path = fdt_getprop(blob, node, "pci0", NULL);
-		if (path) {
-			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
+	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 #endif
 #ifdef CONFIG_PCI2
-		path = fdt_getprop(blob, node, "pci1", NULL);
-		if (path) {
-			tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
+	ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
 #endif
 #ifdef CONFIG_PCIE1
-		path = fdt_getprop(blob, node, "pci2", NULL);
-		if (path) {
-			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
+	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 #endif
-	}
 }
 #endif

board/freescale/mpc8536ds/mpc8536ds.c +37 ~~-73~~

261 lines not on this page · raw message

board/freescale/mpc8544ds/mpc8544ds.c +36 ~~-73~~

269 lines not on this page · raw message

board/freescale/mpc8548cds/mpc8548cds.c +19 ~~-38~~

126 lines not on this page · raw message

board/freescale/mpc8568mds/mpc8568mds.c +19 ~~-37~~

127 lines not on this page · raw message

board/freescale/mpc8572ds/mpc8572ds.c +24 ~~-48~~

185 lines not on this page · raw message

board/sbc8548/sbc8548.c +20 ~~-46~~

139 lines not on this page · raw message

board/tqc/tqm85xx/tqm85xx.c +20 ~~-38~~

130 lines not on this page · raw message

include/configs/ATUM8548.h +0 -5

index 2450adb..1b74526 100644
@@ -287,11 +287,6 @@
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 #endif	/* CONFIG_PCI */
 
 #if defined(CONFIG_TSEC_ENET)

include/configs/MPC8536DS.h +0 -5

index d990f11..bdecfa0 100644
@@ -315,11 +315,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */

include/configs/MPC8544DS.h +0 -5

index c47374a..cdbbea6 100644
@@ -276,11 +276,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
 #define CONFIG_SYS_PCIE2_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE

include/configs/MPC8548CDS.h +0 -5

index b67de56..083afba 100644
@@ -420,11 +420,6 @@ extern unsigned long get_clock_freq(void);
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 #endif	/* CONFIG_PCI */

include/configs/MPC8568MDS.h +0 -5

index c4d4374..ab3e6d6 100644
@@ -389,11 +389,6 @@ extern unsigned long get_clock_freq(void);
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE     0x80000000
-
 #endif	/* CONFIG_PCI */
 
 #ifndef CONFIG_NET_MULTI

include/configs/MPC8572DS.h +0 -5

index 06696f0..fbb8970 100644
@@ -336,11 +336,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 #define CONFIG_SYS_PCIE3_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	CONFIG_SYS_PCIE3_MEM_BASE

include/configs/TQM85xx.h +0 -5

index b05f43d..2d4048a 100644
@@ -403,11 +403,6 @@
 #define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
 #define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/*  16M			*/
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 #ifdef CONFIG_PCIE1
 /*
  * General PCI express

include/configs/sbc8548.h +0 -5

index 54f3e66..aefd30a 100644
@@ -387,11 +387,6 @@
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 #endif	/* CONFIG_PCI */

Signature · 1 line

1.5.5.1

Kumar Gala

author

2008-10-23 06:26 UTC #10 lore raw

PATCH 10/10 86xx: Convert all fsl_pci_init users to new APIs

Converted MPC8610HCPD, MPC8641HPCN, and SBC8641D to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup().

With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards.

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8610hpcd/mpc8610hpcd.c |   78 +++++++++--------------------
 board/freescale/mpc8641hpcn/mpc8641hpcn.c |   53 ++++++-------------
 board/sbc8641d/sbc8641d.c                 |   55 +++++++--------------
 include/configs/MPC8610HPCD.h             |    5 --
 include/configs/MPC8641HPCN.h             |    5 --
 include/configs/sbc8641d.h                |    5 --
 6 files changed, 59 insertions(+), 142 deletions(-)

board/freescale/mpc8610hpcd/mpc8610hpcd.c +24 ~~-54~~

index 5faeca1..dacd2a9 100644
@@ -240,6 +240,9 @@ static struct pci_controller pcie2_hose;
 
 int first_free_busno = 0;
 
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
 void pci_init_board(void)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;

@@ -256,11 +259,11 @@ void pci_init_board(void)
 #ifdef CONFIG_PCIE1
  {
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_configured = (io_sel == 1) || (io_sel == 4);
 	int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
 		(host_agent == 5);
+	struct pci_region *r = hose->regions;
 
 	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
 		printf(" PCIe 1 connected to Uli as %s (base address %x)\n",

@@ -270,27 +273,23 @@ void pci_init_board(void)
 			pci->pme_msg_det = 0xffffffff;
 
 		/* inbound */
-		pci_set_region(hose->regions + 0,
-			 CONFIG_SYS_PCI_MEMORY_BUS,
-			 CONFIG_SYS_PCI_MEMORY_PHYS,
-			 CONFIG_SYS_PCI_MEMORY_SIZE,
-			 PCI_REGION_MEM | PCI_REGION_MEMORY);
+		r += fsl_pci_setup_inbound_windows(r);
 
 		/* outbound memory */
-		pci_set_region(hose->regions + 1,
+		pci_set_region(r++,
 			 CONFIG_SYS_PCIE1_MEM_BASE,
 			 CONFIG_SYS_PCIE1_MEM_PHYS,
 			 CONFIG_SYS_PCIE1_MEM_SIZE,
 			 PCI_REGION_MEM);
 
 		/* outbound io */
-		pci_set_region(hose->regions + 2,
+		pci_set_region(r++,
 			 CONFIG_SYS_PCIE1_IO_BASE,
 			 CONFIG_SYS_PCIE1_IO_PHYS,
 			 CONFIG_SYS_PCIE1_IO_SIZE,
 			 PCI_REGION_IO);
 
-		hose->region_count = 3;
+		hose->region_count = r - hose->regions;
 
 		hose->first_busno = first_free_busno;
 		pci_setup_indirect(hose, (int)&pci->cfg_addr,

@@ -313,8 +312,8 @@ void pci_init_board(void)
 #ifdef CONFIG_PCIE2
  {
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
-	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie2_hose;
+	struct pci_region *r = hose->regions;
 
 	int pcie_configured = (io_sel == 0) || (io_sel == 4);
 	int pcie_ep = (host_agent == 0) || (host_agent == 1) ||

@@ -329,27 +328,23 @@ void pci_init_board(void)
 			pci->pme_msg_det = 0xffffffff;
 
 		/* inbound */
-		pci_set_region(hose->regions + 0,
-			 CONFIG_SYS_PCI_MEMORY_BUS,
-			 CONFIG_SYS_PCI_MEMORY_PHYS,
-			 CONFIG_SYS_PCI_MEMORY_SIZE,
-			 PCI_REGION_MEM | PCI_REGION_MEMORY);
+		r += fsl_pci_setup_inbound_windows(r);
 
 		/* outbound memory */
-		pci_set_region(hose->regions + 1,
+		pci_set_region(r++,
 			 CONFIG_SYS_PCIE2_MEM_BASE,
 			 CONFIG_SYS_PCIE2_MEM_PHYS,
 			 CONFIG_SYS_PCIE2_MEM_SIZE,
 			 PCI_REGION_MEM);
 
 		/* outbound io */
-		pci_set_region(hose->regions + 2,
+		pci_set_region(r++,
 			 CONFIG_SYS_PCIE2_IO_BASE,
 			 CONFIG_SYS_PCIE2_IO_PHYS,
 			 CONFIG_SYS_PCIE2_IO_SIZE,
 			 PCI_REGION_IO);
 
-		hose->region_count = 3;
+		hose->region_count = r - hose->regions;
 
 		hose->first_busno = first_free_busno;
 		pci_setup_indirect(hose, (int)&pci->cfg_addr,

@@ -371,9 +366,9 @@ void pci_init_board(void)
 #ifdef CONFIG_PCI1
  {
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
-	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 	int pci_agent = (host_agent >= 4) && (host_agent <= 6);
+	struct pci_region *r = hose->regions;
 
 	if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
 		printf(" PCI connected to PCI slots as %s" \

@@ -382,27 +377,23 @@ void pci_init_board(void)
 			(uint)pci);
 
 		/* inbound */
-		pci_set_region(hose->regions + 0,
-			 CONFIG_SYS_PCI_MEMORY_BUS,
-			 CONFIG_SYS_PCI_MEMORY_PHYS,
-			 CONFIG_SYS_PCI_MEMORY_SIZE,
-			 PCI_REGION_MEM | PCI_REGION_MEMORY);
+		r += fsl_pci_setup_inbound_windows(r);
 
 		/* outbound memory */
-		pci_set_region(hose->regions + 1,
+		pci_set_region(r++,
 			 CONFIG_SYS_PCI1_MEM_BASE,
 			 CONFIG_SYS_PCI1_MEM_PHYS,
 			 CONFIG_SYS_PCI1_MEM_SIZE,
 			 PCI_REGION_MEM);
 
 		/* outbound io */
-		pci_set_region(hose->regions + 2,
+		pci_set_region(r++,
 			 CONFIG_SYS_PCI1_IO_BASE,
 			 CONFIG_SYS_PCI1_IO_PHYS,
 			 CONFIG_SYS_PCI1_IO_SIZE,
 			 PCI_REGION_IO);
 
-		hose->region_count = 3;
+		hose->region_count = r - hose->regions;
 
 		hose->first_busno = first_free_busno;
 		pci_setup_indirect(hose, (int) &pci->cfg_addr,

@@ -422,12 +413,12 @@ void pci_init_board(void)
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+                        struct pci_controller *hose);
+
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-	int node, tmp[2];
-	const char *path;
-
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 			     "timebase-frequency", bd->bi_busfreq / 4, 1);
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,

@@ -442,36 +433,15 @@ ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
 
-
-	node = fdt_path_offset(blob, "/aliases");
-	tmp[0] = 0;
-	if (node >= 0) {
-
 #ifdef CONFIG_PCI1
-		path = fdt_getprop(blob, node, "pci0", NULL);
-		if (path) {
-			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
-
+	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 #endif
 #ifdef CONFIG_PCIE1
-		path = fdt_getprop(blob, node, "pci1", NULL);
-		if (path) {
-			tmp[1] = pcie1_hose.last_busno
-				- pcie1_hose.first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-	}
+	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
 #endif
 #ifdef CONFIG_PCIE2
-		path = fdt_getprop(blob, node, "pci2", NULL);
-		if (path) {
-			tmp[1] = pcie2_hose.last_busno
-				- pcie2_hose.first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
+	ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
 #endif
-	}
 }
 #endif

board/freescale/mpc8641hpcn/mpc8641hpcn.c +17 ~~-36~~

123 lines not on this page · raw message

board/sbc8641d/sbc8641d.c +18 ~~-37~~

124 lines not on this page · raw message

include/configs/MPC8610HPCD.h +0 -5

index 0492274..fe80e5d 100644
@@ -279,11 +279,6 @@
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 /* For RTL8139 */
 #define KSEG1ADDR(x)	({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); })
 #define _IO_BASE		0x00000000

include/configs/MPC8641HPCN.h +0 -5

index ceb2c69..80c8bee 100644
@@ -305,11 +305,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 /* For RTL8139 */
 #define KSEG1ADDR(x)		({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
 #define _IO_BASE		0x00000000

include/configs/sbc8641d.h +0 -5

index 14d1c88..09a9901 100644
@@ -308,11 +308,6 @@
 #define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
 #define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/* 16M */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE     0x80000000
-
 #define CONFIG_SYS_PCI2_MEM_BASE	0xa0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
 #define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */

Signature · 1 line

1.5.5.1

Jon Loeliger

2008-10-24 00:41 UTC #11 lore raw

PATCH 10/10 86xx: Convert all fsl_pci_init users to new APIs

Quoted 8 lines

Converted MPC8610HCPD, MPC8641HPCN, and SBC8641D to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup().
With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards.
Signed-off-by Kumar Gala <[email protected]>
---

ACK.

jdl

Jerry Van Baren

2008-10-23 11:55 UTC #12 lore raw

PATCH 4/10 fdt: Add fdt_sizecell & fdt_addrcell helpers

In reply to Kumar Gala

Quoted 26 lines · Kumar Gala

Add helper functions to return top level #size-cell and #address-cell info

Signed-off-by Kumar Gala <[email protected]>

---
 include/fdt_support.h |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

include/fdt_support.h +11 -0

index ceaadc2..aa9d86b 100644
@@ -28,6 +28,24 @@
 
 #include <fdt.h>
 
+static inline int fdt_addrcell(void *blob) {
+	const u32 *addrcell = fdt_getprop(blob, 0, "#address-cells", NULL);
+
+	if (addrcell)
+		return *addrcell;
+	else
+		return 1;
+}
+
+static inline int fdt_sizecell(void *blob) {
+	const u32 *sizecell = fdt_getprop(blob, 0, "#size-cells", NULL);

include/fdt_support.h line 51

Quoted 10 lines

include/fdt_support.h +7 -0

+
+	if (sizecell)
+		return *sizecell;
+	else
+		return 1;
+}
+
 int fdt_chosen(void *fdt, int force);
 int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
 void do_fixup_by_path(void *fdt, const char *path, const char *prop,

Hi Kumar,

What about collapsing the two above into a common function?

	fdt_addrcell(blob);
becomes
	fdt_get_prop_u32(blob, "/", "#address-cells", 1);
and
	fdt_sizecell(blob);
becomes
	fdt_get_prop_u32(blob, "/", "#size-cells", 1);

WARNING, UNTESTED CODE:
/**
* fdt_get_prop_u32: Find a node and return it's property or a default *
* @fdt: ptr to device tree
* @node: path of node
* @prop: property name
* @defalt: default value if the property isn't found
*
* Convenience function to find a node and return it's property or a
* default value if it doesn't exist.
*/
u32 fdt_get_prop_u32(void *fdt, const char *node, const char *prop,
const u32 default)

{
	const u32 *addrcell = fdt_getprop(fdt, node, prop, NULL);

	if (addrcell)
		return *addrcell;
	else
		return default;
}

Kumar Gala

author

2008-10-23 12:04 UTC #13 lore raw

PATCH 4/10 fdt: Add fdt_sizecell & fdt_addrcell helpers

Quoted 62 lines · Jerry Van Baren

Quoted 31 lines · Kumar Gala
Add helper functions to return top level #size-cell and #address- cell info
Signed-off-by Kumar Gala <[email protected]>
---
include/fdt_support.h | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
include/fdt_support.h +18 -0
index ceaadc2..aa9d86b 100644
@@ -28,6 +28,24 @@
 #include <fdt.h>
+static inline int fdt_addrcell(void *blob) {
+	const u32 *addrcell = fdt_getprop(blob, 0, "#address-cells", NULL);
+
+	if (addrcell)
+		return *addrcell;
+	else
+		return 1;
+}
+
+static inline int fdt_sizecell(void *blob) {
+	const u32 *sizecell = fdt_getprop(blob, 0, "#size-cells", NULL);
+
+	if (sizecell)
+		return *sizecell;
+	else
+		return 1;
+}
+
 int fdt_chosen(void *fdt, int force);
Quoted 3 lines
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
void do_fixup_by_path(void *fdt, const char *path, const char *prop,
Hi Kumar,
What about collapsing the two above into a common function?
	fdt_addrcell(blob);
becomes
	fdt_get_prop_u32(blob, "/", "#address-cells", 1);
and
	fdt_sizecell(blob);
becomes
	fdt_get_prop_u32(blob, "/", "#size-cells", 1);
WARNING, UNTESTED CODE:
/**
* fdt_get_prop_u32: Find a node and return it's property or a default *
* @fdt: ptr to device tree
* @node: path of node
* @prop: property name
* @defalt: default value if the property isn't found
*
* Convenience function to find a node and return it's property or a
* default value if it doesn't exist.
*/
u32 fdt_get_prop_u32(void *fdt, const char *node, const char *prop,
const u32 default)

Quoted 8 lines

{
	const u32 *addrcell = fdt_getprop(fdt, node, prop, NULL);

	if (addrcell)
		return *addrcell;
	else
		return default;
}

I'd prefer we call it fdt_getprop_u32_default(). If you are good with the name I'll change my patchset.

- k

Jerry Van Baren

2008-10-23 12:26 UTC #14 lore raw

PATCH 4/10 fdt: Add fdt_sizecell & fdt_addrcell helpers

Quoted 74 lines · Kumar Gala

Quoted 62 lines · Jerry Van Baren
Quoted 31 lines · Kumar Gala
Add helper functions to return top level #size-cell and #address-cell info
Signed-off-by Kumar Gala <[email protected]>
---
include/fdt_support.h | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
include/fdt_support.h +18 -0
index ceaadc2..aa9d86b 100644
@@ -28,6 +28,24 @@
 #include <fdt.h>
+static inline int fdt_addrcell(void *blob) {
+    const u32 *addrcell = fdt_getprop(blob, 0, "#address-cells", NULL);
+
+    if (addrcell)
+        return *addrcell;
+    else
+        return 1;
+}
+
+static inline int fdt_sizecell(void *blob) {
+    const u32 *sizecell = fdt_getprop(blob, 0, "#size-cells", NULL);
+
+    if (sizecell)
+        return *sizecell;
+    else
+        return 1;
+}
+
 int fdt_chosen(void *fdt, int force);
Quoted 3 lines
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
void do_fixup_by_path(void *fdt, const char *path, const char *prop,
Hi Kumar,
What about collapsing the two above into a common function?
    fdt_addrcell(blob);
becomes
    fdt_get_prop_u32(blob, "/", "#address-cells", 1);
and
    fdt_sizecell(blob);
becomes
    fdt_get_prop_u32(blob, "/", "#size-cells", 1);
WARNING, UNTESTED CODE:
/**
* fdt_get_prop_u32: Find a node and return it's property or a default *
* @fdt: ptr to device tree
* @node: path of node
* @prop: property name
* @defalt: default value if the property isn't found
*
* Convenience function to find a node and return it's property or a
* default value if it doesn't exist.
*/
u32 fdt_get_prop_u32(void *fdt, const char *node, const char *prop,
const u32 default)
Quoted 8 lines
{
    const u32 *addrcell = fdt_getprop(fdt, node, prop, NULL);

    if (addrcell)
        return *addrcell;
    else
        return default;
}

Quoted 4 lines

I'd prefer we call it fdt_getprop_u32_default(). If you are good with the name I'll change my patchset.
- k

That was my second choice. I figured Dennis Richie would call me up and complain the name was too long. ;-)

I'm find with the change.

Acked-by Gerald Van Baren <[email protected]>

Thanks,
gvb

Kumar Gala

author

2008-10-23 12:59 UTC #15 lore raw

PATCH 4/10 fdt: Add fdt_sizecell & fdt_addrcell helpers

Quoted 44 lines

Quoted 32 lines
Quoted 32 lines
Quoted 1 line
Hi Kumar,
What about collapsing the two above into a common function?
   fdt_addrcell(blob);
becomes
fdt_get_prop_u32(blob, "/", "#address-cells", 1);
and
fdt_sizecell(blob);
becomes
fdt_get_prop_u32(blob, "/", "#size-cells", 1);
WARNING, UNTESTED CODE:
/**
* fdt_get_prop_u32: Find a node and return it's property or a default
*
* @fdt: ptr to device tree
* @node: path of node
* @prop: property name
* @defalt: default value if the property isn't found
*
* Convenience function to find a node and return it's property or a
* default value if it doesn't exist.
*/
u32 fdt_get_prop_u32(void *fdt, const char *node, const char *prop,
const u32 default)
{
   const u32 *addrcell = fdt_getprop(fdt, node, prop, NULL);
Quoted 8 lines
Quoted 5 lines
   if (addrcell)
       return *addrcell;
   else
       return default;
}
I'd prefer we call it fdt_getprop_u32_default(). If you are good with the name I'll change my patchset.
- k
That was my second choice. I figured Dennis Richie would call me up and complain the name was too long. ;-)

Quoted 6 lines

I'm find with the change.
Acked-by Gerald Van Baren <[email protected]>
Thanks,
gvb

sent two new patches for you to ack.

- k

Wolfgang Denk

2008-10-24 13:12 UTC #16 lore raw

PATCH 1/10 pci: Allow for PCI addresses to be 64-bit

In reply to Kumar Gala

Dear Kumar Gala,

Quoted 10 lines · In message <[email protected]> you…

PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT.
Signed-off-by Kumar Gala <[email protected]>
---
 drivers/pci/pci.c      |   37 ++++++++++++++------
 drivers/pci/pci_auto.c |   88 ++++++++++++++++++++++++++++-------------------
 include/pci.h          |   40 +++++++++++++---------
 3 files changed, 102 insertions(+), 63 deletions(-)

Acked-by Wolfgang Denk <[email protected]>

Best regards,

Wolfgang Denk

Signature · 4 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Half of the people in the world are below average.

Wolfgang Denk

2008-10-23 08:35 UTC #17 lore raw

cover 85xx/85xx pci cleanup

In reply to Kumar Gala

Dear Kumar Gala,

Quoted 8 lines · In message <[email protected]> you…

This patch series adds the ability to support 64-bit PCI addresses as well as refactors the fsl_pci_init code and cleans up its users.
Finally it adds some help functions that the board code calls to set dma-ranges in device trees.
If the particular maintainers could ack the patches that would be great (Andy, Jon, Jerry).

So who is supposed to apply the patches, then? Me?

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Security is mostly a superstition. It does not  exist  in  nature...
Life is either a daring adventure or nothing."         - Helen Keller

Kumar Gala

author

2008-10-23 11:58 UTC #18 lore raw

cover 85xx/85xx pci cleanup

Quoted 8 lines · Wolfgang Denk

Dear Kumar Gala,
In message <[email protected]
Quoted 5 lines
you wrote:
This patch series adds the ability to support 64-bit PCI addresses as well
as refactors the fsl_pci_init code and cleans up its users.

Quoted 8 lines

Quoted 6 lines
Finally it adds some help functions that the board code calls to set dma-ranges in device trees.
If the particular maintainers could ack the patches that would be great
(Andy, Jon, Jerry).
So who is supposed to apply the patches, then? Me?

yes :)

I practice Andy can apply them to u-boot-85xx if you ack the first patch and Jerry ack's the fdt patches.

- k

Andy Fleming

2008-10-24 22:48 UTC #19 lore raw

cover 85xx/85xx pci cleanup

And thus have I done so. 1-10 applied, thanks

Andy