KVM: VMX: Set IGMT bit in EPT entry
PATCH 1/1 KVM: VMX: Set IGMT bit in EPT entry
(Patch for 2.6.27, based on kvm-updates/2.6.27)
There is a potential issue that, when guest using pagetable without vmexit when EPT enabled, guest would use PAT/PCD/PWT bits to index PAT msr for it's memory, which would be inconsistent with host side and would cause host MCE due to inconsistent cache attribute.
The patch set IGMT bit in EPT entry to ignore guest PAT and use WB as default memory type to protect host (notice that all memory mapped by KVM should be WB).
--- arch/x86/kvm/vmx.c | 3 ++- arch/x86/kvm/vmx.h | 1 + 2 files changed, 3 insertions(+), 1 deletions(-)
arch/x86/kvm/vmx.c +2 -1
@@ -3300,7 +3300,8 @@ static int __init vmx_init(void) bypass_guest_pf =0 ;kvm_mmu_set_base_ptes (VMX_EPT_READABLE_MASK |VMX_EPT_WRITABLE_MASK | -VMX_EPT_DEFAULT_MT <<VMX_EPT_MT_EPTE_SHIFT ); +VMX_EPT_DEFAULT_MT <<VMX_EPT_MT_EPTE_SHIFT | +VMX_EPT_IGMT_BIT );kvm_mmu_set_mask_ptes (0ull ,0ull ,0ull ,0ull ,VMX_EPT_EXECUTABLE_MASK );kvm_enable_tdp ();
arch/x86/kvm/vmx.h +1 -0
@@ -370,6 +370,7 @@ enum vmcs_field {#define VMX_EPT_READABLE_MASK 0x1ull#define VMX_EPT_WRITABLE_MASK 0x2ull#define VMX_EPT_EXECUTABLE_MASK 0x4ull +#define VMX_EPT_IGMT_BIT (1ull << 6)#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
Signature · 1 line
1.5.4.5
Avi Kivity
AppliedQuoted 10 lines · Sheng Yang
(Patch for 2.6.27, based on kvm-updates/2.6.27)
There is a potential issue that, when guest using pagetable without vmexit when EPT enabled, guest would use PAT/PCD/PWT bits to index PAT msr for it's memory, which would be inconsistent with host side and would cause host MCE due to inconsistent cache attribute.
The patch set IGMT bit in EPT entry to ignore guest PAT and use WB as default memory type to protect host (notice that all memory mapped by KVM should be WB).
Applied, thanks.
(I applied it to 2.6.28; in general -stable does not accept patches until they have been merged into mainline)
Signature · 1 line
error compiling committee.c: too many arguments to function
Quoted 10 lines · Sheng Yang
(Patch for 2.6.27, based on kvm-updates/2.6.27)
There is a potential issue that, when guest using pagetable without vmexit when EPT enabled, guest would use PAT/PCD/PWT bits to index PAT msr for it's memory, which would be inconsistent with host side and would cause host MCE due to inconsistent cache attribute.
The patch set IGMT bit in EPT entry to ignore guest PAT and use WB as default memory type to protect host (notice that all memory mapped by KVM should be WB).
So this seems incompatible with hardware passthrough, since that would require being able to map guest memory as something other than WB. Is there a fix for that?
Regards,
Anthony Liguori
Quoted 33 lines
Signed-off-by Sheng Yang <[email protected]>--- arch/x86/kvm/vmx.c | 3 ++- arch/x86/kvm/vmx.h | 1 + 2 files changed, 3 insertions(+), 1 deletions(-)arch/x86/kvm/vmx.c +2
-1@@ -3300,7 +3300,8 @@ static int __init vmx_init(void) bypass_guest_pf =0 ;kvm_mmu_set_base_ptes (VMX_EPT_READABLE_MASK |VMX_EPT_WRITABLE_MASK | -VMX_EPT_DEFAULT_MT <<VMX_EPT_MT_EPTE_SHIFT ); +VMX_EPT_DEFAULT_MT <<VMX_EPT_MT_EPTE_SHIFT | +VMX_EPT_IGMT_BIT );kvm_mmu_set_mask_ptes (0ull ,0ull ,0ull ,0ull ,VMX_EPT_EXECUTABLE_MASK );kvm_enable_tdp ();arch/x86/kvm/vmx.h +1
-0@@ -370,6 +370,7 @@ enum vmcs_field {#define VMX_EPT_READABLE_MASK 0x1ull#define VMX_EPT_WRITABLE_MASK 0x2ull#define VMX_EPT_EXECUTABLE_MASK 0x4ull +#define VMX_EPT_IGMT_BIT (1ull << 6)#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
Quoted 8 lines · On Thursday 06 November 2008 21:47:59 Anthony Liguori wrote:
Quoted 7 lines · Sheng Yang
(Patch for 2.6.27, based on kvm-updates/2.6.27)
There is a potential issue that, when guest using pagetable without vmexit when EPT enabled, guest would use PAT/PCD/PWT bits to index PAT msr for it's memory, which would be inconsistent with host side and would cause host MCE due to inconsistent cache attribute.
Quoted 7 lines
Quoted 3 lines
The patch set IGMT bit in EPT entry to ignore guest PAT and use WB as default memory type to protect host (notice that all memory mapped by KVM should be WB).
So this seems incompatible with hardware passthrough, since that would require being able to map guest memory as something other than WB. Is there a fix for that?
Well, this comment is for 2.6.27/2.6.28 which lacks of EPT memory type support, so it based on the assumption there is no memory type other than WB for EPT... And indeed a new fix is needed for 2.6.28 which lacks of EPT memory type support and got device assignment, but we haven't decided yet how to fix...
It's compatible with hardware passthrough, if kernel got EPT memory type(as current KVM upstream). The EPT memory type derived from guest MTRR, and guest would set MMIO region as UC, then the EPT memory type in EPT entry was UC, and this determined the memory type. Well, still a issue here, guest and host may access same region of memory use different memory type, and we are still in the discussion...
Signature · 2 lines
regards Yang, Sheng
Quoted 36 lines
Regards,
Anthony Liguori
Quoted 31 lines
Signed-off-by Sheng Yang <[email protected]>--- arch/x86/kvm/vmx.c | 3 ++- arch/x86/kvm/vmx.h | 1 + 2 files changed, 3 insertions(+), 1 deletions(-)arch/x86/kvm/vmx.c +2
-1@@ -3300,7 +3300,8 @@ static int __init vmx_init(void) bypass_guest_pf =0 ;kvm_mmu_set_base_ptes (VMX_EPT_READABLE_MASK |VMX_EPT_WRITABLE_MASK | -VMX_EPT_DEFAULT_MT <<VMX_EPT_MT_EPTE_SHIFT ); +VMX_EPT_DEFAULT_MT <<VMX_EPT_MT_EPTE_SHIFT | +VMX_EPT_IGMT_BIT );kvm_mmu_set_mask_ptes (0ull ,0ull ,0ull ,0ull ,VMX_EPT_EXECUTABLE_MASK );kvm_enable_tdp ();arch/x86/kvm/vmx.h +1
-0@@ -370,6 +370,7 @@ enum vmcs_field {#define VMX_EPT_READABLE_MASK 0x1ull#define VMX_EPT_WRITABLE_MASK 0x2ull#define VMX_EPT_EXECUTABLE_MASK 0x4ull +#define VMX_EPT_IGMT_BIT (1ull << 6)#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul