ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs

PATCH Superseded Dave Mitchell 2 participants 2 messages Nov 20, 2008

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Dave Mitchell

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2008-11-20 01:05 UTC #0 lore raw

PATCH 1/1 ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs

Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and L2 cache DCRs from ppc440.h to this new header.

Also converted these DCR defines from lowercase to uppercase and modified referencing modules to use them.

Signed-off-by Dave Mitchell <[email protected]>

---
 board/amcc/luan/luan.c         |   23 ++++++------
 cpu/ppc4xx/start.S             |   41 +++++++++++-----------
 include/asm-ppc/ppc4xx-isram.h |   75 ++++++++++++++++++++++++++++++++++++++++
 include/ppc440.h               |   39 ---------------------
 4 files changed, 108 insertions(+), 70 deletions(-)

board/amcc/luan/luan.c +12 ~~-11~~

index b14b6e1..ae65717 100644
@@ -25,6 +25,7 @@
 #include <command.h>
 #include <ppc4xx.h>
 #include <asm/processor.h>
+#include <asm/ppc4xx-isram.h>
 #include <spd_sdram.h>
 #include "epld.h"

@@ -255,7 +256,7 @@ static int on_off( const char *s )
  ************************************************************************/
 static void l2cache_disable(void)
 {
-	mtdcr( l2_cache_cfg, 0 );
+	mtdcr( L2_CACHE_CFG, 0 );
 }

@@ -265,24 +266,24 @@ static void l2cache_disable(void)
  ************************************************************************/
 static void l2cache_enable(void)	/* see p258 7.4.1 Enabling L2 Cache */
 {
-	mtdcr( l2_cache_cfg, 0x80000000 );	/* enable L2_MODE L2_CFG[L2M] */
+	mtdcr( L2_CACHE_CFG, 0x80000000 );	/* enable L2_MODE L2_CFG[L2M] */
 
-	mtdcr( l2_cache_addr, 0 );		/* set L2_ADDR with all zeros */
+	mtdcr( L2_CACHE_ADDR, 0 );		/* set L2_ADDR with all zeros */
 
-	mtdcr( l2_cache_cmd, 0x80000000 );	/* issue HCLEAR command via L2_CMD */
+	mtdcr( L2_CACHE_CMD, 0x80000000 );	/* issue HCLEAR command via L2_CMD */
 
-	while (!(mfdcr( l2_cache_stat ) & 0x80000000 ))  ;; /* poll L2_SR for completion */
+	while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 ))  ;; /* poll L2_SR for completion */
 
-	mtdcr( l2_cache_cmd, 0x10000000 );	/* clear cache errors L2_CMD[CCP] */
+	mtdcr( L2_CACHE_CMD, 0x10000000 );	/* clear cache errors L2_CMD[CCP] */
 
-	mtdcr( l2_cache_cmd, 0x08000000 );	/* clear tag errors L2_CMD[CTE] */
+	mtdcr( L2_CACHE_CMD, 0x08000000 );	/* clear tag errors L2_CMD[CTE] */
 
-	mtdcr( l2_cache_snp0, 0 );		/* snoop registers */
-	mtdcr( l2_cache_snp1, 0 );
+	mtdcr( L2_CACHE_SNP0, 0 );		/* snoop registers */
+	mtdcr( L2_CACHE_SNP1, 0 );
 
 	__asm__ volatile ("sync");		/* msync */
 
-	mtdcr( l2_cache_cfg, 0xe0000000 );	/* inst and data use L2 */
+	mtdcr( L2_CACHE_CFG, 0xe0000000 );	/* inst and data use L2 */
 
 	__asm__ volatile ("sync");
 }

@@ -294,7 +295,7 @@ static void l2cache_enable(void)	/* see p258 7.4.1 Enabling L2 Cache */
  ************************************************************************/
 static int l2cache_status(void)
 {
-	return  (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
+	return  (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
 }

cpu/ppc4xx/start.S +21 ~~-20~~

92 lines not on this page · raw message

include/asm-ppc/ppc4xx-isram.h new file +75 -0

75 lines not on this page · raw message

include/ppc440.h +0 ~~-39~~

index 7ffc640..3c9b916 100644
@@ -616,45 +616,6 @@
 
 #endif /* 440EP || 440GR || 440EPX || 440GRX */
 
-/*-----------------------------------------------------------------------------
- | L2 Cache
- +----------------------------------------------------------------------------*/
-#if defined (CONFIG_440GX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
-#define L2_CACHE_BASE	0x030
-#define l2_cache_cfg	(L2_CACHE_BASE+0x00)	/* L2 Cache Config	*/
-#define l2_cache_cmd	(L2_CACHE_BASE+0x01)	/* L2 Cache Command	*/
-#define l2_cache_addr	(L2_CACHE_BASE+0x02)	/* L2 Cache Address	*/
-#define l2_cache_data	(L2_CACHE_BASE+0x03)	/* L2 Cache Data	*/
-#define l2_cache_stat	(L2_CACHE_BASE+0x04)	/* L2 Cache Status	*/
-#define l2_cache_cver	(L2_CACHE_BASE+0x05)	/* L2 Cache Revision ID */
-#define l2_cache_snp0	(L2_CACHE_BASE+0x06)	/* L2 Cache Snoop reg 0 */
-#define l2_cache_snp1	(L2_CACHE_BASE+0x07)	/* L2 Cache Snoop reg 1 */
-
-#endif /* CONFIG_440GX */
-
-/*-----------------------------------------------------------------------------
- | Internal SRAM
- +----------------------------------------------------------------------------*/
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define ISRAM0_DCR_BASE 0x380
-#else
-#define ISRAM0_DCR_BASE 0x020
-#endif
-#define isram0_sb0cr	(ISRAM0_DCR_BASE+0x00)	/* SRAM bank config 0*/
-#define isram0_sb1cr	(ISRAM0_DCR_BASE+0x01)	/* SRAM bank config 1*/
-#define isram0_sb2cr	(ISRAM0_DCR_BASE+0x02)	/* SRAM bank config 2*/
-#define isram0_sb3cr	(ISRAM0_DCR_BASE+0x03)	/* SRAM bank config 3*/
-#define isram0_bear	(ISRAM0_DCR_BASE+0x04)	/* SRAM bus error addr reg */
-#define isram0_besr0	(ISRAM0_DCR_BASE+0x05)	/* SRAM bus error status reg 0 */
-#define isram0_besr1	(ISRAM0_DCR_BASE+0x06)	/* SRAM bus error status reg 1 */
-#define isram0_pmeg	(ISRAM0_DCR_BASE+0x07)	/* SRAM power management */
-#define isram0_cid	(ISRAM0_DCR_BASE+0x08)	/* SRAM bus core id reg */
-#define isram0_revid	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
-#define isram0_dpc	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
-
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)

Signature · 1 line

1.6.0.4

Stefan Roese

2008-11-20 08:58 UTC #1 lore raw

PATCH 1/1 ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs

Hi Dave,

Quoted 5 lines · Dave Mitchell

Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and L2 cache DCRs from ppc440.h to this new header.
Also converted these DCR defines from lowercase to uppercase and modified referencing modules to use them.

Thanks, looks good. One nitpicking comment below though:

Quoted 22 lines

+++ b/include/asm-ppc/ppc4xx-isram.h

include/asm-ppc/ppc4xx-isram.h new file +20 -0

@@ -0,0 +1,75 @@
+
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */

include/asm-ppc/ppc4xx-isram.h

Quoted 10 lines

include/asm-ppc/ppc4xx-isram.h new file +8 -2

+
+#ifndef _PPC4xx_ISRAM_H_
+#define _PPC4xx_ISRAM_H_
+
+/*------------------------------------------------------------------------
-----
+ | Internal SRAM 
+
+--------------------------------------------------------------------------
--*/

I know that this comment style has been used in the "old" header bit please use the recommended multiline comment style now:

/*
* Comment
*/

Please fix and resubmit. Thanks.

Best regards,
Stefan

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