ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization
PATCH 1/1 ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization
Expanded OCM TLB to allow access to 64K OCM as well as 256K of internal SRAM.
Adjusted internal SRAM initialization to match updated user manual recommendation.
--- board/amcc/canyonlands/init.S | 2 +- cpu/ppc4xx/start.S | 27 ++++++++++++++++++++------- include/configs/canyonlands.h | 2 +- 3 files changed, 22 insertions(+), 9 deletions(-)
board/amcc/canyonlands/init.S +1 -1
@@ -89,7 +89,7 @@ tlbtab: #endif /* TLB-entry for OCM */ - tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CFG_OCM_BASE, SZ_1M, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) /* TLB-entry for Local Configuration registers => peripherals */ tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
cpu/ppc4xx/start.S +20 -7
@@ -678,9 +678,12 @@ _start: /* not all PPC's have internal SRAM usable as L2-cache */ #if defined(CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_460SX) mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + lis r1, 0x0000 + ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ + mtdcr L2_CACHE_CFG,r1 #endif lis r2,0x7fff
@@ -705,8 +708,8 @@ _start: lis r1, 0x8003 ori r1,r1, 0x0980 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#elif defined(CONFIG_440SPE) - lis r1,0x0000 /* BAS = 0000_0000 */ +#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) + lis r1,0x0000 /* BAS = X_0000_0000 */ ori r1,r1,0x0984 /* first 64k */ mtdcr ISRAM0_SB0CR,r1 lis r1,0x0001
@@ -718,10 +721,20 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - lis r1,0x4000 /* BAS = 8000_0000 */ - ori r1,r1,0x4580 /* 16k */ - mtdcr ISRAM0_SB0CR,r1 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + lis r2,0x7fff + ori r2,r2,0xffff + mfdcr r1,ISRAM1_DPC + and r1,r1,r2 /* Disable parity check */ + mtdcr ISRAM1_DPC,r1 + mfdcr r1,ISRAM1_PMEG + and r1,r1,r2 /* Disable pwr mgmt */ + mtdcr ISRAM1_PMEG,r1 + + lis r1,0x0004 /* BAS = 4_0004_0000 */ + ori r1,r1,0x0984 /* 64k */ + mtdcr ISRAM1_SB0CR,r1 +#endif #elif defined(CONFIG_460SX) lis r1,0x0000 /* BAS = 0000_0000 */ ori r1,r1,0x0B84 /* first 128k */
include/configs/canyonlands.h +1 -1
@@ -102,7 +102,7 @@#define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \ (u64)CFG_FLASH_BASE_PHYS_L) -#define CFG_OCM_BASE 0xE3000000/* OCM: 16k */ +#define CFG_OCM_BASE 0xE3000000/* OCM: 64k */ #define CFG_SRAM_BASE 0xE8000000/* SRAM: 256k */ #define CFG_LOCAL_CONF_REGS 0xEF000000
Signature · 1 line
1.6.0.4
PATCH 1/1 ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization
Hi Dave,
Quoted 5 lines · Dave Mitchell
Expanded OCM TLB to allow access to 64K OCM as well as 256K of internal SRAM.
Adjusted internal SRAM initialization to match updated user manual recommendation.
Thanks. I'm having a hard time trying to figure out where the 64k OCM and where the 256k ISRAM are mapped with this patch. Could you please add a short memory map to this patch description, like:
physical address virtual address size
OCM 0x4.0000.0000 e300.0000 64k
ISRAM 0x4.0004.0000 e304.0000 256k
(just an example, probably not correct)
Thanks.
Best regards,
Stefan
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