net: tsec: Fix Marvell 88E1121R phy init
PATCH 1/1 net: tsec: Fix Marvell 88E1121R phy init
This patch tries to ensure that phy interrupt pin won't be asserted after booting. We experienced following issues with current 88E1121R phy init:
Marvell 88E1121R phy can be hardware-configured to share MDC/MDIO and interrupt pins for both ports P0 and P1 (e.g. as configured on socrates board). Port 0 interrupt pin will be shared by both ports in such configuration. After booting Linux and configuring eth0 interface, port 0 phy interrupts are enabled. After rebooting without proper eth0 interface shutdown port 0 phy interrupts remain enabled so any change on port 0 (link status, etc.) cause assertion of the interrupt. Now booting Linux and configuring eth1 interface will cause permanent phy interrupt storm as the registered phy 1 interrupt handler doesn't acknowledge phy 0 interrupts. This of course should be fixed in Linux driver too.
--- drivers/net/tsec.c | 3 +++ include/tsec.h | 4 ++++ 2 files changed, 7 insertions(+), 0 deletions(-)
drivers/net/tsec.c +3 -0
@@ -1196,6 +1196,9 @@ struct phy_info phy_info_M88E1121R = { {MIIM_88E1121_PHY_LED_CTRL , miim_read, &mii_88E1121_set_led}, {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, +/* Disable IRQs and de-assert interrupt */ + {MIIM_88E1121_PHY_IRQ_EN, 0, NULL}, + {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL}, {miim_end,} }, (struct phy_cmd[]){ /* startup */
include/tsec.h +4 -0
@@ -226,6 +226,10 @@#define MIIM_88E1121_PHY_LED_PAGE 3#define MIIM_88E1121_PHY_LED_DEF 0x0030 +/* 88E1121 PHY IRQ Enable/Status Register */ +#define MIIM_88E1121_PHY_IRQ_EN 18 +#define MIIM_88E1121_PHY_IRQ_STATUS 19 +#define MIIM_88E1121_PHY_PAGE 22/* 88E1145 Extended PHY Specific Control Register */
Signature · 1 line
1.5.3.3
PATCH 1/1 net: tsec: Fix Marvell 88E1121R phy init
Quoted 4 lines · Anatolij Gustschin
This patch tries to ensure that phy interrupt pin won't be asserted after booting. We experienced following issues with current 88E1121R phy init:
Quoted 14 lines
Marvell 88E1121R phy can be hardware-configured to share MDC/MDIO and interrupt pins for both ports P0 and P1 (e.g. as configured on socrates board). Port 0 interrupt pin will be shared by both ports in such configuration. After booting Linux and configuring eth0 interface, port 0 phy interrupts are enabled. After rebooting without proper eth0 interface shutdown port 0 phy interrupts remain enabled so any change on port 0 (link status, etc.) cause assertion of the interrupt. Now booting Linux and configuring eth1 interface will cause permanent phy interrupt storm as the registered phy 1 interrupt handler doesn't acknowledge phy 0 interrupts. This of course should be fixed in Linux driver too.
Agreed, and...
Quoted 2 lines
Signed-off-by Anatolij Gustschin <[email protected]>
Ben Warren
AppliedPATCH 1/1 net: tsec: Fix Marvell 88E1121R phy init
Hi Anatolij & Andy,
Quoted 22 lines · Andy Fleming
Quoted 4 lines · Anatolij Gustschin
This patch tries to ensure that phy interrupt pin won't be asserted after booting. We experienced following issues with current 88E1121R phy init:
Quoted 15 lines
Marvell 88E1121R phy can be hardware-configured to share MDC/MDIO and interrupt pins for both ports P0 and P1 (e.g. as configured on socrates board). Port 0 interrupt pin will be shared by both ports in such configuration. After booting Linux and configuring eth0 interface, port 0 phy interrupts are enabled. After rebooting without proper eth0 interface shutdown port 0 phy interrupts remain enabled so any change on port 0 (link status, etc.) cause assertion of the interrupt. Now booting Linux and configuring eth1 interface will cause permanent phy interrupt storm as the registered phy 1 interrupt handler doesn't acknowledge phy 0 interrupts. This of course should be fixed in Linux driver too.
Quoted 8 lines
Agreed, and...
Quoted 2 lines
Signed-off-by Anatolij Gustschin <[email protected]>Acked-by Andy Fleming <[email protected]>
Applied to net repo.
thanks,
Ben