Skip to contentSkip to conversation

85xx: seperate PIXIS virtual from physical address

PATCH New Kumar Gala 3 participants 5 messages Dec 2, 2008

lore
Share & tools
lore

Kumar Gala

author
#0 lore raw

PATCH 1/2 85xx: seperate PIXIS virtual from physical address

Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers.

This allows us to deal with 36-bit phys on these boards in the future.

Signed-off-by Kumar Gala <[email protected]>

---

These require the 'FSL: Moved BR_PHYS_ADDR for localbus to common header' patch

- k

 board/freescale/mpc8536ds/law.c |    2 +-
 board/freescale/mpc8536ds/tlb.c |    2 +-
 board/freescale/mpc8572ds/law.c |    2 +-
 board/freescale/mpc8572ds/tlb.c |    2 +-
 include/configs/MPC8536DS.h     |    3 ++-
 include/configs/MPC8572DS.h     |    3 ++-
 6 files changed, 8 insertions(+), 6 deletions(-)
board/freescale/mpc8536ds/law.c +1 -1
index 0861fa7..caccce4 100644
@@ -37,7 +37,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };
board/freescale/mpc8536ds/tlb.c +1 -1
index c81a959..89d5097 100644
@@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
-	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
+	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
board/freescale/mpc8572ds/law.c +1 -1
index 83eb681..9814479 100644
@@ -35,7 +35,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };
board/freescale/mpc8572ds/tlb.c +1 -1
index 8d1f646..3832e01 100644
@@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
-	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
+	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
include/configs/MPC8536DS.h +2 -1
index fff888a..136fb48 100644
@@ -195,8 +195,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+#define PIXIS_BASE_PHYS	PIXIS_BASE
 
-#define CONFIG_SYS_BR3_PRELIM	(PIXIS_BASE | 0x0801)	/* port size 8bit */
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
 
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
include/configs/MPC8572DS.h +2 -1
index c3693b8..f40be92 100644
@@ -196,8 +196,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+#define PIXIS_BASE_PHYS	PIXIS_BASE
 
-#define CONFIG_SYS_BR3_PRELIM	(PIXIS_BASE | 0x0801)	/* port size 8bit */
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
 
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
Signature · 1 line
1.5.6.5
author
#1 lore raw

PATCH 2/2 85xx: seperate FLASH BASE virtual from physical address

Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash.

This allows us to deal with 36-bit phys on these boards in the future.

Signed-off-by Kumar Gala <[email protected]>

---

These require the 'FSL: Moved BR_PHYS_ADDR for localbus to common header' patch

- k

 board/freescale/mpc8536ds/law.c       |    2 +-
 board/freescale/mpc8536ds/mpc8536ds.c |    2 +-
 board/freescale/mpc8536ds/tlb.c       |    2 +-
 board/freescale/mpc8572ds/law.c       |    2 +-
 board/freescale/mpc8572ds/mpc8572ds.c |    2 +-
 board/freescale/mpc8572ds/tlb.c       |    2 +-
 include/configs/MPC8536DS.h           |    9 +++++----
 include/configs/MPC8572DS.h           |    9 +++++----
 8 files changed, 16 insertions(+), 14 deletions(-)
board/freescale/mpc8536ds/law.c +1 -1
index caccce4..31614d2 100644
@@ -30,7 +30,7 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2),
board/freescale/mpc8536ds/mpc8536ds.c +1 -1
index 6fed4ea..b2c37f0 100644
@@ -445,7 +445,7 @@ int board_early_init_r(void)
 	/* invalidate existing TLB entry for flash + promjet */
 	disable_tlb(flash_esel);
 
-	set_tlb(1, flashbase, flashbase,		/* tlb, epn, rpn */
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
board/freescale/mpc8536ds/tlb.c +1 -1
index 89d5097..f4bab55 100644
@@ -53,7 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
board/freescale/mpc8572ds/law.c +1 -1
index 9814479..02ea0ec 100644
@@ -28,7 +28,7 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
board/freescale/mpc8572ds/mpc8572ds.c +1 -1
index 3a78c98..3e8052f 100644
@@ -368,7 +368,7 @@ int board_early_init_r(void)
 	/* invalidate existing TLB entry for flash + promjet */
 	disable_tlb(flash_esel);
 
-	set_tlb(1, flashbase, flashbase,		/* tlb, epn, rpn */
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
 			0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
board/freescale/mpc8572ds/tlb.c +1 -1
index 3832e01..c8ded15 100644
@@ -58,7 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
include/configs/MPC8536DS.h +5 -4
index 136fb48..acd6823 100644
@@ -167,12 +167,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Local Bus Definitions
  */
 #define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 
-#define CONFIG_SYS_BR0_PRELIM		0xe8001001
-#define CONFIG_SYS_OR0_PRELIM		0xf8000ff7
+#define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	0xf8000ff7
 
-#define CONFIG_SYS_BR1_PRELIM		0xe0001001
-#define CONFIG_SYS_OR1_PRELIM		0xf8000ff7
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
 
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
 #define CONFIG_SYS_FLASH_QUIET_TEST
include/configs/MPC8572DS.h +5 -4
index f40be92..d604bd7 100644
@@ -168,12 +168,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Local Bus Definitions
  */
 #define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 
-#define CONFIG_SYS_BR0_PRELIM		0xe8001001
-#define CONFIG_SYS_OR0_PRELIM		0xf8000ff7
+#define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	0xf8000ff7
 
-#define CONFIG_SYS_BR1_PRELIM		0xe0001001
-#define CONFIG_SYS_OR1_PRELIM		0xf8000ff7
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
 
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
 #define CONFIG_SYS_FLASH_QUIET_TEST
Signature · 1 line
1.5.6.5
#2 lore raw

PATCH 1/2 85xx: seperate PIXIS virtual from physical address

In reply to Kumar Gala
Quoted 7 lines · Kumar Gala

Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers.

This allows us to deal with 36-bit phys on these boards in the future.

Signed-off-by Kumar Gala <[email protected]>

---

Nit:
s/seperate/separate/ here and 2/2.

jdl

author
#3 lore raw

PATCH 1/2 85xx: seperate PIXIS virtual from physical address

Quoted 7 lines · Jon Loeliger
Quoted 6 lines · Kumar Gala

Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers.

This allows us to deal with 36-bit phys on these boards in the future.

Quoted 6 lines
Quoted 2 lines
Signed-off-by Kumar Gala <[email protected]>

---

Nit:
s/seperate/separate/ here and 2/2.

I'll leave it to Andy to fix my lack of spelling ability when he commits these.

- k

#4 lore raw

PATCH 1/2 85xx: seperate PIXIS virtual from physical address

Quoted 14 lines · Kumar Gala
Quoted 11 lines · Jon Loeliger
Quoted 8 lines · Kumar Gala

Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers.

This allows us to deal with 36-bit phys on these boards in the future.

Signed-off-by Kumar Gala <[email protected]>

---

Quoted 5 lines
Quoted 2 lines

Nit:
s/seperate/separate/ here and 2/2.

I'll leave it to Andy to fix my lack of spelling ability when he commits these.

I don't know, maybe we should have public floggings for spelling mistakes ;-)

FYI, I have a very similar patch series coming for all the 86xx platforms. I've got a bunch of other stuff on tap as well; I expect to push everything in the next day or two.

-B