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tg3: Prevent send BD corruption

PATCH Applied Matt Carlson 2 participants 2 messages Apr 20, 2009 – Apr 21, 2009

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Networking Network drivers
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Matt Carlson

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PATCH 4/8 tg3: Prevent send BD corruption

On rare occasions, send BD corruptions can occur. This patch fixes the problem by increasing the L1 entry threshold to 4 milliseconds.

Signed-off-by Matt Carlson <[email protected]>
Signed-off-by Michael Chan <[email protected]>
---
 drivers/net/tg3.c |    7 +++++++
 drivers/net/tg3.h |    2 ++
 2 files changed, 9 insertions(+), 0 deletions(-)
drivers/net/tg3.c +7 -0
index 9b04954..ed7a86d 100644
@@ -6717,6 +6717,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 		tw32(TG3_CPMU_HST_ACC, val);
 	}
 
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
+		val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
+		val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
+		       PCIE_PWR_MGMT_L1_THRESH_4MS;
+		tw32(PCIE_PWR_MGMT_THRESH, val);
+	}
+
 	/* This works around an issue with Athlon chipsets on
 	 * B3 tigon3 silicon.  This bit has no effect on any
 	 * other revision.  But do not set this on PCI Express
drivers/net/tg3.h +2 -0
index afbabf2..f1016cb 100644
@@ -1697,6 +1697,8 @@
 
 #define PCIE_PWR_MGMT_THRESH		0x00007d28
 #define PCIE_PWR_MGMT_L1_THRESH_MSK	 0x0000ff00
+#define PCIE_PWR_MGMT_L1_THRESH_4MS	 0x0000ff00
+#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN	 0x01000000
 
 
 /* OTP bit definitions */
Signature · 1 line
1.6.0.6