tg3 / broadcom: Add PHY_BRCM_CLEAR_RGMII_MODE flag
Subsystems (4)
PATCH 15/20 tg3 / broadcom: Add PHY_BRCM_CLEAR_RGMII_MODE flag
Broadcom 50610M parts changed the default definitions of the RGMII mode shadow register. The 5785 needs the RGMII mode selection bits [4:3] cleared.
The default value of the remaining bits in this register are zero. Rather than unnecessarily burn an extra bit in the dev_flags member in an attempt to enumerate all possible combinations, this patch take a more course grained approach and labels the option as "clear all bits".
Signed-off-by Matt Carlson <[email protected]>
Reviewed-by Michael Chan <[email protected]>
--- drivers/net/phy/broadcom.c | 6 ++++++ drivers/net/tg3.c | 1 + include/linux/brcmphy.h | 1 + 3 files changed, 8 insertions(+), 0 deletions(-)
drivers/net/phy/broadcom.c +6 -0
@@ -105,6 +105,7 @@#define BCM5482_SHD_LEDS1_LED3 (src) ((src & 0xf) << 4)/* LED1 / ~LINKSPD[1] selector */ #define BCM5482_SHD_LEDS1_LED1 (src) ((src & 0xf) << 0) +#define BCM54XX_SHD_RGMII_MODE 0x0b/* 01011: RGMII Mode Selector */ #define BCM5482_SHD_SSD 0x14/* 10100: Secondary SerDes control */ #define BCM5482_SHD_SSD_LEDM 0x0008/* SSD LED Mode enable */ #define BCM5482_SHD_SSD_EN 0x0001/* SSD enable */
@@ -330,6 +331,11 @@ static int bcm54xx_config_init(struct phy_device *phydev)if (err <0 )return err; +if ((BRCM_PHY_MODEL (phydev) ==PHY_ID_BCM50610 || +BRCM_PHY_MODEL (phydev) ==PHY_ID_BCM50610M ) && + (phydev->dev_flags &PHY_BRCM_CLEAR_RGMII_MODE )) +bcm54xx_shadow_write (phydev,BCM54XX_SHD_RGMII_MODE ,0 ); +bcm54xx_phydsp_config (phydev);return 0 ;
drivers/net/tg3.c +1 -0
@@ -1100,6 +1100,7 @@ static int tg3_mdio_init(struct tg3 *tp)break ;case TG3_PHY_ID_BCM50610 :case TG3_PHY_ID_BCM50610M : + phydev->dev_flags |=PHY_BRCM_CLEAR_RGMII_MODE ;if (tp->tg3_flags3 &TG3_FLG3_RGMII_STD_IBND_DISABLE ) phydev->dev_flags |=PHY_BRCM_STD_IBND_DISABLE ;if (tp->tg3_flags3 &TG3_FLG3_RGMII_EXT_IBND_RX_EN )
include/linux/brcmphy.h +1 -0
@@ -8,4 +8,5 @@#define PHY_BRCM_STD_IBND_DISABLE 0x00000800#define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000 +#define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000#define PHY_BCM_FLAGS_VALID 0x80000000
Signature · 1 line
1.6.4.4