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drm: remove address mask param for drm_pci_alloc()

PATCH Applied Zhenyu Wang 3 participants 6 messages Jan 5, 2010 – Jan 18, 2010

Subsystems (4)
DRM drivers DRM misc Intel i915 Agpgart driver
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Zhenyu Wang

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#0 lore raw

PATCH 1/2 drm: remove address mask param for drm_pci_alloc()

From: Zhenyu Wang <[email protected]>

drm_pci_alloc() has input of address mask for setting pci dma mask on the device, which should be properly setup by drm driver. And leave it as a param for drm_pci_alloc() would cause confusion or mistake would corrupt the correct dma mask setting, as seen on intel hw which set wrong dma mask for hw status page. So remove it from drm_pci_alloc() function.

Signed-off-by Zhenyu Wang <[email protected]>
---
 drivers/gpu/drm/ati_pcigart.c   |   10 ++++++++--
 drivers/gpu/drm/drm_bufs.c      |    4 ++--
 drivers/gpu/drm/drm_pci.c       |    8 +-------
 drivers/gpu/drm/i915/i915_dma.c |    2 +-
 drivers/gpu/drm/i915/i915_gem.c |    2 +-
 include/drm/drmP.h              |    2 +-
 6 files changed, 14 insertions(+), 14 deletions(-)
drivers/gpu/drm/ati_pcigart.c +8 -2
index 628eae3..a1fce68 100644
@@ -39,8 +39,7 @@ static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
 				       struct drm_ati_pcigart_info *gart_info)
 {
 	gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
-						PAGE_SIZE,
-						gart_info->table_mask);
+						PAGE_SIZE);
 	if (gart_info->table_handle == NULL)
 		return -ENOMEM;
 

@@ -112,6 +111,13 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
 	if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
 		DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
 
+		if (pci_set_dma_mask(dev->pdev, gart_info->table_mask)) {
+			DRM_ERROR("fail to set dma mask to 0x%Lx\n",
+				  gart_info->table_mask);
+			ret = 1;
+			goto done;
+		}
+
 		ret = drm_ati_alloc_pcigart_table(dev, gart_info);
 		if (ret) {
 			DRM_ERROR("cannot allocate PCI GART page!\n");
drivers/gpu/drm/drm_bufs.c +2 -2
index 3d09e30..8417cc4 100644
@@ -326,7 +326,7 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
 		 * As we're limiting the address to 2^32-1 (or less),
 		 * casting it down to 32 bits is no problem, but we
 		 * need to point to a 64bit variable first. */
-		dmah = drm_pci_alloc(dev, map->size, map->size, 0xffffffffUL);
+		dmah = drm_pci_alloc(dev, map->size, map->size);
 		if (!dmah) {
 			kfree(map);
 			return -ENOMEM;

@@ -885,7 +885,7 @@ int drm_addbufs_pci(struct drm_device * dev, struct drm_buf_desc * request)
 
 	while (entry->buf_count < count) {
 
-		dmah = drm_pci_alloc(dev, PAGE_SIZE << page_order, 0x1000, 0xfffffffful);
+		dmah = drm_pci_alloc(dev, PAGE_SIZE << page_order, 0x1000);
 
 		if (!dmah) {
 			/* Set count correctly so we free the proper amount. */
drivers/gpu/drm/drm_pci.c +1 -7
index 577094f..e68ebf9 100644
@@ -47,8 +47,7 @@
 /**
  * \brief Allocate a PCI consistent memory block, for DMA.
  */
-drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t align,
-				dma_addr_t maxaddr)
+drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t align)
 {
 	drm_dma_handle_t *dmah;
 #if 1

@@ -63,11 +62,6 @@ drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t ali
 	if (align > size)
 		return NULL;
 
-	if (pci_set_dma_mask(dev->pdev, maxaddr) != 0) {
-		DRM_ERROR("Setting pci dma mask failed\n");
-		return NULL;
-	}
-
 	dmah = kmalloc(sizeof(drm_dma_handle_t), GFP_KERNEL);
 	if (!dmah)
 		return NULL;
drivers/gpu/drm/i915/i915_dma.c +1 -1
index 701bfea..02607ed 100644
@@ -123,7 +123,7 @@ static int i915_init_phys_hws(struct drm_device *dev)
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	/* Program Hardware Status Page */
 	dev_priv->status_page_dmah =
-		drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
+		drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
 
 	if (!dev_priv->status_page_dmah) {
 		DRM_ERROR("Can not allocate hardware status page\n");
drivers/gpu/drm/i915/i915_gem.c +1 -1
index 8c463cf..0d81f88 100644
@@ -4708,7 +4708,7 @@ int i915_gem_init_phys_object(struct drm_device *dev,
 
 	phys_obj->id = id;
 
-	phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
+	phys_obj->handle = drm_pci_alloc(dev, size, 0);
 	if (!phys_obj->handle) {
 		ret = -ENOMEM;
 		goto kfree_obj;
include/drm/drmP.h +1 -1
index 71dafb6..ffac157 100644
@@ -1408,7 +1408,7 @@ extern int drm_ati_pcigart_cleanup(struct drm_device *dev,
 				   struct drm_ati_pcigart_info * gart_info);
 
 extern drm_dma_handle_t *drm_pci_alloc(struct drm_device *dev, size_t size,
-				       size_t align, dma_addr_t maxaddr);
+				       size_t align);
 extern void __drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
 extern void drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
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author
#1 lore raw

PATCH 2/2 drm/i915: enable 36bit physical address for hardware status page

This enables possible 36bit address mask on 965G that use physical address for hw status page.

Signed-off-by Zhenyu Wang <[email protected]>
---
 drivers/char/agp/intel-agp.c    |    6 +++++-
 drivers/gpu/drm/i915/i915_dma.c |    4 ++++
 2 files changed, 9 insertions(+), 1 deletions(-)
drivers/char/agp/intel-agp.c +5 -1
index 30c36ac..3999a5f 100644
@@ -2460,10 +2460,14 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
 				&bridge->mode);
 	}
 
-	if (bridge->driver->mask_memory == intel_i965_mask_memory)
+	if (bridge->driver->mask_memory == intel_i965_mask_memory) {
 		if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
 			dev_err(&intel_private.pcidev->dev,
 				"set gfx device dma mask 36bit failed!\n");
+		else
+			pci_set_consistent_dma_mask(intel_private.pcidev,
+						    DMA_BIT_MASK(36));
+	}
 
 	pci_set_drvdata(pdev, bridge);
 	return agp_add_bridge(bridge);
drivers/gpu/drm/i915/i915_dma.c +4 -0
index 02607ed..750f6c8 100644
@@ -134,6 +134,10 @@ static int i915_init_phys_hws(struct drm_device *dev)
 
 	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 
+	if (IS_I965G(dev))
+		dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
+					     0xf0;
+
 	I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 	DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 	return 0;
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#2 lore raw

Re: [Intel-gfx] [PATCH 2/2] drm/i915: enable 36bit physical address for hardware status page

Quoted 16 lines · Zhenyu Wang

This enables possible 36bit address mask on 965G that use physical address for hw status page.

Signed-off-by Zhenyu Wang <[email protected]>
---
 drivers/char/agp/intel-agp.c    |    6 +++++-
 drivers/gpu/drm/i915/i915_dma.c |    4 ++++
 2 files changed, 9 insertions(+), 1 deletions(-)
drivers/char/agp/intel-agp.c +0 -0
index 30c36ac..3999a5f 100644
@@ -2460,10 +2460,14 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
 				&bridge->mode);
 	}

drivers/char/agp/intel-agp.c static int __devinit agp_intel_probe(struct pci_dev *pdev, · line 2470

Quoted 10 lines
drivers/char/agp/intel-agp.c +5 -1
 
-	if (bridge->driver->mask_memory == intel_i965_mask_memory)
+	if (bridge->driver->mask_memory == intel_i965_mask_memory) {
 		if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
 			dev_err(&intel_private.pcidev->dev,
 				"set gfx device dma mask 36bit failed!\n");
+		else
+			pci_set_consistent_dma_mask(intel_private.pcidev,
+						    DMA_BIT_MASK(36));
+	}

It seems that both pci_set_dma_mask/set_consistent_dma_mask will be called when the DMA mask is set correctly.

Can we use the following format so that it is easy to understand?

   if (!pci_set_dma_mask() && !pci_set_consistent_dma_mask()) {
       success;
   } else
      failure;

Do we need to add the explicit DMA mask for using 32bit DMA mask?

Quoted 8 lines
drivers/char/agp/intel-agp.c +0 -0
 	pci_set_drvdata(pdev, bridge);
 	return agp_add_bridge(bridge);
drivers/gpu/drm/i915/i915_dma.c +0 -0
index 02607ed..750f6c8 100644

drivers/gpu/drm/i915/i915_dma.c static int i915_init_phys_hws(struct drm_device *dev) · line 143

Quoted 10 lines
drivers/gpu/drm/i915/i915_dma.c +4 -0
@@ -134,6 +134,10 @@ static int i915_init_phys_hws(struct drm_device *dev)
 
 	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 
+	if (IS_I965G(dev))
+		dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
+					     0xf0;
+
 	I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 	DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 	return 0;

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author
#3 lore raw

Re: [Intel-gfx] [PATCH 2/2] drm/i915: enable 36bit physical address for hardware status page

Quoted 3 lines · ykzhao

Do we need to add the explicit DMA mask for using 32bit DMA mask?

No, 32bit mask is the default.

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Applied
#4 lore raw

Re: [Intel-gfx] [PATCH 2/2] drm/i915: enable 36bit physical address for hardware status page

In reply to Zhenyu Wang
Quoted 4 lines · Zhenyu Wang

This enables possible 36bit address mask on 965G that use physical address for hw status page.

Signed-off-by Zhenyu Wang <[email protected]>

Applied to for-linus. Thanks!

My understanding is that with the current 2 patches applied, the other swiotlb stuff in intel-agp is not required. Is that right?

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author
#5 lore raw

Re: [Intel-gfx] [PATCH 2/2] drm/i915: enable 36bit physical address for hardware status page

Quoted 10 lines · Eric Anholt
Quoted 4 lines · Zhenyu Wang

This enables possible 36bit address mask on 965G that use physical address for hw status page.

Signed-off-by Zhenyu Wang <[email protected]>

Applied to for-linus. Thanks!

My understanding is that with the current 2 patches applied, the other swiotlb stuff in intel-agp is not required. Is that right?

Yes.

We've already tried to make dma mapping stuff in intel-agp to work with any pci mapping implement, so does swiotlb now although we just pass through it.

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