Add support for i.MX25 SOC and TX25 board

index acc5b7d..7dcedf6 100644
@@ -166,11 +166,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void serial_setbrg (void)
 {
-#ifdef CONFIG_MX31
-	u32 clk = mx31_get_ipg_clk();
-#else
-	u32 clk = imx_get_perclk1();
-#endif
+	u32 clk = imx_get_uartclk();
 
 	if (!gd->baudrate)
 		gd->baudrate = CONFIG_BAUDRATE;

index 5fc75c5..472e8f2 100644
@@ -36,4 +36,6 @@ ulong imx_get_perclk2(void);
 ulong imx_get_perclk3(void);
 ulong imx_get_ahbclk(void);
 
+#define imx_get_uartclk imx_get_perclk1
+
 #endif /* __ASM_ARCH_CLOCK_H */

index 53b9f27..3cc4b35 100644
@@ -25,6 +25,7 @@
 #define __ASM_ARCH_MX31_H
 
 extern u32 mx31_get_ipg_clk(void);
+#define imx_get_uartclk mx31_get_ipg_clk
 extern void mx31_gpio_mux(unsigned long mode);
 
 enum mx31_gpio_direction {

index fb61432..1608e54 100644
@@ -48,6 +48,10 @@
 #define CONFIG_SKIP_RELOCATE_UBOOT
 #endif
 
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NAND_MXC_V1
+#endif
+
 /*
  * Size of malloc() pool
  */

104 lines not on this page · raw message

148 lines not on this page · raw message

index eb0323f..e83420f 100644
@@ -22,27 +22,55 @@
 #include <nand.h>
 #include <linux/err.h>
 #include <asm/io.h>
-#ifdef CONFIG_MX27
 #include <asm/arch/imx-regs.h>
-#endif
 
 #define DRIVER_NAME "mxc_nand"
 
+/*
+ * TODO: Use same register defs here as nand_spl mxc nand driver.
+ */
+/*
+ * Register map and bit definitions for the Freescale NAND Flash Controller
+ * present in various i.MX devices.
+ *
+ * MX31 and MX27 have version 1 which has
+ * 	4 512 byte main buffers and
+ * 	4 16 byte spare buffers
+ * 	to support up to 2K byte pagesize nand.
+ * 	Reading or writing a 2K page requires 4 FDI/FDO cycles.
+ *
+ * MX25 has version 1.1 which has
+ * 	8 512 byte main buffers and
+ * 	8 64 byte spare buffers
+ * 	to support up to 4K byte pagesize nand.
+ * 	Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
+ *      Also some of registers are moved and/or changed meaning as seen below.
+ */
+#if defined(CONFIG_NAND_MXC_V1)
+#define NAND_MXC_NR_BUFS		4
+#define NAND_MXC_SPARE_BUF_SIZE		16
+#define NAND_MXC_REG_OFFSET		0xe00
+#define is_mxc_nfc_11() 		0
+#elif defined(CONFIG_NAND_MXC_V1_1)
+#define NAND_MXC_NR_BUFS		8
+#define NAND_MXC_SPARE_BUF_SIZE		64
+#define NAND_MXC_REG_OFFSET		0x1e00
+#define is_mxc_nfc_11() 		1
+#else
+#error "define CONFIG_NAND_MXC_VXXX to use mtd mxc nand driver"
+#endif
 struct nfc_regs {
-/* NFC RAM BUFFER Main area 0 */
-	uint8_t main_area0[0x200];
-	uint8_t main_area1[0x200];
-	uint8_t main_area2[0x200];
-	uint8_t main_area3[0x200];
-/* SPARE BUFFER Spare area 0 */
-	uint8_t spare_area0[0x10];
-	uint8_t spare_area1[0x10];
-	uint8_t spare_area2[0x10];
-	uint8_t spare_area3[0x10];
-	uint8_t pad[0x5c0];
-/* NFC registers */
+	uint8_t main_area[NAND_MXC_NR_BUFS][0x200];
+	uint8_t spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
+	/*
+	 * reserved size is offset of nfc registers
+	 * minus total main and spare sizes
+	 */
+	uint8_t reserved1[NAND_MXC_REG_OFFSET
+		- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
+#if defined(CONFIG_NAND_MXC_V1)
 	uint16_t nfc_buf_size;
-	uint16_t reserved;
+	uint16_t reserved2;
 	uint16_t nfc_buf_addr;
 	uint16_t nfc_flash_addr;
 	uint16_t nfc_flash_cmd;

@@ -56,6 +84,30 @@ struct nfc_regs {
 	uint16_t nfc_nf_wrprst;
 	uint16_t nfc_config1;
 	uint16_t nfc_config2;
+#elif defined(CONFIG_NAND_MXC_V1_1)
+	uint16_t reserved2[2];
+	uint16_t nfc_buf_addr;
+	uint16_t nfc_flash_addr;
+	uint16_t nfc_flash_cmd;
+	uint16_t nfc_config;
+	uint16_t nfc_ecc_status_result;
+	uint16_t nfc_ecc_status_result2;
+	uint16_t nfc_spare_area_size;
+	uint16_t nfc_wrprot;
+	uint16_t reserved3[2];
+	uint16_t nfc_nf_wrprst;
+	uint16_t nfc_config1;
+	uint16_t nfc_config2;
+	uint16_t reserved4;
+	uint16_t nfc_unlockstart_blkaddr;
+	uint16_t nfc_unlockend_blkaddr;
+	uint16_t nfc_unlockstart_blkaddr1;
+	uint16_t nfc_unlockend_blkaddr1;
+	uint16_t nfc_unlockstart_blkaddr2;
+	uint16_t nfc_unlockend_blkaddr2;
+	uint16_t nfc_unlockstart_blkaddr3;
+	uint16_t nfc_unlockend_blkaddr3;
+#endif
 };
 
 /*

@@ -100,6 +152,11 @@ struct nfc_regs {
  */
 #define NFC_INT            0x8000
 
+#ifdef CONFIG_NAND_MXC_V1_1
+#define NFC_4_8N_ECC	(1 << 0)
+#else
+#define NFC_4_8N_ECC	0
+#endif
 #define NFC_SP_EN           (1 << 2)
 #define NFC_ECC_EN          (1 << 3)
 #define NFC_BIG             (1 << 5)

@@ -119,6 +176,7 @@ struct mxc_nand_host {
 	int			pagesize_2k;
 	int			clk_act;
 	uint16_t		col_addr;
+	unsigned int		page_addr;
 };
 
 static struct mxc_nand_host mxc_host;

@@ -135,17 +193,37 @@ static struct mxc_nand_host *host = &mxc_host;
 #define SPARE_SINGLEBIT_ERROR 0x1
 
 /* OOB placement block for use with hardware ecc generation */
-#ifdef CONFIG_MXC_NAND_HWECC
+#if defined(CONFIG_NAND_MXC_V1)
 static struct nand_ecclayout nand_hw_eccoob = {
 	.eccbytes = 5,
 	.eccpos = {6, 7, 8, 9, 10},
-	.oobfree = {{0, 5}, {11, 5}, }
+	.oobfree = { {0, 5}, {11, 5}, }
 };
-#else
-static struct nand_ecclayout nand_soft_eccoob = {
-	.eccbytes = 6,
-	.eccpos = {6, 7, 8, 9, 10, 11},
-	.oobfree = {{0, 5}, {12, 4}, }
+static struct nand_ecclayout nand_hw_eccoob2k = {
+	.eccbytes = 20,
+	.eccpos = {
+		6, 7, 8, 9, 10,
+		22, 23, 24, 25, 26,
+		38, 39, 40, 41, 42,
+		54, 55, 56, 57, 58,
+	},
+	.oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
+};
+#elif defined(CONFIG_NAND_MXC_V1_1)
+static struct nand_ecclayout nand_hw_eccoob = {
+	.eccbytes = 9,
+	.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
+	.oobfree = { {2, 5} }
+};
+static struct nand_ecclayout nand_hw_eccoob2k = {
+	.eccbytes = 36,
+	.eccpos = {
+		7, 8, 9, 10, 11, 12, 13, 14, 15,
+		23, 24, 25, 26, 27, 28, 29, 30, 31,
+		39, 40, 41, 42, 43, 44, 45, 46, 47,
+		55, 56, 57, 58, 59, 60, 61, 62, 63,
+	},
+	.oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
 };
 #endif
 

@@ -221,7 +299,24 @@ static void send_addr(struct mxc_nand_host *host, uint16_t addr)
 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 			int spare_only)
 {
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
+	if (spare_only)
+		MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
+
+	if (is_mxc_nfc_11()) {
+		int i;
+		/*
+		 *  The controller copies the 64 bytes of spare data from
+		 *  the first 16 bytes of each of the 4 64 byte spare buffers.
+		 *  Copy the contiguous data starting in spare_area[0] to
+		 *  the four spare area buffers.
+		 */
+		for (i = 1; i < 4; i++) {
+			void __iomem *src = &host->regs->spare_area[0][i * 16];
+			void __iomem *dst = &host->regs->spare_area[i][0];
+
+			mxc_nand_memcpy32(dst, src, 16);
+		}
+	}
 
 	writew(buf_id, &host->regs->nfc_buf_addr);
 

@@ -266,6 +361,22 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
 
 	/* Wait for operation to complete */
 	wait_op_done(host, TROP_US_DELAY, spare_only);
+
+	if (is_mxc_nfc_11()) {
+		int i;
+
+		/*
+		 *  The controller copies the 64 bytes of spare data to
+		 *  the first 16 bytes of each of the 4 spare buffers.
+		 *  Make the data contiguous starting in spare_area[0].
+		 */
+		for (i = 1; i < 4; i++) {
+			void __iomem *src = &host->regs->spare_area[i][0];
+			void __iomem *dst = &host->regs->spare_area[0][i * 16];
+
+			mxc_nand_memcpy32(dst, src, 16);
+		}
+	}
 }
 
 /* Request the NANDFC to perform a read of the NAND device ID. */

@@ -293,7 +404,7 @@ static void send_read_id(struct mxc_nand_host *host)
  */
 static uint16_t get_dev_status(struct mxc_nand_host *host)
 {
-	void __iomem *main_buf = host->regs->main_area1;
+	void __iomem *main_buf = host->regs->main_area[1];
 	uint32_t store;
 	uint16_t ret, tmp;
 	/* Issue status request to NAND device */

@@ -342,6 +453,330 @@ static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 	 */
 }
 
+#ifdef CONFIG_NAND_MXC_V1_1
+static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct mxc_nand_host *host = nand_chip->priv;
+	uint16_t tmp = readw(&host->regs->nfc_config1);
+
+	if (on)
+		tmp |= NFC_ECC_EN;
+	else
+		tmp &= ~NFC_ECC_EN;
+	writew(tmp, &host->regs->nfc_config1);
+}
+
+static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
+				      struct nand_chip *chip,
+				      int page, int sndcmd)
+{
+	struct mxc_nand_host *host = chip->priv;
+	uint8_t *buf = chip->oob_poi;
+	int length = mtd->oobsize;
+	int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+	uint8_t *bufpoi = buf;
+	int i, toread;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL0,
+			"%s: Reading OOB area of page %u to oob %p\n",
+			 __FUNCTION__, host->page_addr, buf);
+
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
+	for (i = 0; i < chip->ecc.steps; i++) {
+		toread = min_t(int, length, chip->ecc.prepad);
+		if (toread) {
+			chip->read_buf(mtd, bufpoi, toread);
+			bufpoi += toread;
+			length -= toread;
+		}
+		bufpoi += chip->ecc.bytes;
+		host->col_addr += chip->ecc.bytes;
+		length -= chip->ecc.bytes;
+
+		toread = min_t(int, length, chip->ecc.postpad);
+		if (toread) {
+			chip->read_buf(mtd, bufpoi, toread);
+			bufpoi += toread;
+			length -= toread;
+		}
+	}
+	if (length > 0)
+		chip->read_buf(mtd, bufpoi, length);
+
+	_mxc_nand_enable_hwecc(mtd, 0);
+	chip->cmdfunc(mtd, NAND_CMD_READOOB,
+			mtd->writesize + chip->ecc.prepad, page);
+	bufpoi = buf + chip->ecc.prepad;
+	length = mtd->oobsize - chip->ecc.prepad;
+	for (i = 0; i < chip->ecc.steps; i++) {
+		toread = min_t(int, length, chip->ecc.bytes);
+		chip->read_buf(mtd, bufpoi, toread);
+		bufpoi += eccpitch;
+		length -= eccpitch;
+		host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
+	}
+	_mxc_nand_enable_hwecc(mtd, 1);
+	return 1;
+}
+
+static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
+					   struct nand_chip *chip,
+					   uint8_t *buf,
+					   int page)
+{
+	struct mxc_nand_host *host = chip->priv;
+	int eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
+	uint8_t *oob = chip->oob_poi;
+	int steps, size;
+	int n;
+
+	_mxc_nand_enable_hwecc(mtd, 0);
+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
+
+	for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
+		host->col_addr = n * eccsize;
+		chip->read_buf(mtd, buf, eccsize);
+		buf += eccsize;
+
+		host->col_addr = mtd->writesize + n * eccpitch;
+		if (chip->ecc.prepad) {
+			chip->read_buf(mtd, oob, chip->ecc.prepad);
+			oob += chip->ecc.prepad;
+		}
+
+		chip->read_buf(mtd, oob, eccbytes);
+		oob += eccbytes;
+
+		if (chip->ecc.postpad) {
+			chip->read_buf(mtd, oob, chip->ecc.postpad);
+			oob += chip->ecc.postpad;
+		}
+	}
+
+	size = mtd->oobsize - (oob - chip->oob_poi);
+	if (size)
+		chip->read_buf(mtd, oob, size);
+	_mxc_nand_enable_hwecc(mtd, 0);
+
+	return 0;
+}
+
+static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
+				       struct nand_chip *chip,
+				       uint8_t *buf,
+				       int page)
+{
+	struct mxc_nand_host *host = chip->priv;
+	int n, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
+	      host->page_addr, buf, oob);
+
+	/* first read out the data area and the available portion of OOB */
+	for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
+		int stat;
+
+		host->col_addr = n * eccsize;
+
+		chip->read_buf(mtd, p, eccsize);
+
+		host->col_addr = mtd->writesize + n * eccpitch;
+
+		if (chip->ecc.prepad) {
+			chip->read_buf(mtd, oob, chip->ecc.prepad);
+			oob += chip->ecc.prepad;
+		}
+
+		stat = chip->ecc.correct(mtd, p, oob, NULL);
+
+		if (stat < 0)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+		oob += eccbytes;
+
+		if (chip->ecc.postpad) {
+			chip->read_buf(mtd, oob, chip->ecc.postpad);
+			oob += chip->ecc.postpad;
+		}
+	}
+
+	/* Calculate remaining oob bytes */
+	n = mtd->oobsize - (oob - chip->oob_poi);
+	if (n)
+		chip->read_buf(mtd, oob, n);
+
+	/* Then switch ECC off and read the OOB area to get the ECC code */
+	_mxc_nand_enable_hwecc(mtd, 0);
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr);
+	eccsteps = chip->ecc.steps;
+	oob = chip->oob_poi + chip->ecc.prepad;
+	for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
+		host->col_addr = mtd->writesize +
+				 n * eccpitch +
+				 chip->ecc.prepad;
+		chip->read_buf(mtd, oob, eccbytes);
+		oob += eccbytes + chip->ecc.postpad;
+	}
+	_mxc_nand_enable_hwecc(mtd, 1);
+	return 0;
+}
+
+static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
+				       struct nand_chip *chip, int page)
+{
+	struct mxc_nand_host *host = chip->priv;
+	int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+	int length = mtd->oobsize;
+	int i, len, status, steps = chip->ecc.steps;
+	const uint8_t *bufpoi = chip->oob_poi;
+
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+	for (i = 0; i < steps; i++) {
+		len = min_t(int, length, eccpitch);
+
+		chip->write_buf(mtd, bufpoi, len);
+		bufpoi += len;
+		length -= len;
+		host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
+	}
+	if (length > 0)
+		chip->write_buf(mtd, bufpoi, length);
+
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+	status = chip->waitfunc(mtd, chip);
+	return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
+					     struct nand_chip *chip,
+					     const uint8_t *buf)
+{
+	struct mxc_nand_host *host = chip->priv;
+	int eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
+	uint8_t *oob = chip->oob_poi;
+	int steps, size;
+	int n;
+
+	for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
+		host->col_addr = n * eccsize;
+		chip->write_buf(mtd, buf, eccsize);
+		buf += eccsize;
+
+		host->col_addr = mtd->writesize + n * eccpitch;
+
+		if (chip->ecc.prepad) {
+			chip->write_buf(mtd, oob, chip->ecc.prepad);
+			oob += chip->ecc.prepad;
+		}
+
+		host->col_addr += eccbytes;
+		oob += eccbytes;
+
+		if (chip->ecc.postpad) {
+			chip->write_buf(mtd, oob, chip->ecc.postpad);
+			oob += chip->ecc.postpad;
+		}
+	}
+
+	size = mtd->oobsize - (oob - chip->oob_poi);
+	if (size)
+		chip->write_buf(mtd, oob, size);
+}
+
+static void mxc_nand_write_page_syndrome(struct mtd_info *mtd,
+					 struct nand_chip *chip,
+					 const uint8_t *buf)
+{
+	struct mxc_nand_host *host = chip->priv;
+	int i, n, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
+	int eccsteps = chip->ecc.steps;
+	const uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+
+	chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+
+	for (i = n = 0;
+	     eccsteps;
+	     n++, eccsteps--, i += eccbytes, p += eccsize) {
+		host->col_addr = n * eccsize;
+
+		chip->write_buf(mtd, p, eccsize);
+
+		host->col_addr = mtd->writesize + n * eccpitch;
+
+		if (chip->ecc.prepad) {
+			chip->write_buf(mtd, oob, chip->ecc.prepad);
+			oob += chip->ecc.prepad;
+		}
+
+		chip->write_buf(mtd, oob, eccbytes);
+		oob += eccbytes;
+
+		if (chip->ecc.postpad) {
+			chip->write_buf(mtd, oob, chip->ecc.postpad);
+			oob += chip->ecc.postpad;
+		}
+	}
+
+	/* Calculate remaining oob bytes */
+	i = mtd->oobsize - (oob - chip->oob_poi);
+	if (i)
+		chip->write_buf(mtd, oob, i);
+}
+
+static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
+				 u_char *read_ecc, u_char *calc_ecc)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct mxc_nand_host *host = nand_chip->priv;
+	uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
+	int subpages = mtd->writesize / nand_chip->subpagesize;
+	int pg2blk_shift = nand_chip->phys_erase_shift -
+			   nand_chip->page_shift;
+
+	do {
+		if ((ecc_status & 0xf) > 4) {
+			static int last_bad = -1;
+
+			if (last_bad != host->page_addr >> pg2blk_shift) {
+				last_bad = host->page_addr >> pg2blk_shift;
+				printk(KERN_DEBUG
+				       "MXC_NAND: HWECC uncorrectable ECC error"
+				       " in block %u page %u subpage %d\n",
+				       last_bad, host->page_addr,
+				       mtd->writesize / nand_chip->subpagesize
+					    - subpages);
+			}
+			return -1;
+		}
+		ecc_status >>= 4;
+		subpages--;
+	} while (subpages > 0);
+
+	return 0;
+}
+#else
+#define mxc_nand_read_page_syndrome NULL
+#define mxc_nand_read_page_raw_syndrome NULL
+#define mxc_nand_read_oob_syndrome NULL
+#define mxc_nand_write_page_syndrome NULL
+#define mxc_nand_write_page_raw_syndrome NULL
+#define mxc_nand_write_oob_syndrome NULL
+#define mxc_nfc_11_nand_correct_data NULL
+
 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 				 u_char *read_ecc, u_char *calc_ecc)
 {

@@ -363,6 +798,9 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 
 	return 0;
 }
+#endif
+
+
 
 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 				  u_char *ecc_code)

@@ -378,9 +816,9 @@ static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 	uint8_t ret = 0;
 	uint16_t col;
 	uint16_t __iomem *main_buf =
-		(uint16_t __iomem *)host->regs->main_area0;
+		(uint16_t __iomem *)host->regs->main_area[0];
 	uint16_t __iomem *spare_buf =
-		(uint16_t __iomem *)host->regs->spare_area0;
+		(uint16_t __iomem *)host->regs->spare_area[0];
 	union {
 		uint16_t word;
 		uint8_t bytes[2];

@@ -427,9 +865,10 @@ static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 		col += mtd->writesize;
 
 	if (col < mtd->writesize) {
-		p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
+		p = (uint16_t __iomem *)(host->regs->main_area[0] +
+				(col >> 1));
 	} else {
-		p = (uint16_t __iomem *)(host->regs->spare_area0 +
+		p = (uint16_t __iomem *)(host->regs->spare_area[0] +
 				((col - mtd->writesize) >> 1));
 	}
 

@@ -488,9 +927,9 @@ static void mxc_nand_write_buf(struct mtd_info *mtd,
 		void __iomem *p;
 
 		if (col < mtd->writesize) {
-			p = host->regs->main_area0 + (col & ~3);
+			p = host->regs->main_area[0] + (col & ~3);
 		} else {
-			p = host->regs->spare_area0 -
+			p = host->regs->spare_area[0] -
 						mtd->writesize + (col & ~3);
 		}
 

@@ -558,9 +997,9 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 		void __iomem *p;
 
 		if (col < mtd->writesize) {
-			p = host->regs->main_area0 + (col & ~3);
+			p = host->regs->main_area[0] + (col & ~3);
 		} else {
-			p = host->regs->spare_area0 -
+			p = host->regs->spare_area[0] -
 					mtd->writesize + (col & ~3);
 		}
 

@@ -646,7 +1085,7 @@ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
  * Used by the upper layer to write command to NAND Flash for
  * different operations to be carried out on NAND Flash
  */
-static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
+void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 				int column, int page_addr)
 {
 	struct nand_chip *nand_chip = mtd->priv;

@@ -668,6 +1107,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 		break;
 
 	case NAND_CMD_READ0:
+		host->page_addr = page_addr;
 		host->col_addr = column;
 		host->spare_only = false;
 		break;

@@ -713,7 +1153,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 	case NAND_CMD_PAGEPROG:
 		send_prog_page(host, 0, host->spare_only);
 
-		if (host->pagesize_2k) {
+		if (host->pagesize_2k && !is_mxc_nfc_11()) {
 			/* data in 4 areas datas */
 			send_prog_page(host, 1, host->spare_only);
 			send_prog_page(host, 2, host->spare_only);

@@ -743,30 +1183,12 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 
 	/* Write out page address, if necessary */
 	if (page_addr != -1) {
-		/* paddr_0 - p_addr_7 */
-		send_addr(host, (page_addr & 0xff));
-
-		if (host->pagesize_2k) {
-			send_addr(host, (page_addr >> 8) & 0xFF);
-			if (mtd->size >= 0x10000000) {
-				/* paddr_8 - paddr_15 */
-				send_addr(host, (page_addr >> 8) & 0xff);
-				send_addr(host, (page_addr >> 16) & 0xff);
-			} else {
-				/* paddr_8 - paddr_15 */
-				send_addr(host, (page_addr >> 8) & 0xff);
-			}
-		} else {
-			/* One more address cycle for higher density devices */
-			if (mtd->size >= 0x4000000) {
-				/* paddr_8 - paddr_15 */
-				send_addr(host, (page_addr >> 8) & 0xff);
-				send_addr(host, (page_addr >> 16) & 0xff);
-			} else {
-				/* paddr_8 - paddr_15 */
-				send_addr(host, (page_addr >> 8) & 0xff);
-			}
-		}
+		u32 page_mask = nand_chip->pagemask;
+		do {
+			send_addr(host, page_addr & 0xFF);
+			page_addr >>= 8;
+			page_mask >>= 8;
+		} while (page_mask);
 	}
 
 	/* Command post-processing step */

@@ -782,9 +1204,11 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 			send_cmd(host, NAND_CMD_READSTART);
 			/* read for each AREA */
 			send_read_page(host, 0, host->spare_only);
-			send_read_page(host, 1, host->spare_only);
-			send_read_page(host, 2, host->spare_only);
-			send_read_page(host, 3, host->spare_only);
+			if (!is_mxc_nfc_11()) {
+				send_read_page(host, 1, host->spare_only);
+				send_read_page(host, 2, host->spare_only);
+				send_read_page(host, 3, host->spare_only);
+			}
 		} else {
 			send_read_page(host, 0, host->spare_only);
 		}

@@ -806,13 +1230,30 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 	}
 }
 
+#ifdef CONFIG_NAND_MXC_V1_1
+static void mxc_setup_config1(void)
+{
+	uint16_t tmp;
+
+	tmp = readw(&host->regs->nfc_config1);
+	tmp |= NFC_ONE_CYCLE;
+	tmp |= NFC_4_8N_ECC;
+	writew(tmp, &host->regs->nfc_config1);
+	if (host->pagesize_2k)
+		writew(64/2, &host->regs->nfc_spare_area_size);
+	else
+		writew(16/2, &host->regs->nfc_spare_area_size);
+}
+#else
+#define mxc_setup_config1()
+#endif
+
 int board_nand_init(struct nand_chip *this)
 {
-	struct system_control_regs *sc_regs =
-		(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
 	struct mtd_info *mtd;
 	uint16_t tmp;
 	int err = 0;
+	long nfc_info;
 
 	/* structures must be linked */
 	mtd = &host->mtd;

@@ -839,10 +1280,33 @@ int board_nand_init(struct nand_chip *this)
 	this->ecc.calculate = mxc_nand_calculate_ecc;
 	this->ecc.hwctl = mxc_nand_enable_hwecc;
 	this->ecc.correct = mxc_nand_correct_data;
-	this->ecc.mode = NAND_ECC_HW;
+	if (is_mxc_nfc_11()) {
+		this->ecc.mode = NAND_ECC_HW_SYNDROME;
+		this->ecc.read_page = mxc_nand_read_page_syndrome;
+		this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
+		this->ecc.read_oob = mxc_nand_read_oob_syndrome;
+		this->ecc.write_page = mxc_nand_write_page_syndrome;
+		this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
+		this->ecc.write_oob = mxc_nand_write_oob_syndrome;
+		this->ecc.bytes = 9;
+		this->ecc.prepad = 7;
+	} else {
+		this->ecc.mode = NAND_ECC_HW;
+	}
+
+	host->pagesize_2k = 0;
+	nfc_info = mxc_get_nfc_info();
+	if (IMX_NFC_IS_16BIT(nfc_info))
+		this->options |= NAND_BUSWIDTH_16;
+	if (IMX_NFC_IS_2KPAGE(nfc_info))
+		host->pagesize_2k = 1;
+
+	if (host->pagesize_2k)
+		this->ecc.layout = &nand_hw_eccoob2k;
+	else
+		this->ecc.layout = &nand_hw_eccoob;
+
 	this->ecc.size = 512;
-	this->ecc.bytes = 3;
-	this->ecc.layout = &nand_hw_eccoob;
 	tmp = readw(&host->regs->nfc_config1);
 	tmp |= NFC_ECC_EN;
 	writew(tmp, &host->regs->nfc_config1);

@@ -854,6 +1318,8 @@ int board_nand_init(struct nand_chip *this)
 	writew(tmp, &host->regs->nfc_config1);
 #endif
 
+	mxc_setup_config1();
+
 	/* Reset NAND */
 	this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 

@@ -870,11 +1336,5 @@ int board_nand_init(struct nand_chip *this)
 	/* Unlock Block Command for given address range */
 	writew(0x4, &host->regs->nfc_wrprot);
 
-	/* NAND bus width determines access funtions used by upper layer */
-	if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
-		this->options |= NAND_BUSWIDTH_16;
-
-	host->pagesize_2k = 0;
-
 	return err;
 }

index d36a6da..87180fb 100644
@@ -204,6 +204,7 @@ struct iim_regs {
 	u32 res[0x1F0];
 	u32 iim_bank_area0[0x100];
 };
+
 #endif
 
 #define IMX_IO_BASE		0x10000000

@@ -253,6 +254,18 @@ struct iim_regs {
 #define SDCS1_SEL	(1 << 1)
 #define SDCS0_SEL	(1 << 0)
 
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+
+static inline long mxc_get_nfc_info(void)
+{
+	struct system_control_regs *sc_regs =
+		(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+	return readl(&sc_regs->fmcr);
+}
+#define IMX_NFC_IS_16BIT(fmcr) (fmcr & NF_16BIT_SEL)
+#define IMX_NFC_IS_2KPAGE(fmcr) (!(fmcr & NF_FMS))
+#endif
 
 /* important definition of some bits of WCR */
 #define WCR_WDE 0x04

index ee749ec..f4ad8e7 100644
@@ -152,6 +152,7 @@
  * NAND
  */
 #define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1
 #define CONFIG_MXC_NAND_REGS_BASE	0xd8000000
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		0xd8000000

index da05c55..30cf544 100644
@@ -166,6 +166,11 @@ int print_cpuinfo (void)
 int cpu_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FEC_MXC)
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	/* enable FEC clock */
+	writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
+	writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
 	return fecmxc_initialize(bis);
 #else
 	return 0;

index 19116f2..b5619eb 100644
@@ -151,7 +151,9 @@ static int miiphy_restart_aneg(struct eth_device *dev)
 	 * Wake up from sleep if necessary
 	 * Reset PHY, then delay 300ns
 	 */
+#ifdef CONFIG_MX27
 	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
+#endif
 	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
 			PHY_BMCR_RESET);
 	udelay(1000);

@@ -343,7 +345,8 @@ static int fec_open(struct eth_device *edev)
 	/*
 	 * Enable FEC-Lite controller
 	 */
-	writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
+	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
+		&fec->eth->ecntrl);
 
 	miiphy_wait_aneg(edev);
 	miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);

@@ -415,10 +418,10 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 		 * and do not drop the Preamble.
 		 */
-		writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
+		writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
 				&fec->eth->mii_speed);
 		debug("fec_init: mii_speed %#lx\n",
-				(((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
+				(((imx_get_fecclk() / 1000000) + 2) / 5) << 1);
 	}
 	/*
 	 * Set Opcode/Pause Duration Register

@@ -475,7 +478,7 @@ static void fec_halt(struct eth_device *dev)
 	/*
 	 * issue graceful stop command to the FEC transmitter if necessary
 	 */
-	writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl),
+	writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
 			&fec->eth->x_cntrl);
 
 	debug("eth_halt: wait for stop regs\n");

@@ -483,7 +486,7 @@ static void fec_halt(struct eth_device *dev)
 	 * wait for graceful stop to register
 	 */
 	while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
-		;	/* FIXME ensure time */
+		udelay(1);
 
 	/*
 	 * Disable SmartDMA tasks

@@ -495,7 +498,7 @@ static void fec_halt(struct eth_device *dev)
 	 * Disable the Ethernet Controller
 	 * Note: this will also reset the BD index counter!
 	 */
-	writel(0, &fec->eth->ecntrl);
+	writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
 	fec->rbd_index = 0;
 	fec->tbd_index = 0;
 	debug("eth_halt: done\n");

@@ -554,7 +557,7 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length)
 	 * wait until frame is sent .
 	 */
 	while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
-		/* FIXME: Timeout */
+		udelay(1);
 	}
 	debug("fec_send: status 0x%x index %d\n",
 			readw(&fec->tbd_base[fec->tbd_index].status),

@@ -651,7 +654,6 @@ static int fec_recv(struct eth_device *dev)
 
 static int fec_probe(bd_t *bd)
 {
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 	struct eth_device *edev;
 	struct fec_priv *fec = &gfec;
 	unsigned char ethaddr_str[20];

@@ -659,10 +661,6 @@ static int fec_probe(bd_t *bd)
 	char *tmp = getenv("ethaddr");
 	char *end;
 
-	/* enable FEC clock */
-	writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
-	writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
-
 	/* create and fill edev struct */
 	edev = (struct eth_device *)malloc(sizeof(struct eth_device));
 	if (!edev) {

@@ -681,7 +679,7 @@ static int fec_probe(bd_t *bd)
 	fec->xcv_type = MII100;
 
 	/* Reset chip. */
-	writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl);
+	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
 	while (readl(&fec->eth->ecntrl) & 1)
 		udelay(10);
 

@@ -706,10 +704,10 @@ static int fec_probe(bd_t *bd)
 	 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 	 * and do not drop the Preamble.
 	 */
-	writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
+	writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
 			&fec->eth->mii_speed);
 	debug("fec_init: mii_speed %#lx\n",
-			(((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
+			(((imx_get_fecclk() / 1000000) + 2) / 5) << 1);
 
 	sprintf(edev->name, "FEC_MXC");
 

index 472e8f2..7e9c7aa 100644
@@ -37,5 +37,6 @@ ulong imx_get_perclk3(void);
 ulong imx_get_ahbclk(void);
 
 #define imx_get_uartclk imx_get_perclk1
+#define imx_get_fecclk imx_get_ahbclk
 
 #endif /* __ASM_ARCH_CLOCK_H */

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index 7dcedf6..70c1c1e 100644
@@ -27,15 +27,15 @@
 
 #define __REG(x)     (*((volatile u32 *)(x)))
 
-#ifdef CONFIG_SYS_MX31_UART1
+#if defined(CONFIG_SYS_MX31_UART1) || defined(CONFIG_SYS_MX25_UART1)
 #define UART_PHYS 0x43f90000
-#elif defined(CONFIG_SYS_MX31_UART2)
+#elif defined(CONFIG_SYS_MX31_UART2) || defined(CONFIG_SYS_MX25_UART2)
 #define UART_PHYS 0x43f94000
-#elif defined(CONFIG_SYS_MX31_UART3)
+#elif defined(CONFIG_SYS_MX31_UART3) || defined(CONFIG_SYS_MX25_UART3)
 #define UART_PHYS 0x5000c000
-#elif defined(CONFIG_SYS_MX31_UART4)
+#elif defined(CONFIG_SYS_MX31_UART4) || defined(CONFIG_SYS_MX25_UART4)
 #define UART_PHYS 0x43fb0000
-#elif defined(CONFIG_SYS_MX31_UART5)
+#elif defined(CONFIG_SYS_MX31_UART5) || defined(CONFIG_SYS_MX25_UART5)
 #define UART_PHYS 0x43fb4000
 #elif defined(CONFIG_SYS_MX27_UART1)
 #define UART_PHYS 0x1000a000

new file mode 100644
index 0000000..b0752e7
@@ -0,0 +1,35 @@
+/*
+ *
+ * (c) 2009 Ilya Yanok, Emcraft Systems <[email protected]>
+ *
+ * Modified for mx25 by John Rigby <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+ulong imx_get_perclk(int clk);
+ulong imx_get_ahbclk(void);
+
+#define imx_get_uartclk() imx_get_perclk(15)
+
+
+#endif /* __ASM_ARCH_CLOCK_H */

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index b5619eb..f109485 100644
@@ -347,6 +347,34 @@ static int fec_open(struct eth_device *edev)
 	 */
 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
 		&fec->eth->ecntrl);
+#ifdef CONFIG_MX25
+	udelay(100);
+	/*
+	 * setup the MII gasket for RMII mode
+	 */
+
+	/* disable the gasket */
+	writew(0, &fec->eth->miigsk_enr);
+
+	/* wait for the gasket to be disabled */
+	while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
+		udelay(2);
+
+	/* configure gasket for RMII, 50 MHz, no loopback, and no echo */
+	writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
+
+	/* re-enable the gasket */
+	writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
+
+	/* wait until MII gasket is ready */
+	int max_loops = 10;
+	while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
+		if (--max_loops <= 0) {
+			printf("WAIT for MII Gasket ready timed out\n");
+			break;
+		}
+	}
+#endif
 
 	miiphy_wait_aneg(edev);
 	miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);

@@ -498,7 +526,8 @@ static void fec_halt(struct eth_device *dev)
 	 * Disable the Ethernet Controller
 	 * Note: this will also reset the BD index counter!
 	 */
-	writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
+	writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
+			&fec->eth->ecntrl);
 	fec->rbd_index = 0;
 	fec->tbd_index = 0;
 	debug("eth_halt: done\n");

index 6cb1bfc..5d0d69d 100644
@@ -145,9 +145,17 @@ struct ethernet_regs {
 	uint32_t r_fdxfc;		/* MBAR_ETH + 0x2DC */
 	uint32_t ieee_r_octets_ok;	/* MBAR_ETH + 0x2E0 */
 
-	uint32_t res14[6];		/* MBAR_ETH + 0x2E4-2FC */
-
+	uint32_t res14[7];		/* MBAR_ETH + 0x2E4-2FC */
+
+#ifdef CONFIG_MX25
+	uint16_t miigsk_cfgr;		/* MBAR_ETH + 0x300 */
+	uint16_t res15[3];		/* MBAR_ETH + 0x302-306 */
+	uint16_t miigsk_enr;		/* MBAR_ETH + 0x308 */
+	uint16_t res16[3];		/* MBAR_ETH + 0x30a-30e */
+	uint32_t res17[60];		/* MBAR_ETH + 0x300-3FF */
+#else
 	uint32_t res15[64];		/* MBAR_ETH + 0x300-3FF */
+#endif
 };
 
 #define FEC_IEVENT_HBERR		0x80000000

@@ -196,6 +204,26 @@ struct ethernet_regs {
 #define FEC_ECNTRL_RESET		0x00000001	/* reset the FEC */
 #define FEC_ECNTRL_ETHER_EN		0x00000002	/* enable the FEC */
 
+#ifdef CONFIG_MX25
+/* defines for MIIGSK */
+/* RMII frequency control: 0=50MHz, 1=5MHz */
+#define MIIGSK_CFGR_FRCONT		(1 << 6)
+/* loopback mode */
+#define MIIGSK_CFGR_LBMODE		(1 << 4)
+/* echo mode */
+#define MIIGSK_CFGR_EMODE		(1 << 3)
+/* MII gasket mode field */
+#define MIIGSK_CFGR_IF_MODE_MASK	(3 << 0)
+/* MMI/7-Wire mode */
+#define MIIGSK_CFGR_IF_MODE_MII		(0 << 0)
+/* RMII mode */
+#define MIIGSK_CFGR_IF_MODE_RMII	(1 << 0)
+/* reflects MIIGSK Enable bit (RO) */
+#define MIIGSK_ENR_READY		(1 << 2)
+/* enable MIGSK (set by default) */
+#define MIIGSK_ENR_EN			(1 << 1)
+#endif
+
 /**
  * @brief Descriptor buffer alignment
  *

index b0752e7..c59f588 100644
@@ -30,6 +30,7 @@ ulong imx_get_perclk(int clk);
 ulong imx_get_ahbclk(void);
 
 #define imx_get_uartclk() imx_get_perclk(15)
+#define imx_get_fecclk() (imx_get_ahbclk()/2)
 
 
 #endif /* __ASM_ARCH_CLOCK_H */

index ca631af..a15a950 100644
@@ -298,6 +298,13 @@ void env_relocate_spec (void)
 	tmp_env1 = (env_t *) malloc(CONFIG_ENV_SIZE);
 	tmp_env2 = (env_t *) malloc(CONFIG_ENV_SIZE);
 
+	if ((tmp_env1 == NULL) || (tmp_env2 == NULL)) {
+		puts("Can't allocate buffers for environment\n");
+		free (tmp_env1);
+		free (tmp_env2);
+		return use_default();
+	}
+
 	if (readenv(CONFIG_ENV_OFFSET, (u_char *) tmp_env1))
 		puts("No Valid Environment Area Found\n");
 	if (readenv(CONFIG_ENV_OFFSET_REDUND, (u_char *) tmp_env2))

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178 lines not on this page · raw message