Samsung Clock updates #2

PATCH New Ben Dooks 1 participant 5 messages Jan 18, 2010

Subsystems (3)

Arm (32-bit) Arm sub-architectures Arm Samsung Exynos

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Ben Dooks

author

2010-01-18 08:42 UTC #0 lore raw

Some minor fixes sorted out on the next-samsung-clock2 tree.

Ben Dooks

author

2010-01-18 08:42 UTC #1 lore raw

PATCH 1/1 ARM: S5PC1XX: Register pd0 and hd0 clocks, remove unecessary dummy_enable

The clk_hd0 and clk_pd0 where given a local dummy_enable call due to not being registered with the clock code, which they really should have been. Register these two clocks and remove the clk_dummy_enable as this is done by the default clock registration code.

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/plat-s5pc1xx/clock.c |    9 ++-------
 1 files changed, 2 insertions(+), 7 deletions(-)

arch/arm/plat-s5pc1xx/clock.c +2 -7

index aec0305..387f231 100644
@@ -64,18 +64,12 @@ struct clk clk_54m = {
 	.rate		= 54000000,
 };
 
-static int clk_dummy_enable(struct clk *clk, int enable)
-{
-	return 0;
-}
-
 struct clk clk_hd0 = {
 	.name		= "hclkd0",
 	.id		= -1,
 	.rate		= 0,
 	.parent		= NULL,
 	.ctrlbit	= 0,
-	.enable		= clk_dummy_enable,
 	.ops		= &clk_ops_def_setrate,
 };

@@ -86,7 +80,6 @@ struct clk clk_pd0 = {
 	.parent		= NULL,
 	.ctrlbit	= 0,
 	.ops		= &clk_ops_def_setrate,
-	.enable		= clk_dummy_enable,
 };
 
 static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)

@@ -680,6 +673,8 @@ static struct clk s5pc100_init_clocks[] = {
 static struct clk *clks[] __initdata = {
 	&clk_ext,
 	&clk_epll,
+	&clk_pd0,
+	&clk_hd0,
 	&clk_27m,
 	&clk_48m,
 	&clk_54m,

Signature · 1 line

1.6.0.4

Ben Dooks

author

2010-01-18 08:42 UTC #2 lore raw

PATCH 1/1 ARM: SAMSUNG: Add check to ensure that clksrc_clk does have multiple clock sources

In reply to Ben Dooks

From: Thomas Abraham <[email protected]>

Adds a additional check in s3c_set_clksrc function to ensure that the clksrc_clk does have a choice of multiple clock sources. In addition to this, a check is added to ensure that a parent is assigned to the clksrc_clk in case it does not have a choice of parent clocks.

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/plat-samsung/clock-clksrc.c |   11 ++++++++---
 1 files changed, 8 insertions(+), 3 deletions(-)

arch/arm/plat-samsung/clock-clksrc.c +8 -3

index 33c633a..98c6b88 100644
@@ -129,11 +129,16 @@ void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce)
 {
 	struct clksrc_sources *srcs = clk->sources;
 	u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size);
-	u32 clksrc = 0;
+	u32 clksrc;
 
-	if (clk->reg_src.reg)
-		clksrc = __raw_readl(clk->reg_src.reg);
+	if (!clk->reg_src.reg) {
+		if (!clk->clk.parent)
+			printk(KERN_ERR "%s: no parent clock specified\n",
+				clk->clk.name);
+		return;
+	}
 
+	clksrc = __raw_readl(clk->reg_src.reg);
 	clksrc &= mask;
 	clksrc >>= clk->reg_src.shift;

Signature · 1 line

1.6.0.4

Ben Dooks

author

2010-01-18 08:42 UTC #3 lore raw

PATCH 1/1 ARM: SAMSUNG: Fix clksrc-clk's checks for bad register settings

In reply to Ben Dooks

The WARN_ON() was only checking the first clock in the array, instead of being executed for each clksrc clock being registered.

Since this is an array of clocks, WARN_ON() does not provide a lot of useful information about the problem, so change to using printk(KERN_ERR) to report the problem to the console.

As a note, we still try and register the clock even if these problems are present just in case and to avoid changing the behaviour of the registration process.

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/plat-samsung/clock-clksrc.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

arch/arm/plat-samsung/clock-clksrc.c +4 -2

index 98c6b88..656c70e 100644
@@ -177,9 +177,11 @@ void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
 {
 	int ret;
 
-	WARN_ON(!clksrc->reg_div.reg && !clksrc->reg_src.reg);
-
 	for (; size > 0; size--, clksrc++) {
+		if (!clksrc->reg_div.reg && !clksrc->reg_src.reg)
+			printk(KERN_ERR "%s: clock %s has no registers set\n",
+			       __func__, clksrc->clk.name);
+
 		/* fill in the default functions */
 
 		if (!clksrc->clk.ops) {

Signature · 1 line

1.6.0.4

Ben Dooks

author

2010-01-18 08:42 UTC #4 lore raw

PATCH 1/1 ARM: SAMSUNG: Fix bug in clksrc-clk round_rate call.

In reply to Ben Dooks

The call has been assuming all clksrc-clks' divider size is 4 bits, but this may not be the case anymore. Use the reg_div.size parameter to calculate the maximum value it can take and check against that.

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/plat-samsung/clock-clksrc.c |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

arch/arm/plat-samsung/clock-clksrc.c +5 -3

index 656c70e..ae8b850 100644
@@ -60,7 +60,7 @@ static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate)
 
 	rate = clk_round_rate(clk, rate);
 	div = clk_get_rate(clk->parent) / rate;
-	if (div > 16)
+	if (div > (1 << sclk->reg_div.size))
 		return -EINVAL;
 
 	val = __raw_readl(reg);

@@ -102,7 +102,9 @@ static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent)
 static unsigned long s3c_roundrate_clksrc(struct clk *clk,
 					      unsigned long rate)
 {
+	struct clksrc_clk *sclk = to_clksrc(clk);
 	unsigned long parent_rate = clk_get_rate(clk->parent);
+	int max_div = 1 << sclk->reg_div.size;
 	int div;
 
 	if (rate >= parent_rate)

@@ -114,8 +116,8 @@ static unsigned long s3c_roundrate_clksrc(struct clk *clk,
 
 		if (div == 0)
 			div = 1;
-		if (div > 16)
-			div = 16;
+		if (div > max_div)
+			div = max_div;
 
 		rate = parent_rate / div;
 	}

Signature · 1 line

1.6.0.4