ARM: Add SWP/SWPB emulation for ARMv7 processors (v4)
Subsystems (2)
PATCH 1/1 ARM: Add SWP/SWPB emulation for ARMv7 processors (v4)
The SWP instruction was deprecated in the ARMv6 architecture, superseded by the LDREX/STREX family of instructions for load-linked/store-conditional operations. The ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions are treated as undefined from reset, with the ability to enable them through the System Control Register SW bit.
This patch adds the alternative solution to emulate the SWP and SWPB instructions using LDREX/STREX sequences, and log statistics to /proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also modifies cpu_v7_set_pte_ext to change the mappings to priviliged RO when user RO.
--- Documentation/arm/00-INDEX | 2 Documentation/arm/swp_emulation | 27 ++++ arch/arm/kernel/Makefile | 1 arch/arm/kernel/swp_emulate.c | 256 +++++++++++++++++++++++++++++++++++++++ arch/arm/mm/Kconfig | 20 +++ arch/arm/mm/proc-v7.S | 6 + 6 files changed, 312 insertions(+), 0 deletions(-) create mode 100644 Documentation/arm/swp_emulation create mode 100644 arch/arm/kernel/swp_emulate.c
Documentation/arm/00-INDEX +2 -0
@@ -30,3 +30,5 @@ memory.txt - description of the virtual memory layout nwfpe/ - NWFPE floating point emulator documentation +swp_emulation + - SWP/SWPB emulation handler/logging description
Documentation/arm/swp_emulation new file +27 -0
@@ -0,0 +1,27 @@ +Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE) +--------------------------------------------------------------------- + +ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds +moving to the load-locked/store-conditional instructions LDREX and STREX. + +ARMv7 multiprocessing extensions introduce the ability to disable these +instructions, triggering an undefined instruction exception when executed. +Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB +sequence. If a memory access fault (an abort) occurs, a segmentation fault is +signalled to the triggering process. + +/proc/cpu/swp_emulation holds some statistics/information, including the PID of +the last process to trigger the emulation to be invocated. For example: +--- +Emulated SWP: 12 +Emulated SWPB: 0 +Aborted SWP{B}: 1 +Last process: 314 +--- + +NOTE: when accessing uncached shared regions, LDREX/STREX rely on an external +transaction monitoring block called a global monitor to maintain update +atomicity. If your system does not implement a global monitor, this option can +cause programs that perform SWP operations to uncached memory to deadlock, as +the STREX operation will always fail. +
arch/arm/kernel/Makefile +1 -0
@@ -38,6 +38,7 @@ obj-$(CONFIG_ARM_THUMBEE) += thumbee.o obj-$(CONFIG_KGDB) += kgdb.o obj-$(CONFIG_ARM_UNWIND) += unwind.o obj-$(CONFIG_HAVE_TCM) += tcm.o +obj-$(CONFIG_SWP_EMULATE) += swp_emulate.o obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
arch/arm/kernel/swp_emulate.c new file +256 -0
256 lines not on this page · raw message
arch/arm/mm/Kconfig +20 -0
@@ -626,6 +626,26 @@ config ARM_THUMBEE Say Y here if you have a CPU with the ThumbEE extension and code to make use of it. Say N for code that can run on CPUs without ThumbEE. +config SWP_EMULATE + bool "Emulate SWP/SWPB instructions" + depends on CPU_V7 + default y if SMP + help + ARMv6 architecture deprecates use of the SWP/SWPB instructions. + ARMv7 multiprocessing extensions introduce the ability to disable + these instructions, triggering an undefined instruction exception + when executed. Say Y here to enable software emulation of these + instructions for userspace (not kernel) using LDREX/STREX. + Also creates /proc/cpu/swp_emulation for statistics. + + NOTE: when accessing uncached shared regions, LDREX/STREX rely + on an external transaction monitoring block called a global + monitor to maintain update atomicity. If your system does not + implement a global monitor, this option can cause programs that + perform SWP operations to uncached memory to deadlock. + + If unsure, say Y. + config CPU_BIG_ENDIAN bool "Build big-endian kernel" depends on ARCH_SUPPORTS_BIG_ENDIAN
arch/arm/mm/proc-v7.S +6 -0
@@ -147,8 +147,10 @@ ENTRY(cpu_v7_set_pte_ext) tst r1, #L_PTE_USER orrne r3, r3, #PTE_EXT_AP1 +#ifndef CONFIG_SWP_EMULATE tstne r3, #PTE_EXT_APX bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 +#endif tst r1, #L_PTE_EXEC orreq r3, r3, #PTE_EXT_XN
@@ -275,6 +277,10 @@ __v7_setup: #ifdef CONFIG_CPU_ENDIAN_BE8 orr r6, r6, #1 << 25 @ big-endian page tables #endif +#ifdef CONFIG_SWP_EMULATE + orr r5, r5, #(1 << 10) @ set SW bit in "clear" + bic r6, r6, #(1 << 10) @ clear it in "mmuset" +#endif mrc p15, 0, r0, c1, c0, 0 @ read control register bic r0, r0, r5 @ clear bits them orr r0, r0, r6 @ set them
PATCH 1/1 ARM: Add SWP/SWPB emulation for ARMv7 processors (v4)
Quoted 7 lines · Leif Lindholm
The SWP instruction was deprecated in the ARMv6 architecture, superseded by the LDREX/STREX family of instructions for load-linked/store-conditional operations. The ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions are treated as undefined from reset, with the ability to enable them through the System Control Register SW bit.
Quoted 5 lines
This patch adds the alternative solution to emulate the SWP and SWPB instructions using LDREX/STREX sequences, and log statistics to
/proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also modifiescpu_v7_set_pte_extto change the mappings to priviliged RO when user RO.
Just a thought - could we not add another kuser helper in the vectors page that does this? Your exception trapping code would set regs->ARM_lr to the next instruction following SWP and regs->ARM_pc to the helper.
This way you don't have to worry about handling another exception from inside the kernel or modifying set_pte_ext.
Signature · 1 line
Catalin
PATCH 1/1 ARM: Add SWP/SWPB emulation for ARMv7 processors (v4)
Quoted 14 lines · Catalin Marinas
Quoted 7 lines · Leif Lindholm
The SWP instruction was deprecated in the ARMv6 architecture, superseded by the LDREX/STREX family of instructions for load-linked/store-conditional operations. The ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions are treated as undefined from reset, with the ability to enable them through the System Control Register SW bit.
Quoted 5 lines
This patch adds the alternative solution to emulate the SWP and SWPB instructions using LDREX/STREX sequences, and log statistics to
/proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also modifiescpu_v7_set_pte_extto change the mappings to priviliged RO when user RO.
Quoted 3 lines
Just a thought - could we not add another kuser helper in the vectors page that does this? Your exception trapping code would set
regs->ARM_lrto the next instruction following SWP andregs->ARM_pcto the helper.
That would corrupt LR seen by userspace, wouldn't it? Userspace assumes SWP/SWPB do not change LR.
-- Jamie
PATCH 1/1 ARM: Add SWP/SWPB emulation for ARMv7 processors (v4)
Quoted 15 lines · Jamie Lokier
Quoted 14 lines · Catalin Marinas
Quoted 12 lines · Leif Lindholm
The SWP instruction was deprecated in the ARMv6 architecture, superseded by the LDREX/STREX family of instructions for load-linked/store-conditional operations. The ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions are treated as undefined from reset, with the ability to enable them through the System Control Register SW bit.
This patch adds the alternative solution to emulate the SWP and SWPB instructions using LDREX/STREX sequences, and log statistics to
/proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also modifiescpu_v7_set_pte_extto change the mappings to priviliged RO when user RO.
Quoted 6 lines
Quoted 3 lines
Just a thought - could we not add another kuser helper in the vectors page that does this? Your exception trapping code would set
regs->ARM_lrto the next instruction following SWP andregs->ARM_pcto the helper.That would corrupt LR seen by userspace, wouldn't it? Userspace assumes SWP/SWPB do not change LR.
You are right, so not a good option.
Signature · 1 line
Catalin