arm: mm: support error reporting in L1/L2 caches on QSD
RFC PATCH 7/12 arm: mm: support error reporting in L1/L2 caches on QSD
From: Steve Muckle <[email protected]>
The Scorpion processor supports reporting L2 errors, L1 icache parity errors, and L1 dcache parity errors as imprecise external aborts. If this option is not enabled these errors will go unreported and data corruption will occur.
--- arch/arm/mm/Kconfig | 8 ++++++++ arch/arm/mm/proc-v7.S | 8 ++++++++ 2 files changed, 16 insertions(+), 0 deletions(-)
arch/arm/mm/Kconfig +8 -0
@@ -687,6 +687,14 @@ config CPU_DCACHE_SIZE If your SoC is configured to have a different size, define the value here with proper conditions. +config CPU_CACHE_ERR_REPORT + bool "Report errors in the L1 and L2 caches" + depends on ARCH_MSM_SCORPION + default y + help + Say Y here to have errors in the L1 and L2 caches reported as + imprecise data aborts. + config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
arch/arm/mm/proc-v7.S +8 -0
@@ -246,6 +246,14 @@ __v7_setup: #ifdef CONFIG_ARCH_MSM_SCORPION mov r0, #0x77 mcr p15, 3, r0, c15, c0, 3 @ set L2CR1 + + mrc p15, 0, r0, c1, c0, 1 @ read ACTLR +#ifdef CONFIG_CPU_CACHE_ERR_REPORT + orr r0, r0, #0x37 @ turn on L1/L2 error reporting +#else + bic r0, r0, #0x37 +#endif + mcr p15, 0, r0, c1, c0, 1 @ write ACTLR #endif /* * Memory region attributes with SCTLR.TRE=1
Signature · 1 line
1.6.3.3
RFC PATCH 7/12 arm: mm: support error reporting in L1/L2 caches on QSD
Quoted 40 lines · Daniel Walker
From: Steve Muckle <[email protected]>
The Scorpion processor supports reporting L2 errors, L1 icache parity errors, and L1 dcache parity errors as imprecise external aborts. If this option is not enabled these errors will go unreported and data corruption will occur.
Signed-off-by Steve Muckle <[email protected]>Signed-off-by Daniel Walker <[email protected]>--- arch/arm/mm/Kconfig | 8 ++++++++ arch/arm/mm/proc-v7.S | 8 ++++++++ 2 files changed, 16 insertions(+), 0 deletions(-)arch/arm/mm/Kconfig +8
-0@@ -687,6 +687,14 @@ config CPU_DCACHE_SIZE If your SoC is configured to have a different size, define the value here with proper conditions. +config CPU_CACHE_ERR_REPORT + bool "Report errors in the L1 and L2 caches" + depends on ARCH_MSM_SCORPION + default y + help + Say Y here to have errors in the L1 and L2 caches reported as + imprecise data aborts. + config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLEarch/arm/mm/proc-v7.S +0
-0@@ -246,6 +246,14 @@ __v7_setup: #ifdef CONFIG_ARCH_MSM_SCORPION mov r0, #0x77
arch/arm/mm/proc-v7.S __v7_setup: · line 257
Quoted 10 lines
arch/arm/mm/proc-v7.S +8
-0mcr p15, 3, r0, c15, c0, 3 @ set L2CR1 + + mrc p15, 0, r0, c1, c0, 1 @ read ACTLR +#ifdef CONFIG_CPU_CACHE_ERR_REPORT + orr r0, r0, #0x37 @ turn on L1/L2 error reporting +#else + bic r0, r0, #0x37 +#endif + mcr p15, 0, r0, c1, c0, 1 @ write ACTLR #endif
Does it need to be configurable? Why not always Y?
msm has _way_ too many config options already.
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
RFC PATCH 7/12 arm: mm: support error reporting in L1/L2 caches onQSD
In reply to Daniel WalkerQuoted 7 lines · Daniel Walker
arch/arm/mm/proc-v7.S +1
-0@@ -246,6 +246,14 @@ __v7_setup: #ifdef CONFIG_ARCH_MSM_SCORPION mov r0, #0x77 mcr p15, 3, r0, c15, c0, 3 @ set L2CR1 +
arch/arm/mm/proc-v7.S __v7_setup: · line 259
Quoted 10 lines
arch/arm/mm/proc-v7.S +7
-0+ mrc p15, 0, r0, c1, c0, 1 @ read ACTLR +#ifdef CONFIG_CPU_CACHE_ERR_REPORT + orr r0, r0, #0x37 @ turn on L1/L2 error reporting +#else + bic r0, r0, #0x37 +#endif + mcr p15, 0, r0, c1, c0, 1 @ write ACTLR #endif /* * Memory region attributes with SCTLR.TRE=1
As for the previous patch, maybe it will make sense to move these kind of settings out of the kernel.
Signature · 1 line
Catalin