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S3C2443 clock updates

PATCH New Ben Dooks 1 participant 7 messages Jan 30, 2010

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm Samsung Exynos
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Ben Dooks

author
#0 lore raw

Some clock updates for tidup and to use the common support in clock-clksrc to provide many of the divided or muxed clocks.

In branch next-samsung-s3c2443-clock

Note, untested on real hardware yet

author
#1 lore raw

PATCH 1/6 ARM: S3C2443: Use common clock gate code

Add common clock gate code for each of the S3C2443 clock gate code. Whether to move this elsewhere will be decided later.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/mach-s3c2443/clock.c |   48 +++++++++++-----------------------------
 1 files changed, 13 insertions(+), 35 deletions(-)
arch/arm/mach-s3c2443/clock.c +13 -35
index 3eb8b93..5d061ea 100644
@@ -53,55 +53,33 @@
  * set the correct muxing at initialisation
 */
 
-static int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
+static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
 {
-	unsigned int clocks = clk->ctrlbit;
-	unsigned long clkcon;
-
-	clkcon = __raw_readl(S3C2443_HCLKCON);
+	u32 ctrlbit = clk->ctrlbit;
+	u32 con = __raw_readl(reg);
 
 	if (enable)
-		clkcon |= clocks;
+		con |= ctrlbit;
 	else
-		clkcon &= ~clocks;
-
-	__raw_writel(clkcon, S3C2443_HCLKCON);
+		con &= ~ctrlbit;
 
+	__raw_writel(con, reg);
 	return 0;
 }
 
-static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
+static int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
 {
-	unsigned int clocks = clk->ctrlbit;
-	unsigned long clkcon;
-
-	clkcon = __raw_readl(S3C2443_PCLKCON);
-
-	if (enable)
-		clkcon |= clocks;
-	else
-		clkcon &= ~clocks;
-
-	__raw_writel(clkcon, S3C2443_PCLKCON);
+	return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
+}
 
-	return 0;
+static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
+{
+	return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
 }
 
 static int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
 {
-	unsigned int clocks = clk->ctrlbit;
-	unsigned long clkcon;
-
-	clkcon = __raw_readl(S3C2443_SCLKCON);
-
-	if (enable)
-		clkcon |= clocks;
-	else
-		clkcon &= ~clocks;
-
-	__raw_writel(clkcon, S3C2443_SCLKCON);
-
-	return 0;
+	return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
 }
 
 static unsigned long s3c2443_roundrate_clksrc(struct clk *clk,
Signature · 1 line
1.6.3.3
author
#2 lore raw

PATCH 2/6 ARM: S3C2443: Change to using plat-samsung clksrc-clk implementation

In reply to Ben Dooks

The S3C2443 clock code could easily make use of the clksrc implementation in plat-samsung for many of the clocks. Make the clocks that easily move to clksrc-clk over, update any initialisation and remove the old register definitions from the header file (it is only being used once).

Signed-off-by Ben Dooks <[email protected]>
---
 .../mach-s3c2410/include/mach/regs-s3c2443-clock.h |   29 +--
 arch/arm/mach-s3c2443/Kconfig                      |    1 +
 arch/arm/mach-s3c2443/clock.c                      |  513 +++++---------------
 arch/arm/plat-samsung/clock-clksrc.c               |    2 +-
 4 files changed, 129 insertions(+), 416 deletions(-)
arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +1 -28
index 6026d09..64217ca 100644
@@ -42,12 +42,6 @@
 
 #define S3C2443_PLLCON_OFF		(1<<24)
 
-#define S3C2443_CLKSRC_I2S_EXT		(1<<14)
-#define S3C2443_CLKSRC_I2S_EPLLDIV	(0<<14)
-#define S3C2443_CLKSRC_I2S_EPLLREF	(2<<14)
-#define S3C2443_CLKSRC_I2S_EPLLREF3	(3<<14)
-#define S3C2443_CLKSRC_I2S_MASK		(3<<14)
-
 #define S3C2443_CLKSRC_EPLLREF_XTAL	(2<<7)
 #define S3C2443_CLKSRC_EPLLREF_EXTCLK	(3<<7)
 #define S3C2443_CLKSRC_EPLLREF_MPLLREF	(0<<7)

@@ -81,28 +75,7 @@
 #define S3C2443_CLKDIV0_ARMDIV_12	(13<<9)
 #define S3C2443_CLKDIV0_ARMDIV_16	(15<<9)
 
-/* S3C2443_CLKDIV1 */
-
-#define S3C2443_CLKDIV1_CAMDIV_MASK	(15<<26)
-#define S3C2443_CLKDIV1_CAMDIV_SHIFT	(26)
-
-#define S3C2443_CLKDIV1_HSSPIDIV_MASK	(3<<24)
-#define S3C2443_CLKDIV1_HSSPIDIV_SHIFT	(24)
-
-#define S3C2443_CLKDIV1_DISPDIV_MASK	(0xff<<16)
-#define S3C2443_CLKDIV1_DISPDIV_SHIFT	(16)
-
-#define S3C2443_CLKDIV1_I2SDIV_MASK	(15<<12)
-#define S3C2443_CLKDIV1_I2SDIV_SHIFT	(12)
-
-#define S3C2443_CLKDIV1_UARTDIV_MASK	(15<<8)
-#define S3C2443_CLKDIV1_UARTDIV_SHIFT	(8)
-
-#define S3C2443_CLKDIV1_HSMMCDIV_MASK	(3<<6)
-#define S3C2443_CLKDIV1_HSMMCDIV_SHIFT	(6)
-
-#define S3C2443_CLKDIV1_USBHOSTDIV_MASK	(3<<4)
-#define S3C2443_CLKDIV1_USBHOSTDIV_SHIFT (4)
+/* S3C2443_CLKDIV1 removed, only used in clock.c code */
 
 #define S3C2443_CLKCON_NAND
arch/arm/mach-s3c2443/Kconfig +1 -0
index 4314c44..698140a 100644
@@ -7,6 +7,7 @@ config CPU_S3C2443
 	depends on ARCH_S3C2410
 	select S3C2443_DMA if S3C2410_DMA
 	select CPU_LLSERIAL_S3C2440
+	select SAMSUNG_CLKSRC
 	help
 	  Support for the S3C2443 SoC from the S3C24XX line
arch/arm/mach-s3c2443/clock.c +126 -387

663 lines not on this page · raw message

arch/arm/plat-samsung/clock-clksrc.c +1 -1
index ae8b850..3dfbcfb 100644
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-samsung/clock-clksrc.c
+#/* linux/arch/arm/plat-samsung/clock-clksrc.c
  *
  * Copyright 2008 Simtec Electronics
  *	Ben Dooks <[email protected]>
Signature · 1 line
1.6.3.3
author
#3 lore raw

PATCH 3/6 ARM: S3C2443: Further clksrc-clk conversions

In reply to Ben Dooks

Move more of the core clocks that where left over from the last commit as they are much more core to the system operation. This should allow for easier tracking of any problems.

Signed-off-by Ben Dooks <[email protected]>
---
 .../mach-s3c2410/include/mach/regs-s3c2443-clock.h |    3 -
 arch/arm/mach-s3c2443/clock.c                      |  187 +++++++-------------
 2 files changed, 62 insertions(+), 128 deletions(-)
arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +0 -3
index 64217ca..d87ebe0 100644
@@ -48,11 +48,8 @@
 #define S3C2443_CLKSRC_EPLLREF_MPLLREF2	(1<<7)
 #define S3C2443_CLKSRC_EPLLREF_MASK	(3<<7)
 
-#define S3C2443_CLKSRC_ESYSCLK_EPLL	(1<<6)
-#define S3C2443_CLKSRC_MSYSCLK_MPLL	(1<<4)
 #define S3C2443_CLKSRC_EXTCLK_DIV	(1<<3)
 
-#define S3C2443_CLKDIV0_DVS		(1<<13)
 #define S3C2443_CLKDIV0_HALF_HCLK	(1<<3)
 #define S3C2443_CLKDIV0_HALF_PCLK	(1<<2)
arch/arm/mach-s3c2443/clock.c +62 -125

308 lines not on this page · raw message

Signature · 1 line
1.6.3.3
author
#4 lore raw

PATCH 4/6 ARM: S3C2443: Update notes on MPLLREF clock

In reply to Ben Dooks

Add note on MPLLREF clock source and why it cannot be easily removed.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/mach-s3c2443/clock.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)
arch/arm/mach-s3c2443/clock.c +4 -2
index 1307f69..3fa37aa 100644
@@ -83,10 +83,12 @@ static int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
 	return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
 }
 
-/* s3c2443_roundate_clksrc is close enough to s3c_roundate_clksrc */
-
 /* clock selections */
 
+/* mpllref is a direct descendant of clk_xtal by default, but it is not
+ * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
+ * such directly equating the two source clocks is impossible.
+ */
 static struct clk clk_mpllref = {
 	.name		= "mpllref",
 	.parent		= &clk_xtal,
Signature · 1 line
1.6.3.3
author
#5 lore raw

PATCH 5/6 ARM: S3C2443: Remove #if 0 for clk_mpll

In reply to Ben Dooks

The clk_mpll has long been moved into common clock code, remove the code completely instead of the nasty #if 0 block.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/mach-s3c2443/clock.c |    8 --------
 1 files changed, 0 insertions(+), 8 deletions(-)
arch/arm/mach-s3c2443/clock.c +0 -8
index 3fa37aa..177719c 100644
@@ -95,14 +95,6 @@ static struct clk clk_mpllref = {
 	.id		= -1,
 };
 
-#if 0
-static struct clk clk_mpll = {
-	.name		= "mpll",
-	.parent		= &clk_mpllref,
-	.id		= -1,
-};
-#endif
-
 static struct clk clk_i2s_ext = {
 	.name		= "i2s-ext",
 	.id		= -1,
Signature · 1 line
1.6.3.3
author
#6 lore raw

PATCH 6/6 ARM: S3C2443: Add set_rate and round_rate calls for armdiv clock

In reply to Ben Dooks

Add set_rate and round_rate calls to armdiv for future use with cpu frequency scaling.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/mach-s3c2443/clock.c |   93 ++++++++++++++++++++++++++++++++---------
 1 files changed, 73 insertions(+), 20 deletions(-)
arch/arm/mach-s3c2443/clock.c +73 -20
index 177719c..62cd4ea 100644
@@ -165,10 +165,83 @@ static struct clksrc_clk clk_msysclk = {
  * divider values applied to it to then be fed into armclk.
 */
 
+/* armdiv divisor table */
+
+static unsigned int armdiv[16] = {
+	[S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 1,
+	[S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 2,
+	[S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 3,
+	[S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 4,
+	[S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 6,
+	[S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 8,
+	[S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 12,
+	[S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 16,
+};
+
+static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
+{
+	clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
+
+	return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
+}
+
+static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
+					      unsigned long rate)
+{
+	unsigned long parent = clk_get_rate(clk->parent);
+	unsigned long calc;
+	unsigned best = 256; /* bigger than any value */
+	unsigned div;
+	int ptr;
+
+	for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
+		div = armdiv[ptr];
+		calc = parent / div;
+		if (calc <= rate && div < best)
+			best = div;
+	}
+
+	return parent / best;
+}
+
+static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
+{
+	unsigned long parent = clk_get_rate(clk->parent);
+	unsigned long calc;
+	unsigned div;
+	unsigned best = 256; /* bigger than any value */
+	int ptr;
+	int val = -1;
+
+	for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
+		div = armdiv[ptr];
+		calc = parent / div;
+		if (calc <= rate && div < best) {
+			best = div;
+			val = ptr;
+		}
+	}
+
+	if (val >= 0) {
+		unsigned long clkcon0;
+
+		clkcon0 = __raw_readl(S3C2443_CLKDIV0);
+		clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
+		clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
+		__raw_writel(clkcon0, S3C2443_CLKDIV0);
+	}
+
+	return (val == -1) ? -EINVAL : 0;
+}
+
 static struct clk clk_armdiv = {
 	.name		= "armdiv",
 	.id		= -1,
 	.parent		= &clk_msysclk.clk,
+	.ops		= &(struct clk_ops) {
+		.round_rate = s3c2443_armclk_roundrate,
+		.set_rate = s3c2443_armclk_setrate,
+	},
 };
 
 /* armclk

@@ -619,26 +692,6 @@ static void __init s3c2443_clk_initparents(void)
 		s3c_set_clksrc(init_list[ptr], true);
 }
 
-/* armdiv divisor table */
-
-static unsigned int armdiv[16] = {
-	[S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 1,
-	[S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 2,
-	[S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 3,
-	[S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 4,
-	[S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 6,
-	[S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 8,
-	[S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 12,
-	[S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 16,
-};
-
-static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
-{
-	clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
-
-	return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
-}
-
 static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
 {
 	clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
Signature · 1 line
1.6.3.3