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OMAP3: PM: OMAP3630 support for smartreflex driver

PATCH In review Thara Gopinath 2 participants 5 messages Apr 16, 2010 – Apr 28, 2010

Subsystems (4)
Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP hwmod data
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Thara Gopinath

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#0 lore raw

v3 cover OMAP3: PM: OMAP3630 support for smartreflex driver

This patch series adds support for the updated 45nm smrtrelfex IP supported in OMAP3630 and OMAP4 in the smartreflex driver and adds support to enable smartreflex autocompensation for OMAP3630 using test nvalues.

This patch series is based on the V3 version of Smartreflex and voltage revamp patch series.

This patch series has been tested on OMAP3630 SDP board with CONFIG_OMAP_SMARTREFLEX_TESTING option enabled in the menuconfig.

This patch series has been based on Kevin's PM tree origin/pm-wip-opp branch.

Thara Gopinath (2):
OMAP3: PM: Smartreflex IP update changes for OMAP3630
OMAP3: PM: Adding OMAP3630 support in smartreflex driver

 arch/arm/mach-omap2/board-3630sdp.c        |    2 +
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   86 +++++++++++-
 arch/arm/mach-omap2/smartreflex.c          |  217 ++++++++++++++++++++--------
 arch/arm/mach-omap2/smartreflex.h          |   44 +++++-
 arch/arm/mach-omap2/voltage.c              |   45 ++++++-
 arch/arm/mach-omap2/voltage.h              |   22 +++-
 arch/arm/plat-omap/include/plat/control.h  |    8 +
 7 files changed, 348 insertions(+), 76 deletions(-)
author
#1 lore raw

PATCH v3 1/2 OMAP3: PM: Smartreflex IP update changes for OMAP3630

OMAP3430 uses the 65nm version of the smartreflex IP where as OMAP3630 and OMAP4430 uses the 45nm updated IP.

This patch adds support for the updated smartreflex IP used in OMAP3630 and OMAP4 in the smartreflex driver.

Major changes between the two versions of IP involve:
1. Change in offset position for ERRCONFIG and SENERROR registers
2. Change in bit positions for VP bound interrupt enable and status in ERRCONFIG register.
3. Change in bit positions and width of SENNENABLE and SENPENABLE bits in SRCONFIG registers.
4. Introduction of separate irq registers for MCU bound interrupts.
5. Removal of clockactivity bits in ERRCONFIG and introduction of idlemode and wakeupenable bits in ERRCONFIG.

Signed-off-by Thara Gopinath <[email protected]>
---
 arch/arm/mach-omap2/smartreflex.c |  215 +++++++++++++++++++++++++++----------
 arch/arm/mach-omap2/smartreflex.h |   44 +++++++--
 2 files changed, 194 insertions(+), 65 deletions(-)
arch/arm/mach-omap2/smartreflex.c +157 -58
index 4dccfd1..b81f9f3 100644
@@ -43,6 +43,7 @@ struct omap_sr {
 	int			srid;
 	int			is_sr_enable;
 	int			is_autocomp_active;
+	int			sr_ip_type;
 	u32			clk_length;
 	u32			err_weight;
 	u32			err_minlimit;

@@ -71,6 +72,7 @@ static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
 {
 	struct omap_device *odev = to_omap_device(sr->pdev);
 	u32 reg_val;
+	u32 errconfig_offs, errconfig_mask;
 
 	reg_val = omap_hwmod_readl(odev->hwmods[0], offset);
 	reg_val &= ~mask;

@@ -82,8 +84,15 @@ static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
 	 * value. Now if there is an actual reguest to write to these bits
 	 * they will be set in the nex step.
 	 */
-	if (offset == ERRCONFIG)
-		reg_val &= ~ERRCONFIG_STATUS_MASK;
+	if (sr->sr_ip_type == SR_TYPE_V1) {
+		errconfig_offs = ERRCONFIG_V1;
+		errconfig_mask = ERRCONFIG_STATUS_V1_MASK;
+	} else if (sr->sr_ip_type == SR_TYPE_V2) {
+		errconfig_offs = ERRCONFIG_V2;
+		errconfig_mask = ERRCONFIG_VPBOUNDINTST_V2;
+	}
+	if (offset == errconfig_offs)
+		reg_val &= ~errconfig_mask;
 
 	reg_val |= value;
 

@@ -114,13 +123,19 @@ static struct omap_sr *_sr_lookup(int srid)
 static irqreturn_t sr_omap_isr(int irq, void *data)
 {
 	struct omap_sr *sr_info = (struct omap_sr *)data;
-	u32 status;
-
-	/* Read the status bits */
-	status = sr_read_reg(sr_info, ERRCONFIG);
-
-	/* Clear them by writing back */
-	sr_write_reg(sr_info, ERRCONFIG, status);
+	u32 status = 0;
+
+	if (sr_info->sr_ip_type == SR_TYPE_V1) {
+		/* Read the status bits */
+		status = sr_read_reg(sr_info, ERRCONFIG_V1);
+		/* Clear them by writing back */
+		sr_write_reg(sr_info, ERRCONFIG_V1, status);
+	} else if (sr_info->sr_ip_type == SR_TYPE_V2) {
+		/* Read the status bits */
+		sr_read_reg(sr_info, IRQSTATUS);
+		/* Clear them by writing back */
+		sr_write_reg(sr_info, IRQSTATUS, status);
+	}
 
 	/* Call the class driver notify function if registered*/
 	if (sr_class->class_type == SR_CLASS2 && sr_class->notify)

@@ -243,6 +258,77 @@ static int sr_late_init(struct omap_sr *sr_info)
 	return ret;
 }
 
+static void sr_v1_disable(struct omap_sr *sr)
+{
+	int timeout = 0;
+
+	/* Enable MCUDisableAcknowledge interrupt */
+	sr_modify_reg(sr, ERRCONFIG_V1,
+			ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
+
+	/* SRCONFIG - disable SR */
+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+	/* Disable all other SR interrupts and clear the status */
+	sr_modify_reg(sr, ERRCONFIG_V1,
+			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+			ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
+			(ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
+			ERRCONFIG_MCUBOUNDINTST |
+			ERRCONFIG_VPBOUNDINTST_V1));
+
+	/*
+	 * Wait for SR to be disabled.
+	 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
+	 */
+	omap_test_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
+			ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
+			timeout);
+
+	if (timeout >= SR_DISABLE_TIMEOUT)
+		pr_warning("SR%d disable timedout\n", sr->srid);
+
+	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+	sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
+			ERRCONFIG_MCUDISACKINTST);
+}
+
+static void sr_v2_disable(struct omap_sr *sr)
+{
+	int timeout = 0;
+
+	/* Enable MCUDisableAcknowledge interrupt */
+	sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
+
+	/* SRCONFIG - disable SR */
+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+	/* Disable all other SR interrupts and clear the status */
+	sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+			ERRCONFIG_VPBOUNDINTST_V2);
+	sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
+			IRQENABLE_MCUVALIDINT |
+			IRQENABLE_MCUBOUNDSINT));
+	sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
+			IRQSTATUS_MCVALIDINT |
+			IRQSTATUS_MCBOUNDSINT));
+
+	/*
+	 * Wait for SR to be disabled.
+	 * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
+	 */
+	omap_test_timeout((sr_read_reg(sr, IRQSTATUS) &
+			IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
+			timeout);
+
+	if (timeout >= SR_DISABLE_TIMEOUT)
+		pr_warning("SR%d disable timedout\n", sr->srid);
+
+	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+	sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
+	sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
+}
+
 /* Public Functions */
 
 /**

@@ -259,8 +345,9 @@ static int sr_late_init(struct omap_sr *sr_info)
  */
 void sr_configure_errgen(int srid)
 {
-	u32 sr_config, sr_errconfig;
-	u32 senp_en , senn_en;
+	u32 sr_config, sr_errconfig, errconfig_offs, vpboundint_en;
+	u32 vpboundint_st, senp_en , senn_en;
+	u8 senp_shift, senn_shift;
 	struct omap_sr *sr = _sr_lookup(srid);
 	struct omap_smartreflex_data *pdata = sr->pdev->dev.platform_data;
 

@@ -276,20 +363,36 @@ void sr_configure_errgen(int srid)
 	senp_en = pdata->senp_mod;
 	senn_en = pdata->senn_mod;
 	sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-		SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
-		(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
-		(senp_en << SRCONFIG_SENPENABLE_SHIFT) | SRCONFIG_DELAYCTRL;
+		SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
+	if (sr->sr_ip_type == SR_TYPE_V1) {
+		sr_config |= SRCONFIG_DELAYCTRL;
+		senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+		errconfig_offs = ERRCONFIG_V1;
+		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+	} else if (sr->sr_ip_type == SR_TYPE_V2) {
+		senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+		errconfig_offs = ERRCONFIG_V2;
+		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+	} else {
+		pr_err("Trying to Configure smartreflex module without \
+				specifying the ip\n");
+		return;
+	}
+	sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
 	sr_write_reg(sr, SRCONFIG, sr_config);
 	sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
 		(sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
 		(sr->err_minlimit <<  ERRCONFIG_ERRMINLIMIT_SHIFT);
-	sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
+	sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
 		SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
 		sr_errconfig);
 	/* Enabling the interrupts if the ERROR module is used */
-	sr_modify_reg(sr, ERRCONFIG,
-		(ERRCONFIG_VPBOUNDINTEN),
-		(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
+	sr_modify_reg(sr, errconfig_offs,
+		vpboundint_en, (vpboundint_en | vpboundint_st));
 }
 
 /**

@@ -308,6 +411,7 @@ void sr_configure_minmax(int srid)
 {
 	u32 sr_config, sr_avgwt;
 	u32 senp_en , senn_en;
+	u8 senp_shift, senn_shift;
 	struct omap_sr *sr = _sr_lookup(srid);
 	struct omap_smartreflex_data *pdata = sr->pdev->dev.platform_data;
 

@@ -323,10 +427,21 @@ void sr_configure_minmax(int srid)
 	senp_en = pdata->senp_mod;
 	senn_en = pdata->senn_mod;
 	sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-		SRCONFIG_SENENABLE | (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
-		(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
-		(sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT) |
-		SRCONFIG_DELAYCTRL;
+		SRCONFIG_SENENABLE |
+		(sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
+	if (sr->sr_ip_type == SR_TYPE_V1) {
+		sr_config |= SRCONFIG_DELAYCTRL;
+		senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+	} else if (sr->sr_ip_type == SR_TYPE_V2) {
+		senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+	} else {
+		pr_err("Trying to Configure smartreflex module without \
+				specifying the ip\n");
+		return;
+	}
+	sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
 	sr_write_reg(sr, SRCONFIG, sr_config);
 	sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
 		(sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);

@@ -335,12 +450,21 @@ void sr_configure_minmax(int srid)
 	 * Enabling the interrupts if MINMAXAVG module is used.
 	 * TODO: check if all the interrupts are mandatory
 	 */
-	sr_modify_reg(sr, ERRCONFIG,
-		(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
-		ERRCONFIG_MCUBOUNDINTEN),
-		(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
-		 ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
-		 ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
+	if (sr->sr_ip_type == SR_TYPE_V1) {
+		sr_modify_reg(sr, ERRCONFIG_V1,
+			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+			ERRCONFIG_MCUBOUNDINTEN),
+			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
+			 ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
+			 ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
+	} else if (sr->sr_ip_type == SR_TYPE_V2) {
+		sr_write_reg(sr, IRQSTATUS,
+			IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
+			IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
+		sr_write_reg(sr, IRQENABLE_SET,
+			IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
+			IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
+	}
 }
 
 /**

@@ -418,7 +542,6 @@ void sr_disable(int srid)
 {
 	struct omap_sr *sr = _sr_lookup(srid);
 	struct omap_smartreflex_data *pdata;
-	int timeout = 0;
 
 	if (!sr) {
 		pr_warning("omap_sr struct corresponding to SR%d not found\n",

@@ -434,35 +557,10 @@ void sr_disable(int srid)
 	if (!(sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE))
 		goto disable_clocks;
 
-	/* Enable MCUDisableAcknowledge interrupt */
-	sr_modify_reg(sr, ERRCONFIG,
-			ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
-
-	/* SRCONFIG - disable SR */
-	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
-
-	/* Disable all other SR interrupts and clear the status */
-	sr_modify_reg(sr, ERRCONFIG,
-			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
-			ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN),
-			(ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
-			ERRCONFIG_MCUBOUNDINTST | ERRCONFIG_VPBOUNDINTST));
-
-	/* Wait for SR to be disabled.
-	 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
-	 */
-	omap_test_timeout((sr_read_reg(sr, ERRCONFIG) &
-			ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
-			timeout);
-
-	if (timeout >= SR_DISABLE_TIMEOUT)
-		pr_warning("SR%d disable timedout\n", srid);
-
-	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt
-	 * Also enable VPBOUND interrrupt
-	 */
-	sr_modify_reg(sr, ERRCONFIG, ERRCONFIG_MCUDISACKINTEN,
-			ERRCONFIG_MCUDISACKINTST);
+	if (sr->sr_ip_type == SR_TYPE_V1)
+		sr_v1_disable(sr);
+	else if (sr->sr_ip_type == SR_TYPE_V2)
+		sr_v2_disable(sr);
 
 disable_clocks:
 	pdata = sr->pdev->dev.platform_data;

@@ -619,6 +717,7 @@ static int __devinit omap_smartreflex_probe(struct platform_device *pdev)
 	sr_info->srid = pdev->id;
 	sr_info->is_autocomp_active = 0;
 	sr_info->clk_length = 0;
+	sr_info->sr_ip_type = odev->hwmods[0]->class->rev;
 	if (odev->hwmods[0]->mpu_irqs)
 		sr_info->irq = odev->hwmods[0]->mpu_irqs[0].irq;
 	sr_set_clk_length(sr_info);
arch/arm/mach-omap2/smartreflex.h +37 -7

80 lines not on this page · raw message

Signature · 1 line
1.7.0.rc1.33.g07cf0f
author
#2 lore raw

PATCH v3 2/2 OMAP3: PM: Adding OMAP3630 support in smartreflex driver

This patch adapts smartreflex driver to support OMAP3630 also. Changes involve:
1. Separate hwmod structures for OMAP3630 distinguished from 3430 structures using omap_chip attribute.
2. Introducing new test nvalues for OMAP3630.
3. OMAP3630 specific changes for srconfig err_minlimit field, vpx_config errorgain field and vpx_vlimitto vddmax and vddmin fields.
4. Adding 3630 voltage tables in voltage.c

Signed-off-by Thara Gopinath <[email protected]>
---
 arch/arm/mach-omap2/board-3630sdp.c        |    2 +
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   86 +++++++++++++++++++++++++++-
 arch/arm/mach-omap2/smartreflex.c          |    2 +-
 arch/arm/mach-omap2/voltage.c              |   45 +++++++++++++-
 arch/arm/mach-omap2/voltage.h              |   22 ++++++-
 arch/arm/plat-omap/include/plat/control.h  |    8 +++
 6 files changed, 154 insertions(+), 11 deletions(-)
arch/arm/mach-omap2/board-3630sdp.c +2 -0
index 2fc1d0b..b06f59a 100644
@@ -27,6 +27,7 @@
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 #include "pm.h"
 #include "omap3-opp.h"
+#include "smartreflex-class3.h"
 
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
 

@@ -107,6 +108,7 @@ static void __init omap_sdp_init(void)
 	board_smc91x_init();
 	enable_board_wakeup_source();
 	usb_ehci_init(&ehci_pdata);
+	sr_class3_init();
 }
 
 MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +84 -2

116 lines not on this page · raw message

arch/arm/mach-omap2/smartreflex.c +1 -1
index b81f9f3..a6a29d1 100644
@@ -183,7 +183,7 @@ static void sr_set_regfields(struct omap_sr *sr)
 	 * file or pmic specific data structure. In that case these structure
 	 * fields will have to be populated using the pdata or pmic structure.
 	 */
-	if (cpu_is_omap343x()) {
+	if (cpu_is_omap34xx()) {
 		sr->err_weight = OMAP3430_SR_ERRWEIGHT;
 		sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
 		sr->accum_data = OMAP3430_SR_ACCUMDATA;
arch/arm/mach-omap2/voltage.c +41 -4

77 lines not on this page · raw message

arch/arm/mach-omap2/voltage.h +18 -4
index 473a953..c6445c5 100644
@@ -58,12 +58,26 @@
 #define OMAP3_VP_VSTEPMIN_VSTEPMIN		0x1
 #define OMAP3_VP_VSTEPMAX_SMPSWAITTIMEMAX	0x3C
 #define OMAP3_VP_VSTEPMAX_VSTEPMAX		0x04
-#define OMAP3_VP1_VLIMITTO_VDDMIN		0x14
-#define OMAP3_VP1_VLIMITTO_VDDMAX		0x42
-#define OMAP3_VP2_VLIMITTO_VDDMAX		0x2C
-#define OMAP3_VP2_VLIMITTO_VDDMIN		0x18
 #define OMAP3_VP_VLIMITTO_TIMEOUT_US		0x200
 
+/*
+ * Omap3430 specific VP register values. Maybe these need to come from
+ * board file or PMIC data structure
+ */
+#define OMAP3430_VP1_VLIMITTO_VDDMIN		0x14
+#define OMAP3430_VP1_VLIMITTO_VDDMAX		0x42
+#define OMAP3430_VP2_VLIMITTO_VDDMAX		0x2C
+#define OMAP3430_VP2_VLIMITTO_VDDMIN		0x18
+
+/*
+ * Omap3630 specific VP register values. Maybe these need to come from
+ * board file or PMIC data structure
+ */
+#define OMAP3630_VP1_VLIMITTO_VDDMIN		0x18
+#define OMAP3630_VP1_VLIMITTO_VDDMAX		0x3C
+#define OMAP3630_VP2_VLIMITTO_VDDMIN		0x18
+#define OMAP3630_VP2_VLIMITTO_VDDMAX		0x30
+
 /* TODO OMAP4 VP register values if the same file is used for OMAP4*/
 
 /**
arch/arm/plat-omap/include/plat/control.h +8 -0
index d540ae8..7a94feb 100644
@@ -169,6 +169,14 @@
 #define OMAP343X_CONTROL_SRAMLDO5	(OMAP2_CONTROL_GENERAL + 0x02C0)
 #define OMAP343X_CONTROL_CSI		(OMAP2_CONTROL_GENERAL + 0x02C4)
 
+/* OMAP3630 only CONTROL_GENERAL register offsets */
+#define OMAP3630_CONTROL_FUSE_OPP50_VDD1	(OMAP2_CONTROL_GENERAL + 0x0114)
+#define OMAP3630_CONTROL_FUSE_OPP100_VDD1	(OMAP2_CONTROL_GENERAL + 0x0118)
+#define OMAP3630_CONTROL_FUSE_OPP120_VDD1	(OMAP2_CONTROL_GENERAL + 0x011C)
+#define OMAP3630_CONTROL_FUSE_OPPTM_VDD1	(OMAP2_CONTROL_GENERAL + 0x0120)
+#define OMAP3630_CONTROL_FUSE_OPP50_VDD2	(OMAP2_CONTROL_GENERAL + 0x0128)
+#define OMAP3630_CONTROL_FUSE_OPP100_VDD2	(OMAP2_CONTROL_GENERAL + 0x012C)
+
 /* AM35XX only CONTROL_GENERAL register offsets */
 #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
 #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
Signature · 1 line
1.7.0.rc1.33.g07cf0f
#3 lore raw

Re: [PATCHv3 1/2] OMAP3: PM: Smartreflex IP update changes for OMAP3630

In reply to Thara Gopinath
Quoted 16 lines · Thara Gopinath

OMAP3430 uses the 65nm version of the smartreflex IP where as OMAP3630 and OMAP4430 uses the 45nm updated IP.

This patch adds support for the updated smartreflex IP used in OMAP3630 and OMAP4 in the smartreflex driver.

Major changes between the two versions of IP involve:
1. Change in offset position for ERRCONFIG and SENERROR registers
2. Change in bit positions for VP bound interrupt enable and status in ERRCONFIG register.
3. Change in bit positions and width of SENNENABLE and SENPENABLE bits in SRCONFIG registers.
4. Introduction of separate irq registers for MCU bound interrupts.
5. Removal of clockactivity bits in ERRCONFIG and introduction of idlemode and wakeupenable bits in ERRCONFIG.

Quoted 1 line
Signed-off-by Thara Gopinath <[email protected]>

Looks good. One minor comment for discussion below...

[...]

arch/arm/mach-omap2/smartreflex.c static int __devinit omap_smartreflex_probe(struct platform_device *pdev) · line 720

Quoted 5 lines
arch/arm/mach-omap2/smartreflex.c +1 -0
@@ -619,6 +717,7 @@ static int __devinit omap_smartreflex_probe(struct platform_device *pdev)
 	sr_info->srid = pdev->id;
 	sr_info->is_autocomp_active = 0;
 	sr_info->clk_length = 0;
+	sr_info->sr_ip_type = odev->hwmods[0]->class->rev;

I'm not crazy about drivers having to know the details of hwmod structs. I'd suggest a HWMOD API for getting this revision.

Other ideas?

Kevin

#4 lore raw
In reply to Thara Gopinath
Quoted 5 lines · Thara Gopinath

This patch series adds support for the updated 45nm smrtrelfex IP supported in OMAP3630 and OMAP4 in the smartreflex driver and adds support to enable smartreflex autocompensation for OMAP3630 using test nvalues.

Quoted 8 lines

This patch series is based on the V3 version of Smartreflex and voltage revamp patch series.

This patch series has been tested on OMAP3630 SDP board with CONFIG_OMAP_SMARTREFLEX_TESTING option enabled in the menuconfig.

This patch series has been based on Kevin's PM tree origin/pm-wip-opp branch.

Will get to reviewing this later this week, but in the mean time, added this series to pm-wip-sr branch.

Kevin