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PXA: Add UP2OCR register bit definitions

PATCH New Marek Vasut 2 participants 3 messages Apr 18, 2010 Arm (32-bit)

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Marek Vasut

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#0 lore raw

PATCH 1/2 PXA: Add UP2OCR register bit definitions

This register is used on PXA to control the USB Port2 operation (USB Port2 is the host port).

Signed-off-by Marek Vasut <[email protected]>
---
 arch/arm/include/asm/arch-pxa/pxa-regs.h |   20 ++++++++++++++++----
 1 files changed, 16 insertions(+), 4 deletions(-)
arch/arm/include/asm/arch-pxa/pxa-regs.h +16 -4
index a25d4c5..06711f7 100644
@@ -992,10 +992,6 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UHCHIE		__REG(0x4C000068)
 #define UHCHIT		__REG(0x4C00006C)
 
-#if defined(CONFIG_CPU_MONAHANS)
-#define UP2OCR		__REG(0x40600020)
-#endif
-
 #define UHCHR_FSBIR	(1<<0)
 #define UHCHR_FHR	(1<<1)
 #define UHCHR_CGR	(1<<2)

@@ -1015,6 +1011,22 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UHCHIE_HBAIE	(1<<8)
 #define UHCHIE_RWIE	(1<<7)
 
+#define UP2OCR		__REG(0x40600020)
+
+#define	UP2OCR_HXOE	(1<<17)
+#define	UP2OCR_HXS	(1<<16)
+#define	UP2OCR_IDON	(1<<10)
+#define	UP2OCR_EXSUS	(1<<9)
+#define	UP2OCR_EXSP	(1<<8)
+#define	UP2OCR_DMSTATE	(1<<7)
+#define	UP2OCR_VPM	(1<<6)
+#define	UP2OCR_DPSTATE	(1<<5)
+#define	UP2OCR_DPPUE	(1<<4)
+#define	UP2OCR_DMPDE	(1<<3)
+#define	UP2OCR_DPPDE	(1<<2)
+#define	UP2OCR_CPVPE	(1<<1)
+#define	UP2OCR_CPVEN	(1<<0)
+
 #endif
 
 /*
Signature · 1 line
1.7.0
author
#1 lore raw

PATCH 2/2 PXA: Add missing MDREFR bits

Signed-off-by Marek Vasut <[email protected]>
---
 arch/arm/include/asm/arch-pxa/pxa-regs.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-pxa/pxa-regs.h +3 -0
index 06711f7..3dd0aba 100644
@@ -2419,6 +2419,9 @@ typedef void		(*ExcpHndlr) (void) ;
 #define MDMRS		__REG(0x48000040)  /* MRS value to be written to SDRAM */
 #define BOOT_DEF	__REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
 
+#define	MDREFR_ALTREFA	(1 << 31)	/* Exiting Alternate Bus Master Mode Refresh Control */
+#define	MDREFR_ALTREFB	(1 << 30)	/* Entering Alternate Bus Master Mode Refresh Control */
+#define	MDREFR_K0DB4	(1 << 29)	/* SDCLK0 Divide by 4 Control/Status */
 #define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
 #define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
 #define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
Signature · 1 line
1.7.0
#2 lore raw

PATCH 1/2 PXA: Add UP2OCR register bit definitions

In reply to Marek Vasut
Quoted 13 lines · Marek Vasut

This register is used on PXA to control the USB Port2 operation (USB Port2 is the host port).

Signed-off-by Marek Vasut <[email protected]>
---
 arch/arm/include/asm/arch-pxa/pxa-regs.h |   20 ++++++++++++++++----
 1 files changed, 16 insertions(+), 4 deletions(-)
arch/arm/include/asm/arch-pxa/pxa-regs.h +0 -0
index a25d4c5..06711f7 100644

arch/arm/include/asm/arch-pxa/pxa-regs.h typedef void (*ExcpHndlr) (void) ; · line 997

Quoted 6 lines
arch/arm/include/asm/arch-pxa/pxa-regs.h +0 -3
@@ -992,10 +992,6 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UHCHIE		__REG(0x4C000068)
 #define UHCHIT		__REG(0x4C00006C)
 
-#if defined(CONFIG_CPU_MONAHANS)
-#define UP2OCR		__REG(0x40600020)
-#endif

Previously this was only defined for CPU_MONAHANS. If this really is a common register, add a comment to the commit log.

Be aware that the preferred method of register access is through structure member elements. In this case, this is a trival change so I do not believe converting the access is warranted. But it will likely be in the future.

Quoted 13 lines
arch/arm/include/asm/arch-pxa/pxa-regs.h +5 -1
-
 #define UHCHR_FSBIR	(1<<0)
 #define UHCHR_FHR	(1<<1)
 #define UHCHR_CGR	(1<<2)

@@ -1015,6 +1011,22 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UHCHIE_HBAIE	(1<<8)
 #define UHCHIE_RWIE	(1<<7)
 
+#define UP2OCR		__REG(0x40600020)
+
+#define	UP2OCR_HXOE	(1<<17)
+#define	UP2OCR_HXS	(1<<16)
+#define	UP2OCR_IDON	(1<<10)

arch/arm/include/asm/arch-pxa/pxa-regs.h typedef void (*ExcpHndlr) (void) ; · line 1028

Quoted 10 lines
arch/arm/include/asm/arch-pxa/pxa-regs.h +10 -0
+#define	UP2OCR_EXSUS	(1<<9)
+#define	UP2OCR_EXSP	(1<<8)
+#define	UP2OCR_DMSTATE	(1<<7)
+#define	UP2OCR_VPM	(1<<6)
+#define	UP2OCR_DPSTATE	(1<<5)
+#define	UP2OCR_DPPUE	(1<<4)
+#define	UP2OCR_DMPDE	(1<<3)
+#define	UP2OCR_DPPDE	(1<<2)
+#define	UP2OCR_CPVPE	(1<<1)
+#define	UP2OCR_CPVEN	(1<<0)

For readability, change the tab after #define to a space. This is an issue in the 2/2 patch as well

Tom

Quoted 4 lines
arch/arm/include/asm/arch-pxa/pxa-regs.h +1 -0
+
 #endif
 
 /*