85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled

PATCH New Kumar Gala 2 participants 5 messages Apr 28, 2010

Subsystems (2)

PowerPC Block layer

lore

Share & tools

lore

Kumar Gala

author

2010-04-28 08:05 UTC #0 lore raw

PATCH v2 1/2 85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled

The new is_serdes_configured covers a broader range of devices than the PCI specific code. Use it instead as we convert away from the is_fsl_pci_cfg() code.

Additionally move to setting LAWs for PCI based on if its configured. Also updated PCI FDT fixup code to remove PCI controllers from dtb if they are configured.

Signed-off-by Kumar Gala <[email protected]>

---
* Added code to handle dynamic LAW setup for PCI
* Added removing of PCI controller nodes from dtb if not cfg

 arch/powerpc/cpu/mpc8xxx/pci_cfg.c    |   12 ------------
 board/freescale/mpc8536ds/law.c       |    8 --------
 board/freescale/mpc8536ds/mpc8536ds.c |   33 +++++++++++++++++++++++++++++----
 3 files changed, 29 insertions(+), 24 deletions(-)

arch/powerpc/cpu/mpc8xxx/pci_cfg.c +0 ~~-12~~

index 85995ca..186936f 100644
@@ -56,18 +56,6 @@ static struct pci_info pci_config_info[] =
 #elif defined(CONFIG_MPC8536)
 static struct pci_info pci_config_info[] =
 {
-	[LAW_TRGT_IF_PCI] = {
-		.cfg =   0,
-	},
-	[LAW_TRGT_IF_PCIE_1] = {
-		.cfg =   (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7),
-	},
-	[LAW_TRGT_IF_PCIE_2] = {
-		.cfg =   (1 << 5) | (1 << 7),
-	},
-	[LAW_TRGT_IF_PCIE_3] = {
-		.cfg =   (1 << 7),
-	},
 };
 #elif defined(CONFIG_MPC8544)
 static struct pci_info pci_config_info[] =

board/freescale/mpc8536ds/law.c +0 -8

index 1f11563..61b7454 100644
@@ -28,15 +28,7 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };

board/freescale/mpc8536ds/mpc8536ds.c +29 -4

index 253ed18..8daa0c3 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -30,6 +30,7 @@
 #include <asm/fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/io.h>
+#include <asm/fsl_serdes.h>
 #include <spd.h>
 #include <miiphy.h>
 #include <libfdt.h>

@@ -219,9 +220,13 @@ void pci_init_board(void)
 
 	puts("\n");
 #ifdef CONFIG_PCIE3
-	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
+	pcie_configured = is_serdes_configured(PCIE3);
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
+				LAW_TRGT_IF_PCIE_3);
+		set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
+				LAW_TRGT_IF_PCIE_3);
 		SET_STD_PCIE_INFO(pci_info[num], 3);
 		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
 		printf ("    PCIE3 connected to Slot3 as %s (base address %lx)\n",

@@ -239,9 +244,13 @@ void pci_init_board(void)
 #endif
 
 #ifdef CONFIG_PCIE1
-	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+	pcie_configured = is_serdes_configured(PCIE1);
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
+				LAW_TRGT_IF_PCIE_1);
+		set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
+				LAW_TRGT_IF_PCIE_1);
 		SET_STD_PCIE_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 		printf ("    PCIE1 connected to Slot1 as %s (base address %lx)\n",

@@ -259,9 +268,13 @@ void pci_init_board(void)
 #endif
 
 #ifdef CONFIG_PCIE2
-	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+	pcie_configured = is_serdes_configured(PCIE2);
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
+		set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
+				LAW_TRGT_IF_PCIE_2);
+		set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
+				LAW_TRGT_IF_PCIE_2);
 		SET_STD_PCIE_INFO(pci_info[num], 2);
 		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
 		printf ("    PCIE2 connected to Slot 2 as %s (base address %lx)\n",

@@ -285,6 +298,10 @@ void pci_init_board(void)
 	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
+				LAW_TRGT_IF_PCI);
+		set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
+				LAW_TRGT_IF_PCI);
 		SET_STD_PCI_INFO(pci_info[num], 1);
 		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
 		printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",

@@ -540,15 +557,23 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 #ifdef CONFIG_PCI1
 	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
+#else
+	ft_fsl_pci_setup(blob, "pci0", NULL);
 #endif
 #ifdef CONFIG_PCIE2
 	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
+#else
+	ft_fsl_pci_setup(blob, "pci1", NULL);
 #endif
 #ifdef CONFIG_PCIE2
 	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#else
+	ft_fsl_pci_setup(blob, "pci2", NULL);
 #endif
 #ifdef CONFIG_PCIE1
 	ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
+#else
+	ft_fsl_pci_setup(blob, "pci3", NULL);
 #endif
 #ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_fdt_fixup(blob);

Signature · 1 line

1.6.0.6

Kumar Gala

author

2010-04-28 08:05 UTC #1 lore raw

PATCH v2 2/2 85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled

On the MPC85xx platform if we have SATA its connected on SERDES. Determing if SATA is enabled via sata_initialize should not be board specific and thus we move it out of the MPC8536DS board code.

Additionally, now that we have is_serdes_configured() we can determine if the given SATA port is enabled and error out if its not in the driver.

Signed-off-by Kumar Gala <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu_init.c   |   14 +++++++++++++-
 board/freescale/mpc8536ds/mpc8536ds.c |   11 -----------
 drivers/block/fsl_sata.c              |   14 +++++++++++++-
 3 files changed, 26 insertions(+), 13 deletions(-)

arch/powerpc/cpu/mpc85xx/cpu_init.c +13 -1

index e578b29..99431dc 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Modified by Xianghua Xiao, X.Xiao at motorola.com

@@ -30,9 +30,11 @@
 #include <watchdog.h>
 #include <asm/processor.h>
 #include <ioports.h>
+#include <sata.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
 #include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -418,3 +420,13 @@ void arch_preboot_os(void)
 
 	setup_ivors();
 }
+
+#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
+int sata_initialize(void)
+{
+	if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
+		return __sata_initialize();
+
+	return 1;
+}
+#endif

board/freescale/mpc8536ds/mpc8536ds.c +0 ~~-11~~

index 8daa0c3..1968106 100644
@@ -498,17 +498,6 @@ get_board_ddr_clk(ulong dummy)
 }
 #endif
 
-int sata_initialize(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	uint sdrs2_io_sel =
-		(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
-	if (sdrs2_io_sel & 0x04)
-		return 1;
-
-	return __sata_initialize();
-}
-
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_TSEC_ENET

drivers/block/fsl_sata.c +13 -1

index 8878560..4b97a0e 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
  *		Dave Liu <[email protected]>
  *
  * This program is free software; you can redistribute it and/or

@@ -22,6 +22,7 @@
 #include <command.h>
 #include <asm/io.h>
 #include <asm/processor.h>
+#include <asm/fsl_serdes.h>
 #include <malloc.h>
 #include <libata.h>
 #include <fis.h>

@@ -129,6 +130,17 @@ int init_sata(int dev)
 		return -1;
 	}
 
+#ifdef CONFIG_MPC85xx
+	if ((dev == 0) && (!is_serdes_configured(SATA1))) {
+		printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
+		return -1;
+	}
+	if ((dev == 1) && (!is_serdes_configured(SATA2))) {
+		printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
+		return -1;
+	}
+#endif
+
 	/* Allocate SATA device driver struct */
 	sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
 	if (!sata) {

Signature · 1 line

1.6.0.6

Li Yang-R58472

2010-04-28 08:17 UTC #2 lore raw

PATCH v2 1/2 85xx/mpc8536ds: Use is_serdes_configured()to determine of PCIe enabled

In reply to Kumar Gala

Quoted 12 lines

Subject: [U-Boot] [PATCH v2 1/2] 85xx/mpc8536ds: Use is_serdes_configured()to determine of PCIe enabled
The new is_serdes_configured covers a broader range of devices than the PCI specific code. Use it instead as we convert away from the is_fsl_pci_cfg() code.
Additionally move to setting LAWs for PCI based on if its configured. Also updated PCI FDT fixup code to remove PCI controllers from dtb if they are configured.
Signed-off-by Kumar Gala <[email protected]>

Quoted 8 lines

---
* Added code to handle dynamic LAW setup for PCI
* Added removing of PCI controller nodes from dtb if not cfg
arch/powerpc/cpu/mpc8xxx/pci_cfg.c    |   12 ------------
board/freescale/mpc8536ds/law.c       |    8 --------
board/freescale/mpc8536ds/mpc8536ds.c |   33 
+++++++++++++++++++++++++++++----

Wouldn't it be better to share the PCIE initialization code through all the MPC85xx boards? Like in the P2020 serdes patch series I proposed last year. What do you think?

- Leo

Li Yang-R58472

2010-04-28 08:25 UTC #3 lore raw

PATCH v2 1/2 85xx/mpc8536ds: Use is_serdes_configured()to determine of PCIe enabled

In reply to Kumar Gala

Quoted 18 lines

Quoted 5 lines
Subject: [U-Boot] [PATCH v2 1/2] 85xx/mpc8536ds: Use is_serdes_configured()to determine of PCIe enabled
The new is_serdes_configured covers a broader range of
devices than the
Quoted 12 lines
PCI specific code. Use it instead as we convert away from the is_fsl_pci_cfg() code.
Additionally move to setting LAWs for PCI based on if its configured. Also updated PCI FDT fixup code to remove PCI controllers from dtb if they are configured.
Signed-off-by Kumar Gala <[email protected]>
---
* Added code to handle dynamic LAW setup for PCI
* Added removing of PCI controller nodes from dtb if not cfg

Quoted 8 lines

Quoted 4 lines
arch/powerpc/cpu/mpc8xxx/pci_cfg.c    |   12 ------------
board/freescale/mpc8536ds/law.c       |    8 --------
board/freescale/mpc8536ds/mpc8536ds.c |   33 
+++++++++++++++++++++++++++++----
Wouldn't it be better to share the PCIE initialization code through all the MPC85xx boards? Like in the P2020 serdes patch series I proposed last year. What do you think?

The patch can be referenced at
http://www.mail-archive.com/u-boot at lists.denx.de/msg26339.html

- Leo

Kumar Gala

author

2010-04-28 08:52 UTC #4 lore raw

PATCH v2 1/2 85xx/mpc8536ds: Use is_serdes_configured()to determine of PCIe enabled

Quoted 23 lines · On Apr 28, 2010, at 3:25 AM, Li Yang-R58472 wrote:

Quoted 23 lines
Quoted 5 lines
Subject: [U-Boot] [PATCH v2 1/2] 85xx/mpc8536ds: Use is_serdes_configured()to determine of PCIe enabled
The new is_serdes_configured covers a broader range of
devices than the
Quoted 16 lines
PCI specific code. Use it instead as we convert away from the is_fsl_pci_cfg() code.
Additionally move to setting LAWs for PCI based on if its configured. Also updated PCI FDT fixup code to remove PCI controllers from dtb if they are configured.
Signed-off-by Kumar Gala <[email protected]>
---
* Added code to handle dynamic LAW setup for PCI
* Added removing of PCI controller nodes from dtb if not cfg
arch/powerpc/cpu/mpc8xxx/pci_cfg.c    |   12 ------------
board/freescale/mpc8536ds/law.c       |    8 --------
board/freescale/mpc8536ds/mpc8536ds.c |   33 
+++++++++++++++++++++++++++++----

Quoted 8 lines

Quoted 3 lines
Wouldn't it be better to share the PCIE initialization code through all the MPC85xx boards? Like in the P2020 serdes patch series I proposed last year. What do you think?
The patch can be referenced at
http://www.mail-archive.com/u-boot at lists.denx.de/msg26339.html
- Leo

Yeah, we can get there. Just one step at a time.

- k