MIPS: Alchemy: basic Au1300 SoC support
Subsystems (4)
PATCH 1/1 MIPS: Alchemy: basic Au1300 SoC support
Add support for the Au1300 SoC:
- CPU core detection
- New GPIO/Interrupt controller code,
- enable DBDMA, video and PSCs for new subtype.
Signed-off-by Manuel Lauss <[email protected]>
---
I'm submitting this in the hopes of some feedback. The code here adds just interrupt controller support which should be enough to get a new board started.
I'm still working on DB1300 support; unfortunately the FPGA's irq multiplexer is extremely problematic: it generates mostly spurious interrupts or refuses to generate any more when poked the wrong way.
I've tried to contact Kevin Hickey and other people inside RMI for assistance but got no response in the last 3 months.
Please have a look,
Thanks!
Manuel Lauss
arch/mips/alchemy/Kconfig | 9 + arch/mips/alchemy/common/Makefile | 2 + arch/mips/alchemy/common/dbdma.c | 48 ++- arch/mips/alchemy/common/gpioint.c | 462 ++++++++++++++++++++++ arch/mips/alchemy/common/gpiolib-au1300.c | 54 +++ arch/mips/alchemy/common/platform.c | 9 + arch/mips/alchemy/common/power.c | 9 +- arch/mips/alchemy/common/time.c | 1 + arch/mips/include/asm/cpu.h | 8 + arch/mips/include/asm/mach-au1x00/au1000.h | 197 +++++++++- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 33 ++ arch/mips/include/asm/mach-au1x00/gpio-au1300.h | 215 ++++++++++ arch/mips/include/asm/mach-au1x00/gpio.h | 4 + arch/mips/kernel/cpu-probe.c | 18 + drivers/i2c/busses/Kconfig | 2 +- drivers/spi/Kconfig | 2 +- drivers/video/Kconfig | 17 +- 17 files changed, 1071 insertions(+), 19 deletions(-) create mode 100644 arch/mips/alchemy/common/gpioint.c create mode 100644 arch/mips/alchemy/common/gpiolib-au1300.c create mode 100644 arch/mips/include/asm/mach-au1x00/gpio-au1300.h
arch/mips/alchemy/Kconfig +9 -0
@@ -2,6 +2,10 @@ config ALCHEMY_GPIOINT_AU1000 bool +# au1300-style GPIO/INT controller +config ALCHEMY_GPIOINT_AU1300 + bool + # select this in your board config if you don't want to use the gpio # namespace as documented in the manuals. In this case however you need # to create the necessary gpio_* functions in your board code/headers!
@@ -155,6 +159,11 @@ config SOC_AU1200 select SOC_AU1X00 select ALCHEMY_GPIOINT_AU1000 +config SOC_AU1300 + bool + select SOC_AU1X00 + select ALCHEMY_GPIOINT_AU1300 + config SOC_AU1X00 bool select 64BIT_PHYS_ADDR
arch/mips/alchemy/common/Makefile +2 -0
@@ -9,11 +9,13 @@ obj-y += prom.o time.o clocks.o platform.o power.o setup.o \ sleeper.o dma.o dbdma.o obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o +obj-$(CONFIG_ALCHEMY_GPIOINT_AU1300) += gpioint.o # optional gpiolib support ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) ifeq ($(CONFIG_GPIOLIB),y) obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o + obj-$(CONFIG_ALCHEMY_GPIOINT_AU1300) += gpiolib-au1300.o endif endif
arch/mips/alchemy/common/dbdma.c +44 -4
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arch/mips/alchemy/common/gpioint.c new file +462 -0
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arch/mips/alchemy/common/gpiolib-au1300.c new file +54 -0
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arch/mips/alchemy/common/platform.c +9 -0
@@ -53,6 +53,11 @@ static struct plat_serial8250_port au1x00_uart_data[] = { #elif defined(CONFIG_SOC_AU1200) PORT(UART0_PHYS_ADDR, AU1200_UART0_INT), PORT(UART1_PHYS_ADDR, AU1200_UART1_INT), +#elif defined(CONFIG_SOC_AU1300) + PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT), + PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT), + PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT), + PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT), #endif #endif /* CONFIG_SERIAL_8250_AU1X00 */ { },
@@ -66,6 +71,7 @@ static struct platform_device au1xx0_uart_device = { }, }; +#ifdef FOR_PLATFORM_C_USB_HOST_INT /* OHCI (USB full speed host controller) */ static struct resource au1xxx_usb_ohci_resources[] = { [0] = {
@@ -93,6 +99,7 @@ static struct platform_device au1xxx_usb_ohci_device = { .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), .resource = au1xxx_usb_ohci_resources, }; +#endif /*** AU1100 LCD controller ***/
@@ -412,7 +419,9 @@ void __init au1xxx_override_eth_cfg(unsigned int port,static struct platform_device *au1xxx_platform_devices[]__initdata = { &au1xx0_uart_device, +#ifdef FOR_PLATFORM_C_USB_HOST_INT &au1xxx_usb_ohci_device, +#endif #ifdef CONFIG_FB_AU1100 &au1100_lcd_device, #endif
arch/mips/alchemy/common/power.c +7 -2
@@ -54,7 +54,9 @@ static unsigned int sleep_uart0_fifoctl;static unsigned int sleep_uart0_linectl;static unsigned int sleep_uart0_clkdiv;static unsigned int sleep_uart0_enable; +#ifndef CONFIG_SOC_AU1300 static unsigned int sleep_usb[2 ]; +#endif static unsigned int sleep_sys_clocks[5 ];static unsigned int sleep_sys_pinfunc;static unsigned int sleep_static_memctlr[4 ][3 ];
@@ -79,7 +81,8 @@ static void save_core_regs(void)au_sync ();#ifndef CONFIG_SOC_AU1200 -/* Shutdown USB host/device. */ +#ifndef CONFIG_SOC_AU1300 /* doesn't apply to Au1300 USB */ +/* Shutdown USB host/device. */ sleep_usb[0 ] =au_readl (USB_HOST_CONFIG );/* There appears to be some undocumented reset register.... */
@@ -91,7 +94,7 @@ static void save_core_regs(void) sleep_usb[1 ] =au_readl (USBD_ENABLE );au_writel (0 ,USBD_ENABLE );au_sync (); - +#endif /* au1300 */ #else /* AU1200 */ /* enable access to OTG mmio so we can save OTG CAP/MUX.
@@ -147,9 +150,11 @@ static void restore_core_regs(void)au_sync ();#ifndef CONFIG_SOC_AU1200 +#ifndef CONFIG_SOC_AU1300 /* doesn't apply to Au1300 either */ au_writel (sleep_usb[0 ],USB_HOST_CONFIG );au_writel (sleep_usb[1 ],USBD_ENABLE );au_sync (); +#endif #else /* enable accces to OTG memory */ au_writel (au_readl (USB_MSR_BASE +4 ) | (1 <<6 ),USB_MSR_BASE +4 );
arch/mips/alchemy/common/time.c +1 -0
@@ -179,6 +179,7 @@ static int alchemy_m2inttab[] __initdata = {AU1100_RTC_MATCH2_INT ,AU1550_RTC_MATCH2_INT ,AU1200_RTC_MATCH2_INT , + AU1300_RTC_MATCH2_INT, };void __init plat_time_init (void )
arch/mips/include/asm/cpu.h +8 -0
@@ -33,6 +33,7 @@#define PRID_COMP_TOSHIBA 0x070000#define PRID_COMP_LSI 0x080000#define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_RMI 0x0c0000#define PRID_COMP_CAVIUM 0x0d0000
@@ -121,6 +122,13 @@#define PRID_REV_BCM6368 0x0030/* +* These are the PRID's for when 23:16 == PRID_COMP_RMI +*/ + +#define PRID_IMP_AU13XX 0x8000 + + +/* * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM */
arch/mips/include/asm/mach-au1x00/au1000.h +194 -3
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arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +33 -0
@@ -195,6 +195,39 @@ typedef volatile struct au1xxx_ddma_desc {#define DSCR_CMD0_CIM_SYNC 26#endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU1300 +#define DSCR_CMD0_UART0_TX 0 +#define DSCR_CMD0_UART0_RX 1 +#define DSCR_CMD0_UART1_TX 2 +#define DSCR_CMD0_UART1_RX 3 +#define DSCR_CMD0_UART2_TX 4 +#define DSCR_CMD0_UART2_RX 5 +#define DSCR_CMD0_UART3_TX 6 +#define DSCR_CMD0_UART3_RX 7 +#define DSCR_CMD0_SDMS_TX0 8 +#define DSCR_CMD0_SDMS_RX0 9 +#define DSCR_CMD0_SDMS_TX1 10 +#define DSCR_CMD0_SDMS_RX1 11 +#define DSCR_CMD0_AES_TX 12 +#define DSCR_CMD0_AES_RX 13 +#define DSCR_CMD0_PSC0_TX 14 +#define DSCR_CMD0_PSC0_RX 15 +#define DSCR_CMD0_PSC1_TX 16 +#define DSCR_CMD0_PSC1_RX 17 +#define DSCR_CMD0_PSC2_TX 18 +#define DSCR_CMD0_PSC2_RX 19 +#define DSCR_CMD0_PSC3_TX 20 +#define DSCR_CMD0_PSC3_RX 21 +#define DSCR_CMD0_LCD 22 +#define DSCR_CMD0_NAND_FLASH 23 +#define DSCR_CMD0_SDMS_TX2 24 +#define DSCR_CMD0_SDMS_RX2 25 +#define DSCR_CMD0_CIM_SYNC 26 +#define DSCR_CMD0_UDMA 27 +#define DSCR_CMD0_DMA_REQ0 28 +#define DSCR_CMD0_DMA_REQ1 29 +#endif /* CONFIG_SOC_AU1300 */ +#define DSCR_CMD0_THROTTLE 30#define DSCR_CMD0_ALWAYS 31#define DSCR_NDEV_IDS 32
arch/mips/include/asm/mach-au1x00/gpio-au1300.h new file +215 -0
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arch/mips/include/asm/mach-au1x00/gpio.h +4 -0
@@ -5,6 +5,10 @@#include <asm/mach-au1x00/gpio-au1000.h> +#elif defined(CONFIG_ALCHEMY_GPIOINT_AU1300 ) + +#include <asm/mach-au1x00/gpio-au1300.h> +#endif #endif /* _ALCHEMY_GPIO_H_ */
arch/mips/kernel/cpu-probe.c +18 -0
@@ -826,6 +826,21 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_rmi (struct cpuinfo_mips *c,int cpu) +{ +decode_configs (c); + +switch (c->processor_id &0xff00 ) { +case PRID_IMP_AU13XX : + c->cputype =CPU_ALCHEMY ; + __cpu_name[cpu] ="Au13xx" ; +break ; +default : +panic ("Unknown RMI core!\n" ); +break ; + } +} +static inline void cpu_probe_sibyte (struct cpuinfo_mips *c,unsigned int cpu) {decode_configs (c);
@@ -967,6 +982,9 @@ __cpuinit void cpu_probe(void)case PRID_COMP_NXP :cpu_probe_nxp (c, cpu);break ; +case PRID_COMP_RMI : +cpu_probe_rmi (c, cpu); +break ;case PRID_COMP_CAVIUM :cpu_probe_cavium (c, cpu);break ;
drivers/i2c/busses/Kconfig +1 -1
@@ -297,7 +297,7 @@ config I2C_AT91 config I2C_AU1550 tristate "Au1550/Au1200 SMBus interface" - depends on SOC_AU1550 || SOC_AU1200 + depends on SOC_AU1550 || SOC_AU1200 || SOC_AU1300 help If you say yes to this option, support will be included for the Au1550 and Au1200 SMBus interface.
drivers/spi/Kconfig +1 -1
@@ -68,7 +68,7 @@ config SPI_BFIN config SPI_AU1550 tristate "Au1550/Au12x0 SPI Controller" - depends on (SOC_AU1550 || SOC_AU1200) && EXPERIMENTAL + depends on (SOC_AU1550 || SOC_AU1200 || SOC_AU1300) && EXPERIMENTAL select SPI_BITBANG help If you say yes to this option, support will be included for the
drivers/video/Kconfig +9 -8
@@ -1694,15 +1694,16 @@ config FB_AU1100 au1100fb:panel=<name>. config FB_AU1200 - bool "Au1200 LCD Driver" - depends on (FB = y) && MIPS && SOC_AU1200 - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT + bool "Au1200/Au1300 LCD Driver" + depends on (FB = y) && (SOC_AU1200 || SOC_AU1300) + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_SYS_FOPS help - This is the framebuffer driver for the AMD Au1200 SOC. It can drive - various panels and CRTs by passing in kernel cmd line option - au1200fb:panel=<name>. + This is the framebuffer driver for the AMD Au1200/Au1300 SOCs. + It can drive various panels and CRTs by passing in kernel + cmdline option au1200fb:panel=<name>. source "drivers/video/geode/Kconfig"
Signature · 1 line
1.7.0.4