powerpc/8xxx: Distinguish between incompatible SEC h/w types

PATCH New Kumar Gala 1 participant 4 messages Jun 10, 2010 – Jun 30, 2010 PowerPC

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Kumar Gala

author

2010-06-10 04:46 UTC #0 lore raw

PATCH 1/1 powerpc/8xxx: Distinguish between incompatible SEC h/w types

From: Kim Phillips <[email protected]>

CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x. Parts with newer SEC h/w versions will increment the number to accomodate incompatible code changes.

Signed-off-by Kim Phillips <[email protected]>

Signed-off-by Kumar Gala <[email protected]>

---
 arch/powerpc/cpu/mpc8xxx/fdt.c    |    6 +++---
 arch/powerpc/include/asm/config.h |    7 +++++++
 include/fdt_support.h             |    2 +-
 3 files changed, 11 insertions(+), 4 deletions(-)

arch/powerpc/cpu/mpc8xxx/fdt.c +3 -3

index 79d3cdf..d0e06e2 100644
@@ -97,11 +97,11 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 }
 #endif /* CONFIG_HAS_FSL_DR_USB */
 
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx)
 /*
  * update crypto node properties to a specified revision of the SEC
- * called with sec_rev == 0 if not on an mpc8xxxE processor
+ * called with sec_rev == 0 if not on an E processor
  */
+#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */
 void fdt_fixup_crypto_node(void *blob, int sec_rev)
 {
 	const struct sec_rev_prop {

@@ -183,4 +183,4 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
 		printf("WARNING: could not set crypto property: %s\n",
 		       fdt_strerror(err));
 }
-#endif /* defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) */
+#endif

arch/powerpc/include/asm/config.h +7 -0

index fc3facb..1c61784 100644
@@ -66,6 +66,13 @@
 #define CONFIG_TSECV2
 #endif
 
+/*
+ * SEC (crypto unit) major compatible version determination
+ */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+#endif
+
 /* Number of TLB CAM entries we have on FSL Book-E chips */
 #if defined(CONFIG_E500MC)
 #define CONFIG_SYS_NUM_TLBCAMS	64

include/fdt_support.h +1 -1

index 9a453af..fc16159 100644
@@ -59,7 +59,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd);
 static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
 #endif /* CONFIG_HAS_FSL_DR_USB */
 
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
+#if defined(CONFIG_SYS_FSL_SEC_COMPAT)
 void fdt_fixup_crypto_node(void *blob, int sec_rev);
 #else
 static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}

Signature · 1 line

1.6.0.6

Kumar Gala

author

2010-06-10 04:46 UTC #1 lore raw

PATCH 1/1 powerpc/8xxx: Add base support for the SEC4

From: Kim Phillips <[email protected]>

Signed-off-by Kim Phillips <[email protected]>

Signed-off-by Kumar Gala <[email protected]>

---
 arch/powerpc/cpu/mpc8xxx/fdt.c        |    6 +++++
 arch/powerpc/include/asm/config.h     |    4 ++-
 arch/powerpc/include/asm/immap_85xx.h |   38 +++++++++++++++++++++++++++++++++
 3 files changed, 47 insertions(+), 1 deletions(-)

arch/powerpc/cpu/mpc8xxx/fdt.c +6 -0

index d0e06e2..738394f 100644
@@ -183,4 +183,10 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
 		printf("WARNING: could not set crypto property: %s\n",
 		       fdt_strerror(err));
 }
+#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4  /* SEC4 */
+void fdt_fixup_crypto_node(void *blob, int sec_rev)
+{
+	if (!sec_rev)
+		fdt_del_node_and_alias(blob, "crypto");
+}
 #endif

arch/powerpc/include/asm/config.h +3 -1

index 1c61784..75e19a5 100644
@@ -69,7 +69,9 @@
 /*
  * SEC (crypto unit) major compatible version determination
  */
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
+#if defined(CONFIG_FSL_CORENET)
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #endif

arch/powerpc/include/asm/immap_85xx.h +38 -0

index 74236a2..8b773be 100644
@@ -2073,6 +2073,41 @@ enum {
 	FSL_SRDS_B3_LANE_D = 23,
 };
 
+/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+typedef struct ccsr_sec {
+	u8	res1[0xfa0];
+	u32	crnr_ms;	/* CHA Revision Number Register, MS */
+	u32	crnr_ls;	/* CHA Revision Number Register, LS */
+	u32	ctpr_ms;	/* Compile Time Parameters Register, MS */
+#define SEC_CTPR_MS_AXI_LIODN		0x08000000
+#define SEC_CTPR_MS_QI			0x02000000
+	u32	ctpr_ls;	/* Compile Time Parameters Register, LS */
+	u8	res2[0x10];
+	u32	far_ms;		/* Fault Address Register, MS */
+	u32	far_ls;		/* Fault Address Register, LS */
+	u32	falr;		/* Fault Address LIODN Register */
+	u32	fadr;		/* Fault Address Detail Register */
+	u8	res3[0x4];
+	u32	csta;		/* CAAM Status Register */
+	u8	res4[0x8];
+	u32	rvid;		/* Run Time Integrity Checking Version ID Reg.*/
+#define SEC_RVID_MA			0x0f000000
+	u32	ccbvid;		/* CHA Cluster Block Version ID Register */
+	u32	chavid_ms;	/* CHA Version ID Register, MS */
+	u32	chavid_ls;	/* CHA Version ID Register, LS */
+	u32	chanum_ms;	/* CHA Number Register, MS */
+#define SEC_CHANUM_MS_JQNUM_MASK	0xf0000000
+#define SEC_CHANUM_MS_JQNUM_SHIFT	28
+#define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
+#define SEC_CHANUM_MS_DECONUM_SHIFT	24
+	u32	chanum_ls;	/* CHA Number Register, LS */
+	u32	caamvid_ms;	/* CAAM Version ID Register, MS */
+	u32	caamvid_ls;	/* CAAM Version ID Register, LS */
+	u8	res5[0xf000];
+} ccsr_sec_t;
+#endif
+
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x8000

@@ -2089,6 +2124,7 @@ enum {
 #define CONFIG_SYS_MPC85xx_USB_OFFSET		0x210000
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x220000
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x221000
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x300000
 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET	0x318000
 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET	0x31a000
 #define CONFIG_SYS_FSL_FM1_OFFSET		0x400000

@@ -2181,6 +2217,8 @@ enum {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 #define CONFIG_SYS_FSL_FM2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
+#define CONFIG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 
 #define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2010-06-30 09:36 UTC #2 lore raw

PATCH 1/1 powerpc/8xxx: Add base support for the SEC4

Quoted 9 lines · Kumar Gala

From: Kim Phillips <[email protected]>
Signed-off-by Kim Phillips <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
arch/powerpc/cpu/mpc8xxx/fdt.c        |    6 +++++
arch/powerpc/include/asm/config.h     |    4 ++-
arch/powerpc/include/asm/immap_85xx.h |   38 +++++++++++++++++++++++++++++++++
3 files changed, 47 insertions(+), 1 deletions(-)

applied to 85xx

- k

Kumar Gala

author Applied

2010-06-30 09:36 UTC #3 lore raw

PATCH 1/1 powerpc/8xxx: Distinguish between incompatible SEC h/w types

In reply to Kumar Gala

Quoted 6 lines · Kumar Gala

From: Kim Phillips <[email protected]>
CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x. Parts with newer SEC h/w versions will increment the number to accomodate incompatible code changes.

Quoted 7 lines

Signed-off-by Kim Phillips <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
arch/powerpc/cpu/mpc8xxx/fdt.c    |    6 +++---
arch/powerpc/include/asm/config.h |    7 +++++++
include/fdt_support.h             |    2 +-
3 files changed, 11 insertions(+), 4 deletions(-)

applied to 85xx

- k