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radeon/kms: fix powerpc/rn50 untiled behaviour.

PATCH New Dave Airlie 1 participant 1 message Jun 11, 2010

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Dave Airlie

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PATCH 1/1 radeon/kms: fix powerpc/rn50 untiled behaviour.

From: Dave Airlie <[email protected]>

Installing 2.6.34 on a Power5/rn50 combo machine, X showed buggy sw rendering, enabling tiling in the DDX fixed it. Investigation showed that a further /16 was needed in the untiled case on this chipset. Need further investigations on what other chips this could affect, possibly rv100->rv280.

Signed-off-by Dave Airlie <[email protected]>
---
 drivers/gpu/drm/radeon/r100.c |   20 ++++++++++++++------
 1 files changed, 14 insertions(+), 6 deletions(-)
drivers/gpu/drm/radeon/r100.c +14 -6
index cf89aa2..1930db6 100644
@@ -2604,12 +2604,6 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
 	int surf_index = reg * 16;
 	int flags = 0;
 
-	/* r100/r200 divide by 16 */
-	if (rdev->family < CHIP_R300)
-		flags = pitch / 16;
-	else
-		flags = pitch / 8;
-
 	if (rdev->family <= CHIP_RS200) {
 		if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
 				 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))

@@ -2633,6 +2627,20 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
 	if (tiling_flags & RADEON_TILING_SWAP_32BIT)
 		flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
 
+	/* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
+	if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
+		if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
+			if (ASIC_IS_RN50(rdev))
+				pitch /= 16;
+	}
+
+	/* r100/r200 divide by 16 */
+	if (rdev->family < CHIP_R300)
+		flags |= pitch / 16;
+	else
+		flags |= pitch / 8;
+
+
 	DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
 	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
 	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
Signature · 9 lines
1.6.5.2


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