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patches on my 'for-anholt' branch

PATCH RESEND In review Zhenyu Wang 6 participants 18 messages Jun 12, 2010 – Jul 6, 2010

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DRM drivers Intel i915
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Zhenyu Wang

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#0 lore raw

Eric, I've queued some patches on my 'for-anholt' branch of drm-intel tree. The first and second ones are resent patch for fixing eDP through PCH DP port. And following patches are watermark fixes that recently investigated by Yakui.

The last one is FBC enabling patch for Ironlake, after Yakui fixed flicker issue with origin FBC enabling patch by programming the cursor wm properly from an Ironlake sighting.

Thanks.

author
#1 lore raw

PATCH RESEND 1/7 drm/i915: Add the support of eDP on DP-D for Ibex/CPT

From: Zhao Yakui <[email protected]>

This one adds support for eDP that connected on PCH DP-D port instead of CPU DP-A port, and only DP-D port could be used for eDP.

https://bugs.freedesktop.org/show_bug.cgi?id=27220

Signed-off-by Zhao Yakui <[email protected]>
Tested-by Jan-Hendrik Zab <[email protected]>
Tested-by Templar <[email protected]>
Signed-off-by Zhenyu Wang <[email protected]>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 drivers/gpu/drm/i915/intel_dp.c      |   71 +++++++++++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_drv.h     |    1 +
 3 files changed, 64 insertions(+), 10 deletions(-)
drivers/gpu/drm/i915/intel_display.c +1 -1
index 88a1ab7..7ffd51c 100644
@@ -3449,7 +3449,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 				temp |= PIPE_8BPC;
 			else
 				temp |= PIPE_6BPC;
-		} else if (is_edp) {
+		} else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
 			switch (dev_priv->edp_bpp/3) {
 			case 8:
 				temp |= PIPE_8BPC;
drivers/gpu/drm/i915/intel_dp.c +62 -9

167 lines not on this page · raw message

drivers/gpu/drm/i915/intel_drv.h +1 -0
index df931f7..db17370 100644
@@ -179,6 +179,7 @@ extern void intel_dp_init(struct drm_device *dev, int dp_reg);
 void
 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 		 struct drm_display_mode *adjusted_mode);
+extern bool intel_pch_has_edp(struct drm_crtc *crtc);
 extern void intel_edp_link_config (struct intel_encoder *, int *, int *);
Signature · 1 line
1.7.0.4
#2 lore raw

Re: [PATCH 1/7 resend] drm/i915: Add the support of eDP on DP-D for Ibex/CPT

Quoted 12 lines · Zhenyu Wang

From: Zhao Yakui <[email protected]>

This one adds support for eDP that connected on PCH DP-D port instead of CPU DP-A port, and only DP-D port could be used for eDP.

https://bugs.freedesktop.org/show_bug.cgi?id=27220

Signed-off-by Zhao Yakui <[email protected]>
Tested-by Jan-Hendrik Zab <[email protected]>
Tested-by Templar <[email protected]>
Signed-off-by Zhenyu Wang <[email protected]>

---

[snip]

Quoted 4 lines

static void

drivers/gpu/drm/i915/intel_dp.c +1 -1
-intel_dp_compute_m_n(int bytes_per_pixel,
+intel_dp_compute_m_n(int bpp,
 		     int nlanes,

drivers/gpu/drm/i915/intel_dp.c intel_reduce_ratio(uint32_t *num, uint32_t *den) · line 558

Quoted 10 lines
drivers/gpu/drm/i915/intel_dp.c +1 -1
 		     int pixel_clock,
 		     int link_clock,
 		     struct intel_dp_m_n *m_n)
 {
 	m_n->tu = 64;
-	m_n->gmch_m = pixel_clock * bytes_per_pixel;
+	m_n->gmch_m = (pixel_clock * bpp) >> 3;
 	m_n->gmch_n = link_clock * nlanes;
 	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 	m_n->link_m = pixel_clock;

This rounds the gmch_m down. Is this correct? And how close to overflow is pixel_clock today?
-ickle

Signature · 1 line
Chris Wilson, Intel Open Source Technology Centre
#3 lore raw

Re: [PATCH 1/7 resend] drm/i915: Add the support of eDP on DP-D for Ibex/CPT

Quoted 23 lines · Chris Wilson
Quoted 12 lines · Zhenyu Wang

From: Zhao Yakui <[email protected]>

This one adds support for eDP that connected on PCH DP-D port instead of CPU DP-A port, and only DP-D port could be used for eDP.

https://bugs.freedesktop.org/show_bug.cgi?id=27220

Signed-off-by Zhao Yakui <[email protected]>
Tested-by Jan-Hendrik Zab <[email protected]>
Tested-by Templar <[email protected]>
Signed-off-by Zhenyu Wang <[email protected]>

---

[snip]

Quoted 9 lines

static void

drivers/gpu/drm/i915/intel_dp.c +1 -1
-intel_dp_compute_m_n(int bytes_per_pixel,
+intel_dp_compute_m_n(int bpp,
 		     int nlanes,
 		     int pixel_clock,
 		     int link_clock,
 		     struct intel_dp_m_n *m_n)
 {
 	m_n->tu = 64;
Quoted 8 lines

drivers/gpu/drm/i915/intel_dp.c intel_reduce_ratio(uint32_t *num, uint32_t *den) · line 558

Quoted 5 lines
drivers/gpu/drm/i915/intel_dp.c +1 -1
-	m_n->gmch_m = pixel_clock * bytes_per_pixel;
+	m_n->gmch_m = (pixel_clock * bpp) >> 3;
 	m_n->gmch_n = link_clock * nlanes;
 	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 	m_n->link_m = pixel_clock;

This rounds the gmch_m down. Is this correct? And how close to overflow is pixel_clock today?

The bpp is the abbreviation of bits per pixel and this is not round down. It is only to convert the bits per second to bytes per second, which will be used to calculation the DP M/N .

Quoted 2 lines

-ickle

#4 lore raw

Re: [PATCH 1/7 resend] drm/i915: Add the support of eDP on DP-D for Ibex/CPT

Quoted 21 lines · On Sun, 13 Jun 2010 09:06:32 +0800 ykzhao <[email protected]> wrote:
Quoted 11 lines · Chris Wilson
Quoted 10 lines · Zhenyu Wang

From: Zhao Yakui <[email protected]>
static void

drivers/gpu/drm/i915/intel_dp.c +1 -1
-intel_dp_compute_m_n(int bytes_per_pixel,
+intel_dp_compute_m_n(int bpp,
 		     int nlanes,
 		     int pixel_clock,
 		     int link_clock,
 		     struct intel_dp_m_n *m_n)
 {
 	m_n->tu = 64;
Quoted 8 lines

drivers/gpu/drm/i915/intel_dp.c intel_reduce_ratio(uint32_t *num, uint32_t *den) · line 558

Quoted 5 lines
drivers/gpu/drm/i915/intel_dp.c +1 -1
-	m_n->gmch_m = pixel_clock * bytes_per_pixel;
+	m_n->gmch_m = (pixel_clock * bpp) >> 3;
 	m_n->gmch_n = link_clock * nlanes;
 	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 	m_n->link_m = pixel_clock;

This rounds the gmch_m down. Is this correct? And how close to overflow is pixel_clock today?

Quoted 4 lines

The bpp is the abbreviation of bits per pixel and this is not round down. It is only to convert the bits per second to bytes per second, which will be used to calculation the DP M/N .

You do a bitshift which ignores any fractional part. So, for example, if pixel_clock*bpp == 7 is true, the result of (pixel_clock*bpp)>>3 would be 0. Wouldn't it?

So Chris' question if this is correct is still pending an answer.

It may be correct, but how did you decide what to do there?

Cheers,
Flo

#5 lore raw

Re: [PATCH 1/7 resend] drm/i915: Add the support of eDP on DP-D for Ibex/CPT

In reply to Chris Wilson
Quoted 17 lines · Chris Wilson
Quoted 4 lines · Zhenyu Wang

static void

drivers/gpu/drm/i915/intel_dp.c +1 -1
-intel_dp_compute_m_n(int bytes_per_pixel,
+intel_dp_compute_m_n(int bpp,
 		     int nlanes,

drivers/gpu/drm/i915/intel_dp.c intel_reduce_ratio(uint32_t *num, uint32_t *den) · line 558

Quoted 10 lines
drivers/gpu/drm/i915/intel_dp.c +1 -1
 		     int pixel_clock,
 		     int link_clock,
 		     struct intel_dp_m_n *m_n)
 {
 	m_n->tu = 64;
-	m_n->gmch_m = pixel_clock * bytes_per_pixel;
+	m_n->gmch_m = (pixel_clock * bpp) >> 3;
 	m_n->gmch_n = link_clock * nlanes;
 	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 	m_n->link_m = pixel_clock;

This rounds the gmch_m down. Is this correct?

It's not, though thanks to the magic of PLLs it's probably close enough. However...

Quoted 1 line

And how close to overflow is pixel_clock today?

% echo $(( (2 ** 31 - 1) / 24. ))
89478485.291666672

89MHz isn't even a single LVDS link. Looks like that math needs to be 64-bit.

- ajax

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author
#6 lore raw

Re: [PATCH 1/7 resend] drm/i915: Add the support of eDP on DP-D for Ibex/CPT

Quoted 22 lines · Adam Jackson
Quoted 17 lines · Chris Wilson
Quoted 4 lines · Zhenyu Wang

static void

drivers/gpu/drm/i915/intel_dp.c +1 -1
-intel_dp_compute_m_n(int bytes_per_pixel,
+intel_dp_compute_m_n(int bpp,
 		     int nlanes,

drivers/gpu/drm/i915/intel_dp.c intel_reduce_ratio(uint32_t *num, uint32_t *den) · line 558

Quoted 10 lines
drivers/gpu/drm/i915/intel_dp.c +1 -1
 		     int pixel_clock,
 		     int link_clock,
 		     struct intel_dp_m_n *m_n)
 {
 	m_n->tu = 64;
-	m_n->gmch_m = pixel_clock * bytes_per_pixel;
+	m_n->gmch_m = (pixel_clock * bpp) >> 3;
 	m_n->gmch_n = link_clock * nlanes;
 	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 	m_n->link_m = pixel_clock;

This rounds the gmch_m down. Is this correct?

It's not, though thanks to the magic of PLLs it's probably close enough. However...

Quoted 8 lines
Quoted 1 line

And how close to overflow is pixel_clock today?

% echo $(( (2 ** 31 - 1) / 24. ))
89478485.291666672

89MHz isn't even a single LVDS link. Looks like that math needs to be 64-bit.

Right, 64-bit math is needed for this like what has been done for FDI link.

Signature · 3 lines
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827

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[email protected]
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#7 lore raw

Re: [PATCH 1/7 resend] drm/i915: Add the support of eDP on DP-D for Ibex/CPT

In reply to Adam Jackson
Quoted 22 lines · Adam Jackson
Quoted 17 lines · Chris Wilson
Quoted 4 lines · Zhenyu Wang

static void

drivers/gpu/drm/i915/intel_dp.c +1 -1
-intel_dp_compute_m_n(int bytes_per_pixel,
+intel_dp_compute_m_n(int bpp,
 		     int nlanes,

drivers/gpu/drm/i915/intel_dp.c intel_reduce_ratio(uint32_t *num, uint32_t *den) · line 558

Quoted 10 lines
drivers/gpu/drm/i915/intel_dp.c +1 -1
 		     int pixel_clock,
 		     int link_clock,
 		     struct intel_dp_m_n *m_n)
 {
 	m_n->tu = 64;
-	m_n->gmch_m = pixel_clock * bytes_per_pixel;
+	m_n->gmch_m = (pixel_clock * bpp) >> 3;
 	m_n->gmch_n = link_clock * nlanes;
 	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 	m_n->link_m = pixel_clock;

This rounds the gmch_m down. Is this correct?

It's not, though thanks to the magic of PLLs it's probably close enough. However...

Quoted 7 lines
Quoted 1 line

And how close to overflow is pixel_clock today?

% echo $(( (2 ** 31 - 1) / 24. ))
89478485.291666672

89MHz isn't even a single LVDS link. Looks like that math needs to be 64-bit.

Yes. 64-bit math is required on the above scenario if the actual pixel clock is directly used.

But the pixel clock in code uses the KHz as the unit. E.g. If the actual pixel clock is 89000 KHz, then 89000 will be used for the calculation. In such case it seems that the 32-bit math is enough.

Thanks.
Yakui

Quoted 2 lines

- ajax

#8 lore raw

Re: [PATCH 1/7 resend] drm/i915: Add the support of eDP on DP-D for Ibex/CPT

In reply to Zhenyu Wang
Quoted 6 lines · Zhenyu Wang

From: Zhao Yakui <[email protected]>

This one adds support for eDP that connected on PCH DP-D port instead of CPU DP-A port, and only DP-D port could be used for eDP.

https://bugs.freedesktop.org/show_bug.cgi?id=27220

Instead of changing a ton of EDP checks to be EDP || PCH_EDP, why aren't you just setting the output type to edp when you detect that DPD is EDP?

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author
#9 lore raw

Re: [PATCH 1/7 resend] drm/i915: Add the support of eDP on DP-D for Ibex/CPT

Quoted 10 lines · Eric Anholt
Quoted 6 lines · Zhenyu Wang

From: Zhao Yakui <[email protected]>

This one adds support for eDP that connected on PCH DP-D port instead of CPU DP-A port, and only DP-D port could be used for eDP.

https://bugs.freedesktop.org/show_bug.cgi?id=27220

Instead of changing a ton of EDP checks to be EDP || PCH_EDP, why aren't you just setting the output type to edp when you detect that DPD is EDP?

There's obviously difference between eDP from CPU and eDP from PCH, e.g no FDI link setup for CPU eDP, so not fit in same output type. Or do you think a new output type might be better for it?

Signature · 3 lines
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827

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author
#10 lore raw

PATCH RESEND 2/7 drm/i915: Configure dither for eDP

In reply to Zhenyu Wang

From: Zhao Yakui <[email protected]>

The non-8 BPC can be used for the eDP output device that is connected through DP-A or DP-D on PCH. In such case we should set the PIPECONF dither correctly.

Signed-off-by Zhao Yakui <[email protected]>
Tested-by Jan-Hendrik Zab <[email protected]>
Signed-off-by Zhenyu Wang <[email protected]>
---
 drivers/gpu/drm/i915/intel_display.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)
drivers/gpu/drm/i915/intel_display.c +12 -0
index 7ffd51c..c757019 100644
@@ -3627,6 +3627,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 	/* setup pipeconf */
 	pipeconf = I915_READ(pipeconf_reg);
 
+	/* configure the dither for eDP */
+	if (HAS_PCH_SPLIT(dev) &&
+	    (is_edp || (is_dp && intel_pch_has_edp(crtc)))) {
+		pipeconf &= ~PIPE_DITHER_TYPE_MASK;
+		if ((pipeconf & PIPE_BPC_MASK) != PIPE_8BPC) {
+			pipeconf |= PIPE_ENABLE_DITHER;
+			pipeconf |= PIPE_DITHER_TYPE_ST01;
+		} else {
+			pipeconf &= ~PIPE_ENABLE_DITHER;
+		}
+	}
+
 	/* Set up the display plane register */
 	dspcntr = DISPPLANE_GAMMA_ENABLE;
Signature · 1 line
1.7.0.4
#11 lore raw

Re: [PATCH 2/7 resend] drm/i915: Configure dither for eDP

Quoted 5 lines · Zhenyu Wang

From: Zhao Yakui <[email protected]>

The non-8 BPC can be used for the eDP output device that is connected through DP-A or DP-D on PCH. In such case we should set the PIPECONF dither correctly.

So if I point my pipe at a 6bpp edp output, then back to my lovely DP monitor, it'll leave dithering in place on my monitor?

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#12 lore raw

Re: [PATCH 2/7 resend] drm/i915: Configure dither for eDP

In reply to Zhenyu Wang
Quoted 5 lines · Zhenyu Wang

From: Zhao Yakui <[email protected]>

The non-8 BPC can be used for the eDP output device that is connected through DP-A or DP-D on PCH. In such case we should set the PIPECONF dither correctly.

Applied all of this series but this one -- this patch still looks wrong to me.

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author
#13 lore raw

PATCH 3/7 drm/i915: Fix watermark calculation in self-refresh mode

In reply to Zhenyu Wang

From: Zhao Yakui <[email protected]>

For self-refresh mode WM calculation's "line time" should use mode's htotal instead of hdisplay. "surface width" is the hdisplay for display plane and 64 for cursor plane.

Signed-off-by Zhao Yakui <[email protected]>
Signed-off-by Zhenyu Wang <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.h      |    3 +-
 drivers/gpu/drm/i915/intel_display.c |   42 ++++++++++++++++++++-------------
 2 files changed, 27 insertions(+), 18 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +2 -1
index 9ed8ecd..70b6da1 100644
@@ -176,7 +176,8 @@ struct drm_i915_display_funcs {
 	int (*get_display_clock_speed)(struct drm_device *dev);
 	int (*get_fifo_size)(struct drm_device *dev, int plane);
 	void (*update_wm)(struct drm_device *dev, int planea_clock,
-			  int planeb_clock, int sr_hdisplay, int pixel_size);
+			  int planeb_clock, int sr_hdisplay, int sr_htotal,
+			  int pixel_size);
 	/* clock updates for mode set */
 	/* cursor updates */
 	/* render clock increase/decrease */
drivers/gpu/drm/i915/intel_display.c +25 -17

132 lines not on this page · raw message

Signature · 1 line
1.7.0.4
author
#14 lore raw

PATCH 4/7 drm/i915: Fix fifo size for self-refresh watermark on 965G

In reply to Zhenyu Wang

From: Zhao Yakui <[email protected]>

The total self-refresh fifo entry size for display plane is 512 instead of 128 for 965G. Also fix WM value mask for 965G.

About 1.0W power can be saved on one T61 laptop after the self-refresh watermark is configured correctly.

Signed-off-by Zhao Yakui <[email protected]>
Signed-off-by Zhenyu wang <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h      |    3 ++-
 drivers/gpu/drm/i915/intel_display.c |    4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +2 -1
index 64b0a3a..cf41c96 100644
@@ -2099,7 +2099,8 @@
 #define I830_FIFO_LINE_SIZE	32
 
 #define G4X_FIFO_SIZE		127
-#define I945_FIFO_SIZE		127 /* 945 & 965 */
+#define I965_FIFO_SIZE		512
+#define I945_FIFO_SIZE		127
 #define I915_FIFO_SIZE		95
 #define I855GM_FIFO_SIZE	127 /* In cachelines */
 #define I830_FIFO_SIZE		95
drivers/gpu/drm/i915/intel_display.c +2 -2
index 2c3377e..43e3710 100644
@@ -2969,10 +2969,10 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
 			      pixel_size * sr_hdisplay;
 		sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
 		DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
-		srwm = I945_FIFO_SIZE - sr_entries;
+		srwm = I965_FIFO_SIZE - sr_entries;
 		if (srwm < 0)
 			srwm = 1;
-		srwm &= 0x3f;
+		srwm &= 0x1ff;
 		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
 	} else {
 		/* Turn off self refresh if both pipes are enabled */
Signature · 1 line
1.7.0.4
author
#15 lore raw

PATCH 5/7 drm/i915: Apply self-refresh watermark calculation for cursor plane

In reply to Zhenyu Wang

From: Zhao Yakui <[email protected]>

In SR mode cursor plane watermark calculation uses same formula like display plane. This one fixes the case for 965G and G45.

Signed-off-by Zhao Yakui <[email protected]>
Signed-off-by Zhenyu Wang <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h      |    3 ++
 drivers/gpu/drm/i915/intel_display.c |   44 +++++++++++++++++++++++++++++++++-
 2 files changed, 46 insertions(+), 1 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +3 -0
index cf41c96..7c55212 100644
@@ -2119,6 +2119,9 @@
 #define PINEVIEW_CURSOR_DFT_WM	0
 #define PINEVIEW_CURSOR_GUARD_WM	5
 
+#define I965_CURSOR_FIFO	64
+#define I965_CURSOR_MAX_WM	32
+#define I965_CURSOR_DFT_WM	8
 
 /* define the Watermark register on Ironlake */
 #define WM0_PIPEA_ILK		0x45100
drivers/gpu/drm/i915/intel_display.c +43 -1

74 lines not on this page · raw message

Signature · 1 line
1.7.0.4
author
#16 lore raw

PATCH 6/7 drm/i915: Calculate cursor watermark under non-SR state for Ironlake

In reply to Zhenyu Wang

From: Zhao Yakui <[email protected]>

The hardware team suggest that the "large buffer" method should be used to calculate the cursor watermark under non-SR state as well, which is to avoid the flicker when FBC is enabled on Ironlake.

Signed-off-by Zhao Yakui <[email protected]>
Signed-off-by Zhenyu Wang <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h      |    3 ++
 drivers/gpu/drm/i915/intel_display.c |   56 ++++++++++++++++++++++++++++++++--
 2 files changed, 56 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +3 -0
index 7c55212..99b430a 100644
@@ -2149,6 +2149,9 @@
 #define ILK_DISPLAY_FIFO	128
 #define ILK_DISPLAY_MAXWM	64
 #define ILK_DISPLAY_DFTWM	8
+#define ILK_CURSOR_FIFO		32
+#define ILK_CURSOR_MAXWM	16
+#define ILK_CURSOR_DFTWM	8
 
 #define ILK_DISPLAY_SR_FIFO	512
 #define ILK_DISPLAY_MAX_SRWM	0x1ff
drivers/gpu/drm/i915/intel_display.c +53 -3

92 lines not on this page · raw message

Signature · 1 line
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author
#17 lore raw

PATCH 7/7 drm/i915: Add frame buffer compression support on Ironlake mobile

In reply to Zhenyu Wang

From: Zhao Yakui <[email protected]>

About 0.2W power can be saved on one HP laptop.

Signed-off-by Zhao Yakui <[email protected]>
Signed-off-by Zhenyu Wang <[email protected]>
---
 drivers/gpu/drm/i915/i915_dma.c      |    9 ++--
 drivers/gpu/drm/i915/i915_drv.c      |    2 +-
 drivers/gpu/drm/i915/i915_drv.h      |    1 +
 drivers/gpu/drm/i915/i915_reg.h      |   19 +++++++
 drivers/gpu/drm/i915/i915_suspend.c  |    9 +++-
 drivers/gpu/drm/i915/intel_display.c |   93 +++++++++++++++++++++++++++++++++-
 6 files changed, 125 insertions(+), 8 deletions(-)
drivers/gpu/drm/i915/i915_dma.c +5 -4
index 84ce956..293978d 100644
@@ -1254,7 +1254,7 @@ static void i915_setup_compression(struct drm_device *dev, int size)
 		drm_mm_put_block(compressed_fb);
 	}
 
-	if (!IS_GM45(dev)) {
+	if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
 		compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
 						    4096, 0);
 		if (!compressed_llb) {

@@ -1280,8 +1280,9 @@ static void i915_setup_compression(struct drm_device *dev, int size)
 
 	intel_disable_fbc(dev);
 	dev_priv->compressed_fb = compressed_fb;
-
-	if (IS_GM45(dev)) {
+	if (IS_IRONLAKE_M(dev))
+		I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
+	else if (IS_GM45(dev)) {
 		I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
 	} else {
 		I915_WRITE(FBC_CFB_BASE, cfb_base);

@@ -1289,7 +1290,7 @@ static void i915_setup_compression(struct drm_device *dev, int size)
 		dev_priv->compressed_llb = compressed_llb;
 	}
 
-	DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
+	DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
 		  ll_base, size >> 20);
 }
drivers/gpu/drm/i915/i915_drv.c +1 -1
index 423dc90..f4729d6 100644
@@ -134,7 +134,7 @@ static const struct intel_device_info intel_ironlake_d_info = {
 
 static const struct intel_device_info intel_ironlake_m_info = {
 	.is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
-	.need_gfx_hws = 1, .has_rc6 = 1,
+	.need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
 	.has_hotplug = 1,
 };
drivers/gpu/drm/i915/i915_drv.h +1 -0
index 70b6da1..c38e00a 100644
@@ -1040,6 +1040,7 @@ extern void intel_modeset_cleanup(struct drm_device *dev);
 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
 extern void i8xx_disable_fbc(struct drm_device *dev);
 extern void g4x_disable_fbc(struct drm_device *dev);
+extern void ironlake_disable_fbc(struct drm_device *dev);
 extern void intel_disable_fbc(struct drm_device *dev);
 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
 extern bool intel_fbc_enabled(struct drm_device *dev);
drivers/gpu/drm/i915/i915_reg.h +19 -0
index 99b430a..6906b45 100644
@@ -462,6 +462,21 @@
 #define DPFC_CHICKEN		0x3224
 #define   DPFC_HT_MODIFY	(1<<31)
 
+/* Framebuffer compression for Ironlake */
+#define ILK_DPFC_CB_BASE	0x43200
+#define ILK_DPFC_CONTROL	0x43208
+/* The bit 28-8 is reserved */
+#define   DPFC_RESERVED		(0x1FFFFF00)
+#define ILK_DPFC_RECOMP_CTL	0x4320c
+#define ILK_DPFC_STATUS		0x43210
+#define ILK_DPFC_FENCE_YOFF	0x43218
+#define ILK_DPFC_CHICKEN	0x43224
+#define ILK_FBC_RT_BASE		0x2128
+#define   ILK_FBC_RT_VALID	(1<<0)
+
+#define ILK_DISPLAY_CHICKEN1	0x42000
+#define   ILK_FBCQ_DIS		(1<<22)
+
 /*
  * GPIO regs
  */

@@ -2450,6 +2465,10 @@
 #define  ILK_VSDPFD_FULL	(1<<21)
 #define ILK_DSPCLK_GATE		0x42020
 #define  ILK_DPARB_CLK_GATE	(1<<5)
+/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
+#define   ILK_CLK_FBC		(1<<7)
+#define   ILK_DPFC_DIS1		(1<<8)
+#define   ILK_DPFC_DIS2		(1<<9)
 
 #define DISP_ARB_CTL	0x45000
 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
drivers/gpu/drm/i915/i915_suspend.c +7 -2
index 60a5800..6e20252 100644
@@ -602,7 +602,9 @@ void i915_save_display(struct drm_device *dev)
 
 	/* Only save FBC state on the platform that supports FBC */
 	if (I915_HAS_FBC(dev)) {
-		if (IS_GM45(dev)) {
+		if (IS_IRONLAKE_M(dev)) {
+			dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
+		} else if (IS_GM45(dev)) {
 			dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
 		} else {
 			dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);

@@ -706,7 +708,10 @@ void i915_restore_display(struct drm_device *dev)
 
 	/* only restore FBC info on the platform that supports FBC*/
 	if (I915_HAS_FBC(dev)) {
-		if (IS_GM45(dev)) {
+		if (IS_IRONLAKE_M(dev)) {
+			ironlake_disable_fbc(dev);
+			I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
+		} else if (IS_GM45(dev)) {
 			g4x_disable_fbc(dev);
 			I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
 		} else {
drivers/gpu/drm/i915/intel_display.c +92 -1

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1.7.0.4