PPC LBC/TLB cleanups; reginfo command for 85xx

index 9a40adc..524afa5 100644
@@ -36,6 +36,7 @@
 #define CONFIG_MPC8313ERDB	1
 
 #define CONFIG_PCI
+#define CONFIG_FSL_ELBC 1
 
 #define CONFIG_MISC_INIT_R
 

index 6972fe8..f1b110b 100644
@@ -197,6 +197,7 @@
 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
 #define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00040000
+#define CONFIG_FSL_ELBC		1
 
 /*
  * FLASH on the Local Bus

index b30d0e3..9092755 100644
@@ -223,6 +223,7 @@
 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
 #define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_FSL_ELBC		1
 
 /*
  * FLASH on the Local Bus

index 1654f46..79dadc4 100644
@@ -246,6 +246,7 @@
 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
 #define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_FSL_ELBC		1
 
 /*
  * FLASH on the Local Bus

index eb8657b..70b7489 100644
@@ -37,6 +37,7 @@
 #define CONFIG_MPC8313			1
 
 #define CONFIG_PCI
+#define CONFIG_FSL_ELBC			1
 
 #define CONFIG_MISC_INIT_R
 

index 7fd3668..20a6753 100644
@@ -47,6 +47,7 @@
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_FSL_ELBC		1
 
 /*
  * Multicore config

index b03a600..3ffdc9d 100644
@@ -83,17 +83,6 @@
 #define OHCI_CONTROL_INIT \
 	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
 
-/*
- * e.g. PCI controllers need this
- */
-#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-# define readl(a) __swap_32(*((volatile u32 *)(a)))
-# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
-#else
-# define readl(a) (*((volatile u32 *)(a)))
-# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
-#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
-
 #define min_t(type, x, y) \
 		    ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
 

index 79aa79d..fa4ecc8 100644
@@ -7,6 +7,19 @@
  * usb-ohci.h
  */
 
+/*
+ * e.g. PCI controllers need this
+ */
+#undef readl
+#undef writel
+#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+# define readl(a) __swap_32(*((volatile u32 *)(a)))
+# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
+#else
+# define readl(a) (*((volatile u32 *)(a)))
+# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
+#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
+
 /* functions for doing board or CPU specific setup/cleanup */
 extern int usb_board_init(void);
 extern int usb_board_stop(void);

index d3be909..24193ce 100644
@@ -156,16 +156,16 @@ int checkcpu(void)
 void upmconfig (uint upm, uint *table, uint size)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbus = &immap->lbus;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
 	volatile uchar *dummy = NULL;
 	const u32 msel = (upm + 4) << BR_MSEL_SHIFT;	/* What the MSEL field in BRn should be */
-	volatile u32 *mxmr = &lbus->mamr + upm;	/* Pointer to mamr, mbmr, or mcmr */
+	volatile u32 *mxmr = &lbc->mamr + upm;	/* ptr to mamr, mbmr, or mcmr */
 	uint i;
 
-	/* Scan all the banks to determine the base address of the device */
+	/* Find the address for the dummy write transaction */
 	for (i = 0; i < 8; i++) {
-		if ((lbus->bank[i].br & BR_MSEL) == msel) {
-			dummy = (uchar *) (lbus->bank[i].br & BR_BA);
+		if ((get_lbc_br(i) & BR_MSEL) == msel) {
+			dummy = (uchar *) (get_lbc_br(i) & BR_BA);
 			break;
 		}
 	}

@@ -179,7 +179,7 @@ void upmconfig (uint upm, uint *table, uint size)
 	*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
 
 	for (i = 0; i < size; i++) {
-		lbus->mdr = table[i];
+		lbc->mdr = table[i];
 		__asm__ __volatile__ ("sync");
 		*dummy = 0;	/* Write the value to memory and increment MAD */
 		__asm__ __volatile__ ("sync");

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index 38e141a..d1648b7 100644
@@ -88,8 +88,8 @@ void cpu_init_f (volatile immap_t * im)
 	&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
 	&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
 	&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
-	im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM;
-	im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM;
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
 	im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
 	im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
 #else

index 500eef1..a42c495 100644
@@ -388,7 +388,7 @@ int get_clocks(void)
 
 	lbiu_clk = csb_clk *
 	           (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
-	lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
+	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
 	switch (lcrr) {
 	case 2:
 	case 4:

index fddeb2f..4160b60 100644
@@ -257,8 +257,7 @@ void upmconfig (uint upm, uint * table, uint size)
 {
 	int i, mdr, mad, old_mad = 0;
 	volatile u32 *mxmr;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-	volatile u32 *brp,*orp;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile u8* dummy = NULL;
 	int upmmask;
 

@@ -281,12 +280,9 @@ void upmconfig (uint upm, uint * table, uint size)
 	}
 
 	/* Find the address for the dummy write transaction */
-	for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
-		 i++, brp += 2, orp += 2) {
-
-		/* Look for a valid BR with selected UPM */
-		if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
-			dummy = (volatile u8*)(in_be32(brp) & BR_BA);
+	for (i = 0; i < 8; i++) {
+		if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
+			dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA);
 			break;
 		}
 	}

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index 184cca4..8fb27ab 100644
@@ -25,7 +25,7 @@
 
 void cpu_init_f(void)
 {
-	ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	/*
 	 * LCRR - Clock Ratio Register - set up local bus timing

@@ -34,8 +34,8 @@ void cpu_init_f(void)
 	out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
 
 #if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
-	out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
-	out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
+	set_lbc_br(0, CONFIG_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_NAND_OR_PRELIM);
 #else
 #error  CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
 #endif

index 8132115..dd4c6b3 100644
@@ -172,10 +172,7 @@ void get_sys_info (sys_info_t * sysInfo)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
 #else
-	{
-	    volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-	    lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
-	}
+	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
 #endif
 	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
 #if defined(CONFIG_FSL_CORENET)

index 1887575..0fe94a0 100644
@@ -180,22 +180,9 @@ watchdog_reset(void)
  */
 void mpc86xx_reginfo(void)
 {
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	ccsr_lbc_t *lbc = &immap->im_lbc;
-
 	print_bats();
 	print_laws();
-
-	printf ("Local Bus Controller Registers\n"
-		"\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
-	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
-	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
-	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
-	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
-	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
-	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
-	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
-
+	print_lbc_regs();
 }
 
 /*

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index 64a3479..a2d0a8a 100644
@@ -97,10 +97,7 @@ void get_sys_info(sys_info_t *sysInfo)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
 #else
-	{
-		volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-		lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
-	}
+	lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
 #endif
 	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
 		sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);

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index fc3facb..f46816e 100644
@@ -76,4 +76,10 @@
 /* Relocation to SDRAM works on all PPC boards */
 #define CONFIG_RELOC_FIXUP_WORKS
 
+/* Since so many PPC SOCs have a semi-common LBC, define this here */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+	defined(CONFIG_MPC83xx)
+#define CONFIG_FSL_LBC
+#endif
+
 #endif /* _ASM_CONFIG_H_ */

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index 6b42a73..9353dc0 100644
@@ -635,7 +635,7 @@ typedef struct immap {
 	u8			res2[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res3[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res4[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */

@@ -675,7 +675,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */

@@ -710,7 +710,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */

@@ -755,7 +755,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */

@@ -805,7 +805,7 @@ typedef struct immap {
 	u8			res4[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res5[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res6[0x2000];
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */

@@ -844,7 +844,7 @@ typedef struct immap {
 	u8			res3[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res4[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res5[0x2000];
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */

@@ -868,6 +868,7 @@ typedef struct immap {
 #endif
 #define CONFIG_SYS_MPC83xx_USB_ADDR \
 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
+#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
 
 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
 #define CONFIG_SYS_MDIO1_OFFSET		0x24000

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index c11a5c3..4f7d935 100644
@@ -47,7 +47,7 @@ int board_early_init_f (void)
 int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 
 	if ((uint)&gur->porpllsr != 0xe00e0000) {

index b0ebad7..96698e7 100644
@@ -105,7 +105,7 @@ int misc_init_r()
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 
-	clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0);
+	clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
 
 	return 0;
 }

index 0c4fd68..7aede13 100644
@@ -110,7 +110,7 @@ static long fixed_sdram(void)
 phys_size_t initdram(int board_type)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc = &im->lbus;
+	volatile fsl_lbc_t *lbc = &im->im_lbc;
 	u32 msize;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)

index 61d1249..365ac37 100644
@@ -192,7 +192,7 @@ int checkboard (void)
 void sdram_init(void)
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc = &immap->lbus;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	/*

index 7da39f1..5647579 100644
@@ -221,15 +221,14 @@ int misc_init_f(void)
 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
 	};
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbus = &immap->lbus;
 
-	lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
-	lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 
 	/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
 	   GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
 	 */
-	lbus->mamr = 0x08404440;
+	immap->im_lbc.mamr = 0x08404440;
 
 	upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
 

index 4f55732..59ada9c 100644
@@ -280,7 +280,7 @@ int checkboard(void)
 static int sdram_init(unsigned int base)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc = &immap->lbus;
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
 	int rem = base % sdram_size;
 	uint *sdram_addr;

@@ -293,8 +293,8 @@ static int sdram_init(unsigned int base)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	immap->lbus.bank[2].br = base | CONFIG_SYS_BR2;
-	immap->lbus.bank[2].or = CONFIG_SYS_OR2;
+	set_lbc_br(2, base | CONFIG_SYS_BR2);
+	set_lbc_or(2, CONFIG_SYS_OR2);
 	immap->sysconf.lblaw[2].bar = base;
 	immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
 

index 9ffffb4..92d56a3 100644
@@ -82,9 +82,9 @@ static struct fsl_upm_nand fun = {
 
 int board_nand_init(struct nand_chip *nand)
 {
-	fun.upm.mxmr = &im->lbus.mamr;
-	fun.upm.mdr = &im->lbus.mdr;
-	fun.upm.mar = &im->lbus.mar;
+	fun.upm.mxmr = &im->im_lbc.mamr;
+	fun.upm.mdr = &im->im_lbc.mdr;
+	fun.upm.mar = &im->im_lbc.mar;
 
 	upm_setup(&fun.upm);
 

index 9e3f677..f9ff827 100644
@@ -117,7 +117,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -176,7 +176,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");

@@ -185,8 +185,8 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 

index c30d966..0580fe7 100644
@@ -291,7 +291,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -340,7 +340,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;

@@ -352,16 +352,11 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	asm("msync");
-
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
-	asm("msync");
-
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
-
 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");

index 0be2d89..581d5f2 100644
@@ -40,7 +40,7 @@
 int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	u8 vboot;
 	u8 *pixis_base = (u8 *)PIXIS_BASE;

index aa3f32b..f016995 100644
@@ -118,7 +118,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -154,7 +154,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;

@@ -166,16 +166,11 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	asm("msync");
-
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
-	asm("msync");
-
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
-
 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");

index ecddd0d..b7e0e0c 100644
@@ -291,7 +291,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -340,7 +340,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;

@@ -352,12 +352,8 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	asm("msync");
-
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
-	asm("msync");
-
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 

index 2bca0f2..489f90b 100644
@@ -322,7 +322,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -381,7 +381,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");

@@ -390,8 +390,8 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 

index 4ec13a9..036bf95 100644
@@ -181,7 +181,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -214,7 +214,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint lsdmr_common;
 

@@ -225,16 +225,13 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	asm("msync");
-
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	asm("msync");
 
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
-
 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");

index 1eddeef..81e8ff5 100644
@@ -308,7 +308,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

index 7c27233..054d644 100644
@@ -69,7 +69,7 @@ phys_size_t initdram (int board_type)
 	long dram_size = 0;
 
 #if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	sys_info_t sysinfo;
 	uint temp_lbcdll = 0;
 #endif

@@ -110,8 +110,8 @@ phys_size_t initdram (int board_type)
 		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 		asm("sync;isync;msync");
 	}
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 	asm("sync");

index 5353d73..a302b91 100644
@@ -134,7 +134,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

index b14a3d3..f9d92d9 100644
@@ -290,7 +290,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

index 34861d4..50fae7c 100644
@@ -160,7 +160,7 @@ int checkboard (void)
 void sdram_init(void)
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc = &immap->lbus;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("\n   SDRAM on Local Bus: ");

index 194f6ab..d62cfd1 100644
@@ -116,7 +116,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -152,7 +152,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint lsdmr_common;
 

@@ -163,22 +163,14 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
-	asm("msync");
-
-	out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
-	asm("msync");
-
-	out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
-	asm("msync");
-
-	out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
-	asm("msync");
+	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
+	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
 
 	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
 	asm("msync");
 
-
 	out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
 	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
 	asm("msync");

index c40b5e3..10ba62f 100644
@@ -269,7 +269,7 @@ phys_size_t initdram (int board_type)
 
 #if 0
 #if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	sys_info_t sysinfo;
 	uint temp_lbcdll = 0;
 #endif

@@ -310,8 +310,8 @@ phys_size_t initdram (int board_type)
 		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 		asm("sync;isync;msync");
 	}
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 	asm("sync");

index ebb70a2..ba59943 100644
@@ -129,7 +129,7 @@ void si_read_i2c(u32 lbyte, int count, u8 *buffer)
 phys_size_t initdram(int board_type)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc= &im->lbus;
+	volatile fsl_lbc_t *lbc = &im->im_lbc;
 	u32 msize;
 
 	if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)

index cb30b48..c2164c9 100644
@@ -93,7 +93,7 @@ int misc_init_r(void)
 {
 	int rc = 0;
 	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	fsl_lbus_t *lbus = &immap->lbus;
+	fsl_lbc_t *lbus = &immap->im_lbc;
 	u32 *mxmr = &lbus->mamr;	/* Pointer to mamr */
 
 	/* UPM Table Configuration Code */

index 9183c15..72e7401 100644
@@ -87,8 +87,6 @@ int checkboard (void)
 
 int misc_init_r (void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
 	/*
 	 * Adjust flash start and offset to detected values
 	 */

@@ -99,8 +97,10 @@ int misc_init_r (void)
 	 * Check if boot FLASH isn't max size
 	 */
 	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
-		memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
-		memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
+		set_lbc_or(0, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+		set_lbc_br(0, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
 
 		/*
 		 * Re-check to get correct base address

@@ -112,8 +112,8 @@ int misc_init_r (void)
 	 * Check if only one FLASH bank is available
 	 */
 	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
-		memctl->or1 = 0;
-		memctl->br1 = 0;
+		set_lbc_or(1, 0);
+		set_lbc_br(1, 0);
 
 		/*
 		 * Re-do flash protection upon new addresses

@@ -148,7 +148,7 @@ int misc_init_r (void)
  */
 void local_bus_init (void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	sys_info_t sysinfo;
 	uint clkdiv;

@@ -299,26 +299,25 @@ const gdc_regs *board_get_regs (void)
 
 int lime_probe(void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	uint cfg_br2;
 	uint cfg_or2;
 	int type;
 
-	cfg_br2 = memctl->br2;
-	cfg_or2 = memctl->or2;
+	cfg_br2 = get_lbc_br(2);
+	cfg_or2 = get_lbc_or(2);
 
 	/* Configure GPCM for CS2 */
-	memctl->br2 = 0;
-	memctl->or2 = 0xfc000410;
-	memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
+	set_lbc_br(2, 0);
+	set_lbc_or(2, 0xfc000410);
+	set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
 
 	/* Get controller type */
 	type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
 
 	/* Restore previous CS2 configuration */
-	memctl->br2 = 0;
-	memctl->or2 = cfg_or2;
-	memctl->br2 = cfg_br2;
+	set_lbc_br(2, 0);
+	set_lbc_or(2, cfg_or2);
+	set_lbc_br(2, cfg_br2);
 
 	return (type == MB862XX_TYPE_LIME) ? 1 : 0;
 }

index e564879..8d046f4 100644
@@ -253,10 +253,10 @@ static int detect_num_flash_banks(void)
 	debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
 
 	/* set OR0 and BR0 */
-	im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH |
-		(-(total_size) & OR_GPCM_AM);
-	im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) |
-		(BR_MS_GPCM | BR_PS_32 | BR_V);
+	set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
+		   (-(total_size) & OR_GPCM_AM));
+	set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
+		   (BR_MS_GPCM | BR_PS_32 | BR_V));
 
 	return (0);
 }

index 3da689a..4b16c31 100644
@@ -377,7 +377,7 @@ volatile const u32 *nand_upm_patt;
  */
 static void upmb_write (u_char addr, ulong val)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	out_be32 (&lbc->mdr, val);
 

@@ -393,14 +393,14 @@ static void upmb_write (u_char addr, ulong val)
 /*
  * Initialize UPM for NAND flash access.
  */
-static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
+static void nand_upm_setup (volatile fsl_lbc_t *lbc)
 {
 	uint i, j;
 	uint or3 = CONFIG_SYS_OR3_PRELIM;
 	uint clock = get_lbc_clock ();
 
-	out_be32 (&lbc->br3, 0);	/* disable bank and reset all bits */
-	out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_br(3, 0);	/* disable bank and reset all bits */
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
 
 	/*
 	 * Search appropriate UPM table for bus clock.

@@ -424,7 +424,7 @@ static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
 		/* EAD must be set due to TQM8548 timing specification */
 		or3 |= OR_UPM_EAD;
 
-	out_be32 (&lbc->or3, or3);
+	set_lbc_or(3, or3);
 
 	/* Assign address of table */
 	nand_upm_patt = upm_freq_table[i].upm_patt;

@@ -458,7 +458,7 @@ void board_nand_select_device (struct nand_chip *nand, int chip)
 
 int board_nand_init (struct nand_chip *nand)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	if (!nand_upm_patt)
 		nand_upm_setup (lbc);

index 8c9d586..fc2a6cb 100644
@@ -269,8 +269,6 @@ int checkboard (void)
 
 int misc_init_r (void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
 	/*
 	 * Adjust flash start and offset to detected values
 	 */

@@ -281,26 +279,27 @@ int misc_init_r (void)
 	 * Recalculate CS configuration if second FLASH bank is available
 	 */
 	if (flash_info[0].size > 0) {
-		memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
-			(CONFIG_SYS_OR1_PRELIM & 0x00007fff);
-		memctl->br1 = gd->bd->bi_flashstart |
-			(CONFIG_SYS_BR1_PRELIM & 0x00007fff);
+		set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
+			   (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
+		set_lbc_br(1, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
 		/*
 		 * Re-check to get correct base address for bank 1
 		 */
 		flash_get_size (gd->bd->bi_flashstart, 0);
 	} else {
-		memctl->or1 = 0;
-		memctl->br1 = 0;
+		set_lbc_or(1, 0);
+		set_lbc_br(1, 0);
 	}
 
 	/*
 	 *  If bank 1 is equipped, bank 0 is mapped after bank 1
 	 */
-	memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
-		(CONFIG_SYS_OR0_PRELIM & 0x00007fff);
-	memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
-		(CONFIG_SYS_BR0_PRELIM & 0x00007fff);
+	set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
+		   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+	set_lbc_br(0, gd->bd->bi_flashstart |
+		   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
+
 	/*
 	 * Re-check to get correct base address for bank 0
 	 */

@@ -341,7 +340,7 @@ int misc_init_r (void)
  */
 static void upmc_write (u_char addr, uint val)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	out_be32 (&lbc->mdr, val);
 

@@ -358,7 +357,7 @@ static void upmc_write (u_char addr, uint val)
 
 uint get_lbc_clock (void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	sys_info_t sys_info;
 	ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
 

@@ -386,7 +385,7 @@ uint get_lbc_clock (void)
 void local_bus_init (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint lbc_mhz = get_lbc_clock ()  / 1000000;
 
 #ifdef CONFIG_MPC8548

@@ -502,10 +501,10 @@ void local_bus_init (void)
 	 * set if Local Bus Clock is > 83 MHz.
 	 */
 	if (lbc_mhz > 83)
-		out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
+		set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
 	else
-		out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
-	out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
+		set_lbc_or(2, CONFIG_SYS_OR2_CAN);
+	set_lbc_br(2, CONFIG_SYS_BR2_CAN);
 
 	/* LGPL4 is UPWAIT */
 	out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);

index f4231a9..5822941 100644
@@ -56,8 +56,6 @@ int checkboard(void)
  */
 static void flash_cs_fixup(void)
 {
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	ccsr_lbc_t *lbc = &immap->im_lbc;
 	int flash_sel;
 
 	/*

@@ -70,11 +68,11 @@ static void flash_cs_fixup(void)
 	printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
 
 	if (flash_sel) {
-		out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
-		out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
 
-		out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
-		out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
 	}
 }
 

index 7109771..a2627f8 100644
@@ -38,7 +38,7 @@ extern void ft_board_pci_setup(void *blob, bd_t *bd);
 
 int checkboard(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	char *s;
 

@@ -65,7 +65,6 @@ int checkboard(void)
 
 static void flash_cs_fixup(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	int flash_sel;
 
 	/*

@@ -78,11 +77,11 @@ static void flash_cs_fixup(void)
 	printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
 
 	if (flash_sel) {
-		out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
-		out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
 
-		out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
-		out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
 	}
 }
 

index 48d9fc8..2a060c2 100644
@@ -58,7 +58,6 @@ int checkboard(void)
 
 static void flash_cs_fixup(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	int flash_sel;
 
 	/*

@@ -71,11 +70,11 @@ static void flash_cs_fixup(void)
 	printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
 
 	if (flash_sel) {
-		out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
-		out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
 
-		out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
-		out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
 	}
 }
 

index 146e9bf..acdb431 100644
@@ -75,7 +75,7 @@ struct fsl_elbc_ctrl {
 	struct fsl_elbc_mtd *chips[MAX_BANKS];
 
 	/* device info */
-	fsl_lbus_t *regs;
+	fsl_lbc_t *regs;
 	u8 __iomem *addr;        /* Address of assigned FCM buffer        */
 	unsigned int page;       /* Last page written to / read from      */
 	unsigned int read_bytes; /* Number of bytes read during command   */

@@ -171,7 +171,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 	int buf_num;
 
 	ctrl->page = page_addr;

@@ -211,7 +211,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 	long long end_tick;
 	u32 ltesr;
 

@@ -261,7 +261,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 
 	if (priv->page_size) {
 		out_be32(&lbc->fir,

@@ -295,7 +295,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 
 	ctrl->use_mdr = 0;
 

@@ -633,7 +633,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 
 	if (ctrl->status != LTESR_CC)
 		return NAND_STATUS_FAIL;

@@ -697,11 +697,7 @@ static void fsl_elbc_ctrl_init(void)
 	if (!elbc_ctrl)
 		return;
 
-#ifdef CONFIG_MPC85xx
-	elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
-#else
-	elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus;
-#endif
+	elbc_ctrl->regs = LBC_BASE_ADDR;
 
 	/* clear event registers */
 	out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);

index a4d4d65..2495b99 100644
@@ -6,8 +6,6 @@
 #ifndef	__MPC85xx_H__
 #define __MPC85xx_H__
 
-#include <asm/fsl_lbc.h>
-
 /* define for common ppc_asm.tmpl */
 #define EXC_OFF_SYS_RESET	0x100	/* System reset */
 #define _START_OFFSET		0

index af29dc2..5a0a0c7 100644
@@ -34,12 +34,11 @@ void board_init_f(ulong bootflag)
 	int px_spd;
 	u32 plat_ratio, bus_clk, sys_clk;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	ccsr_lbc_t *lbc = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
 
 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 	/* for FPGA */
-	out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
-	out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 #else
 #error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
 #endif

index ff47d55..9547d44 100644
@@ -32,7 +32,7 @@
 
 static void nand_wait(void)
 {
-	fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+	fsl_lbc_t *regs = LBC_BASE_ADDR;
 
 	for (;;) {
 		uint32_t status = in_be32(&regs->ltesr);

@@ -49,7 +49,7 @@ static void nand_wait(void)
 
 static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 {
-	fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+	fsl_lbc_t *regs = LBC_BASE_ADDR;
 	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
 	int large = in_be32(&regs->bank[0].or) & OR_FCM_PGS;
 	int block_shift = large ? 17 : 14;

index b3037ac..eebb6ae 100644
@@ -55,6 +55,24 @@ void init_tlbs(void)
 	return ;
 }
 
+void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
+		       phys_addr_t *rpn)
+{
+	u32 _mas1;
+
+	mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
+	asm volatile("tlbre;isync");
+	_mas1 = mfspr(MAS1);
+
+	*valid = (_mas1 & MAS1_VALID);
+	*tsize = (_mas1 >> 8) & 0xf;
+	*epn = mfspr(MAS2) & MAS2_EPN;
+	*rpn = mfspr(MAS3) & MAS3_RPN;
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+	*rpn |= ((u64)mfspr(MAS7)) << 32;
+#endif
+}
+
 #ifndef CONFIG_NAND_SPL
 static inline void use_tlb_cam(u8 idx)
 {

@@ -82,15 +100,9 @@ void init_used_tlb_cams(void)
 
 	/* walk all the entries */
 	for (i = 0; i < num_cam; i++) {
-		u32 _mas1;
-
 		mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
-
 		asm volatile("tlbre;isync");
-		_mas1 = mfspr(MAS1);
-
-		/* if the entry isn't valid skip it */
-		if ((_mas1 & MAS1_VALID))
+		if (mfspr(MAS1) & MAS1_VALID)
 			use_tlb_cam(i);
 	}
 }

@@ -134,7 +146,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
 
 #ifdef CONFIG_ADDR_MAP
 	if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
-		addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel);
+		addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
 #endif
 }
 

@@ -201,26 +213,12 @@ void init_addr_map(void)
 	/* walk all the entries */
 	for (i = 0; i < num_cam; i++) {
 		unsigned long epn;
-		u32 tsize, _mas1;
+		u32 tsize, valid;
 		phys_addr_t rpn;
 
-		mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
-
-		asm volatile("tlbre;isync");
-		_mas1 = mfspr(MAS1);
-
-		/* if the entry isn't valid skip it */
-		if (!(_mas1 & MAS1_VALID))
-			continue;
-
-		tsize = (_mas1 >> 8) & 0xf;
-		epn = mfspr(MAS2) & MAS2_EPN;
-		rpn = mfspr(MAS3) & MAS3_RPN;
-#ifdef CONFIG_ENABLE_36BIT_PHYS
-		rpn |= ((phys_addr_t)mfspr(MAS7)) << 32;
-#endif
-
-		addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i);
+		read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
+		if (valid & MAS1_VALID)
+			addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
 	}
 
 	return ;

index 5166507..d4c7b75 100644
@@ -402,6 +402,7 @@ extern void print_bats(void);
 #define MAS1_TID(x)	((x << 16) & 0x3FFF0000)
 #define MAS1_TS		0x00001000
 #define MAS1_TSIZE(x)	((x << 8) & 0x00000F00)
+#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10)))
 
 #define MAS2_EPN	0xFFFFF000
 #define MAS2_X0		0x00000040

index eebb6ae..f2833a5 100644
@@ -74,6 +74,26 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
 }
 
 #ifndef CONFIG_NAND_SPL
+void print_tlbcam(void)
+{
+	int i;
+	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
+
+	/* walk all the entries */
+	printf("TLBCAM entries\n");
+	for (i = 0; i < num_cam; i++) {
+		unsigned long epn;
+		u32 tsize, valid;
+		phys_addr_t rpn;
+
+		read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
+		printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:",
+			i, (valid == 0) ? 0 : 1, (unsigned int)epn,
+			(unsigned long long)rpn);
+		print_size(TSIZE_TO_BYTES(tsize), "\n");
+	}
+}
+
 static inline void use_tlb_cam(u8 idx)
 {
 	int i = idx / 32;

index d4c7b75..c01c85f 100644
@@ -486,6 +486,7 @@ extern void init_tlbs(void);
 extern int find_tlb_idx(void *addr, u8 tlbsel);
 extern void init_used_tlb_cams(void);
 extern int find_free_tlbcam(void);
+extern void print_tlbcam(void);
 
 extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
 

index 34c56a2..12ba1a6 100644
@@ -47,6 +47,7 @@ enum law_size {
 };
 
 #define law_size_bits(sz)	(__ilog2_u64(sz) - 1)
+#define lawar_size(x)	(1ULL << ((x & 0x3f) + 1))
 
 #ifdef CONFIG_FSL_CORENET
 enum law_trgt_if {

175 lines not on this page · raw message

index 9688888..628bd59 100644
@@ -193,7 +193,13 @@ void print_laws(void)
 	printf("\nLocal Access Window Configuration\n");
 	for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
 		lawar = in_be32(LAWAR_ADDR(i));
+#ifdef CONFIG_FSL_CORENET
+		printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
+		       i, in_be32(LAWBARH_ADDR(i)),
+		       i, in_be32(LAWBARL_ADDR(i)));
+#else
 		printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
+#endif
 		printf(" LAWAR0x%02d: 0x%08x\n", i, lawar);
 		printf("\t(EN: %d TGT: 0x%02x SIZE: ",
 		       (lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);

index 4160b60..7ab4a2a 100644
@@ -32,6 +32,8 @@
 #include <fsl_esdhc.h>
 #include <asm/cache.h>
 #include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -322,3 +324,14 @@ int cpu_mmc_init(bd_t *bis)
 	return 0;
 #endif
 }
+
+/*
+ * Print out the state of various machine registers.
+ * Currently prints out LAWs, BR0/OR0, and TLBs
+ */
+void mpc85xx_reginfo(void)
+{
+	print_tlbcam();
+	print_laws();
+	print_lbc_regs();
+}

index 89fd9ec..0fbe0b2 100644
@@ -33,6 +33,8 @@ extern void ppc4xx_reginfo(void);
 #include <mpc5xxx.h>
 #elif defined (CONFIG_MPC86xx)
 extern void mpc86xx_reginfo(void);
+#elif defined(CONFIG_MPC85xx)
+extern void mpc85xx_reginfo(void);
 #endif
 
 int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

@@ -183,6 +185,9 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #elif defined(CONFIG_MPC86xx)
 	mpc86xx_reginfo();
 
+#elif defined(CONFIG_MPC85xx)
+	mpc85xx_reginfo();
+
 #elif defined(CONFIG_BLACKFIN)
 	puts("\nSystem Configuration registers\n");
 

index da4313a..9c46d3e 100644
@@ -669,6 +669,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI

index 95ea275..7daf934 100644
@@ -294,6 +294,7 @@
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index e945da2..ae4fba8 100644
@@ -403,6 +403,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index 799d946..faba353 100644
@@ -420,6 +420,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index 3eb0049..fdd3597 100644
@@ -462,6 +462,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index 07a8e61..5011e5a 100644
@@ -401,6 +401,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index 4a4a9ed..98677e5 100644
@@ -416,6 +416,7 @@
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index 6973538..0cc2d47 100644
@@ -421,6 +421,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index 0c43b2b..bb7bb47 100644
@@ -539,6 +539,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index 78b7369..6038de1 100644
@@ -574,6 +574,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI

index a9b4004..926c774 100644
@@ -466,6 +466,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_NET

index 66be725..9bed161 100644
@@ -553,6 +553,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI

index 4b9bcca..7426bca 100644
@@ -326,6 +326,7 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index 1db20bc..0bd28fc 100644
@@ -325,6 +325,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index 1989e5a..5d424dd 100644
@@ -380,6 +380,7 @@
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index d44fb07..90abe14 100644
@@ -593,6 +593,7 @@
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_MII
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI

index 1a56c60..df5ef78 100644
@@ -338,6 +338,7 @@
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
 
 /*
  * Miscellaneous configurable options

index 20a6753..1d6091c 100644
@@ -397,6 +397,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
 
 /*
  * Miscellaneous configurable options

index aeac2de..3f4056e 100644
@@ -487,6 +487,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index dab4f80..53d06ed 100644
@@ -382,6 +382,7 @@
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index 89f7cc4..ad70109 100644
@@ -355,6 +355,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index 86b231c..891d2bf 100644
@@ -321,6 +321,7 @@
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_SYS_RAMBOOT)
     #undef CONFIG_CMD_SAVEENV

index 2783f9e..363f7b4 100644
@@ -353,6 +353,7 @@
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

index 24193ce..d37fc80 100644
@@ -125,72 +125,6 @@ int checkcpu(void)
 	return 0;
 }
 
-
-/*
- * Program a UPM with the code supplied in the table.
- *
- * The 'dummy' variable is used to increment the MAD. 'dummy' is
- * supposed to be a pointer to the memory of the device being
- * programmed by the UPM.  The data in the MDR is written into
- * memory and the MAD is incremented every time there's a write
- * to 'dummy'. Unfortunately, the current prototype for this
- * function doesn't allow for passing the address of this
- * device, and changing the prototype will break a number lots
- * of other code, so we need to use a round-about way of finding
- * the value for 'dummy'.
- *
- * The value can be extracted from the base address bits of the
- * Base Register (BR) associated with the specific UPM.  To find
- * that BR, we need to scan all 8 BRs until we find the one that
- * has its MSEL bits matching the UPM we want.  Once we know the
- * right BR, we can extract the base address bits from it.
- *
- * The MxMR and the BR and OR of the chosen bank should all be
- * configured before calling this function.
- *
- * Parameters:
- * upm: 0=UPMA, 1=UPMB, 2=UPMC
- * table: Pointer to an array of values to program
- * size: Number of elements in the array.  Must be 64 or less.
- */
-void upmconfig (uint upm, uint *table, uint size)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbc_t *lbc = &immap->im_lbc;
-	volatile uchar *dummy = NULL;
-	const u32 msel = (upm + 4) << BR_MSEL_SHIFT;	/* What the MSEL field in BRn should be */
-	volatile u32 *mxmr = &lbc->mamr + upm;	/* ptr to mamr, mbmr, or mcmr */
-	uint i;
-
-	/* Find the address for the dummy write transaction */
-	for (i = 0; i < 8; i++) {
-		if ((get_lbc_br(i) & BR_MSEL) == msel) {
-			dummy = (uchar *) (get_lbc_br(i) & BR_BA);
-			break;
-		}
-	}
-
-	if (!dummy) {
-		printf("Error: %s() could not find matching BR\n", __FUNCTION__);
-		hang();
-	}
-
-	/* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
-	*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
-
-	for (i = 0; i < size; i++) {
-		lbc->mdr = table[i];
-		__asm__ __volatile__ ("sync");
-		*dummy = 0;	/* Write the value to memory and increment MAD */
-		__asm__ __volatile__ ("sync");
-		while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
-	}
-
-	/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
-	*mxmr &= 0xCFFFFFC0;
-}
-
-
 int
 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {

67 lines not on this page · raw message

53 lines not on this page · raw message

index 33e6dd9..82d24ab 100644
@@ -62,6 +62,8 @@
 #define BR_V				0x00000001
 #define BR_V_SHIFT			0
 
+#define BR_UPMx_TO_MSEL(x)		((x + 4) << BR_MSEL_SHIFT)
+
 #define UPMA			0
 #define UPMB			1
 #define UPMC			2

@@ -458,6 +460,7 @@
 
 extern void print_lbc_regs(void);
 extern void init_early_memctl_regs(void);
+extern void upmconfig(uint upm, uint *table, uint size);
 
 #define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
 #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))

index b03a600..3f76c4e 100644
@@ -83,17 +83,6 @@
 #define OHCI_CONTROL_INIT \
 	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
 
-/*
- * e.g. PCI controllers need this
- */
-#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-# define readl(a) __swap_32(*((volatile u32 *)(a)))
-# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
-#else
-# define readl(a) (*((volatile u32 *)(a)))
-# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
-#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
-
 #define min_t(type, x, y) \
 		    ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
 

@@ -147,13 +136,13 @@ struct ohci_device ohci_dev;
 struct usb_device *devgone;
 
 static inline u32 roothub_a(struct ohci *hc)
-	{ return readl(&hc->regs->roothub.a); }
+	{ return ohci_readl(&hc->regs->roothub.a); }
 static inline u32 roothub_b(struct ohci *hc)
-	{ return readl(&hc->regs->roothub.b); }
+	{ return ohci_readl(&hc->regs->roothub.b); }
 static inline u32 roothub_status(struct ohci *hc)
-	{ return readl(&hc->regs->roothub.status); }
+	{ return ohci_readl(&hc->regs->roothub.status); }
 static inline u32 roothub_portstatus(struct ohci *hc, int i)
-	{ return readl(&hc->regs->roothub.portstatus[i]); }
+	{ return ohci_readl(&hc->regs->roothub.portstatus[i]); }
 
 /* forward declaration */
 static int hc_interrupt(void);

@@ -302,11 +291,11 @@ static void ohci_dump_status(ohci_t *controller)
 	struct ohci_regs	*regs = controller->regs;
 	__u32			temp;
 
-	temp = readl(&regs->revision) & 0xff;
+	temp = ohci_readl(&regs->revision) & 0xff;
 	if (temp != 0x10)
 		dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
 
-	temp = readl(&regs->control);
+	temp = ohci_readl(&regs->control);
 	dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
 		(temp & OHCI_CTRL_RWE) ? " RWE" : "",
 		(temp & OHCI_CTRL_RWC) ? " RWC" : "",

@@ -319,7 +308,7 @@ static void ohci_dump_status(ohci_t *controller)
 		temp & OHCI_CTRL_CBSR
 		);
 
-	temp = readl(&regs->cmdstatus);
+	temp = ohci_readl(&regs->cmdstatus);
 	dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
 		(temp & OHCI_SOC) >> 16,
 		(temp & OHCI_OCR) ? " OCR" : "",

@@ -328,18 +317,20 @@ static void ohci_dump_status(ohci_t *controller)
 		(temp & OHCI_HCR) ? " HCR" : ""
 		);
 
-	ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
-	ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
+	ohci_dump_intr_mask("intrstatus", ohci_readl(&regs->intrstatus));
+	ohci_dump_intr_mask("intrenable", ohci_readl(&regs->intrenable));
 
-	maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
+	maybe_print_eds("ed_periodcurrent",
+			ohci_readl(&regs->ed_periodcurrent));
 
-	maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
-	maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
+	maybe_print_eds("ed_controlhead", ohci_readl(&regs->ed_controlhead));
+	maybe_print_eds("ed_controlcurrent",
+			ohci_readl(&regs->ed_controlcurrent));
 
-	maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
-	maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
+	maybe_print_eds("ed_bulkhead", ohci_readl(&regs->ed_bulkhead));
+	maybe_print_eds("ed_bulkcurrent", ohci_readl(&regs->ed_bulkcurrent));
 
-	maybe_print_eds("donehead", readl(&regs->donehead));
+	maybe_print_eds("donehead", ohci_readl(&regs->donehead));
 }
 
 static void ohci_dump_roothub(ohci_t *controller, int verbose)

@@ -518,11 +509,11 @@ static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
 		/* implicitly requeued */
 		if (urb->dev->irq_handle &&
 				(urb->dev->irq_act_len = urb->actual_length)) {
-			writel(OHCI_INTR_WDH, &regs->intrenable);
-			readl(&regs->intrenable); /* PCI posting flush */
+			ohci_writel(OHCI_INTR_WDH, &regs->intrenable);
+			ohci_readl(&regs->intrenable); /* PCI posting flush */
 			urb->dev->irq_handle(urb->dev);
-			writel(OHCI_INTR_WDH, &regs->intrdisable);
-			readl(&regs->intrdisable); /* PCI posting flush */
+			ohci_writel(OHCI_INTR_WDH, &regs->intrdisable);
+			ohci_readl(&regs->intrdisable); /* PCI posting flush */
 		}
 		urb->actual_length = 0;
 		td_submit_job(

@@ -631,7 +622,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
 	case PIPE_CONTROL:
 		ed->hwNextED = 0;
 		if (ohci->ed_controltail == NULL)
-			writel(ed, &ohci->regs->ed_controlhead);
+			ohci_writel(ed, &ohci->regs->ed_controlhead);
 		else
 			ohci->ed_controltail->hwNextED =
 						   m32_swap((unsigned long)ed);

@@ -640,7 +631,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
 		if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
 			!ohci->ed_rm_list[1] && !ohci->sleeping) {
 			ohci->hc_control |= OHCI_CTRL_CLE;
-			writel(ohci->hc_control, &ohci->regs->control);
+			ohci_writel(ohci->hc_control, &ohci->regs->control);
 		}
 		ohci->ed_controltail = edi;
 		break;

@@ -648,7 +639,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
 	case PIPE_BULK:
 		ed->hwNextED = 0;
 		if (ohci->ed_bulktail == NULL)
-			writel(ed, &ohci->regs->ed_bulkhead);
+			ohci_writel(ed, &ohci->regs->ed_bulkhead);
 		else
 			ohci->ed_bulktail->hwNextED =
 						   m32_swap((unsigned long)ed);

@@ -657,7 +648,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
 		if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
 			!ohci->ed_rm_list[1] && !ohci->sleeping) {
 			ohci->hc_control |= OHCI_CTRL_BLE;
-			writel(ohci->hc_control, &ohci->regs->control);
+			ohci_writel(ohci->hc_control, &ohci->regs->control);
 		}
 		ohci->ed_bulktail = edi;
 		break;

@@ -725,9 +716,10 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi)
 		if (ed->ed_prev == NULL) {
 			if (!ed->hwNextED) {
 				ohci->hc_control &= ~OHCI_CTRL_CLE;
-				writel(ohci->hc_control, &ohci->regs->control);
+				ohci_writel(ohci->hc_control,
+					    &ohci->regs->control);
 			}
-			writel(m32_swap(*((__u32 *)&ed->hwNextED)),
+			ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
 				&ohci->regs->ed_controlhead);
 		} else {
 			ed->ed_prev->hwNextED = ed->hwNextED;

@@ -744,9 +736,10 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi)
 		if (ed->ed_prev == NULL) {
 			if (!ed->hwNextED) {
 				ohci->hc_control &= ~OHCI_CTRL_BLE;
-				writel(ohci->hc_control, &ohci->regs->control);
+				ohci_writel(ohci->hc_control,
+					    &ohci->regs->control);
 			}
-			writel(m32_swap(*((__u32 *)&ed->hwNextED)),
+			ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
 			       &ohci->regs->ed_bulkhead);
 		} else {
 			ed->ed_prev->hwNextED = ed->hwNextED;

@@ -923,7 +916,7 @@ static void td_submit_job(struct usb_device *dev, unsigned long pipe,
 
 		if (!ohci->sleeping) {
 			/* start bulk list */
-			writel(OHCI_BLF, &ohci->regs->cmdstatus);
+			ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus);
 		}
 		break;
 

@@ -949,7 +942,7 @@ static void td_submit_job(struct usb_device *dev, unsigned long pipe,
 
 		if (!ohci->sleeping) {
 			/* start Control list */
-			writel(OHCI_CLF, &ohci->regs->cmdstatus);
+			ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus);
 		}
 		break;
 

@@ -1224,13 +1217,13 @@ static unsigned char root_hub_str_index1[] =
 
 #define OK(x)			len = (x); break
 #ifdef DEBUG
-#define WR_RH_STAT(x)		{info("WR:status %#8x", (x)); writel((x), \
+#define WR_RH_STAT(x)		{info("WR:status %#8x", (x)); ohci_writel((x), \
 						&gohci.regs->roothub.status); }
 #define WR_RH_PORTSTAT(x)	{info("WR:portstatus[%d] %#8x", wIndex-1, \
-		(x)); writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); }
+	(x)); ohci_writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); }
 #else
-#define WR_RH_STAT(x)		writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x)	writel((x), \
+#define WR_RH_STAT(x)		ohci_writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x)	ohci_writel((x), \
 				    &gohci.regs->roothub.portstatus[wIndex-1])
 #endif
 #define RD_RH_STAT		roothub_status(&gohci)

@@ -1661,10 +1654,10 @@ static int hc_reset(ohci_t *ohci)
 		int timeout = 1000;
 
 		pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
-		writel(readl(base + EHCI_USBCMD_OFF) | EHCI_USBCMD_HCRESET,
-			base + EHCI_USBCMD_OFF);
+		base += EHCI_USBCMD_OFF;
+		ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base);
 
-		while (readl(base + EHCI_USBCMD_OFF) & EHCI_USBCMD_HCRESET) {
+		while (ohci_readl(base) & EHCI_USBCMD_HCRESET) {
 			if (timeout-- <= 0) {
 				printf("USB RootHub reset timed out!");
 				break;

@@ -1674,11 +1667,11 @@ static int hc_reset(ohci_t *ohci)
 	} else
 		printf("No EHCI func@%d index!\n", CONFIG_PCI_EHCI_DEVNO);
 #endif
-	if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
-		/* SMM owns the HC */
-		writel(OHCI_OCR, &ohci->regs->cmdstatus);/* request ownership */
+	if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
+		/* SMM owns the HC, request ownership */
+		ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus);
 		info("USB HC TakeOver from SMM");
-		while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
+		while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
 			wait_ms(10);
 			if (--smm_timeout == 0) {
 				err("USB HC TakeOver failed!");

@@ -1688,19 +1681,19 @@ static int hc_reset(ohci_t *ohci)
 	}
 
 	/* Disable HC interrupts */
-	writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
+	ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
 
 	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
 		ohci->slot_name,
-		readl(&ohci->regs->control));
+		ohci_readl(&ohci->regs->control));
 
 	/* Reset USB (needed by some controllers) */
 	ohci->hc_control = 0;
-	writel(ohci->hc_control, &ohci->regs->control);
+	ohci_writel(ohci->hc_control, &ohci->regs->control);
 
 	/* HC Reset requires max 10 us delay */
-	writel(OHCI_HCR,  &ohci->regs->cmdstatus);
-	while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
+	ohci_writel(OHCI_HCR,  &ohci->regs->cmdstatus);
+	while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
 		if (--timeout == 0) {
 			err("USB HC reset timed out!");
 			return -1;

@@ -1726,39 +1719,40 @@ static int hc_start(ohci_t *ohci)
 	/* Tell the controller where the control and bulk lists are
 	 * The lists are empty now. */
 
-	writel(0, &ohci->regs->ed_controlhead);
-	writel(0, &ohci->regs->ed_bulkhead);
+	ohci_writel(0, &ohci->regs->ed_controlhead);
+	ohci_writel(0, &ohci->regs->ed_bulkhead);
 
-	writel((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
+	ohci_writel((__u32)ohci->hcca,
+		    &ohci->regs->hcca); /* reset clears this */
 
 	fminterval = 0x2edf;
-	writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
+	ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
 	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
-	writel(fminterval, &ohci->regs->fminterval);
-	writel(0x628, &ohci->regs->lsthresh);
+	ohci_writel(fminterval, &ohci->regs->fminterval);
+	ohci_writel(0x628, &ohci->regs->lsthresh);
 
 	/* start controller operations */
 	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
 	ohci->disabled = 0;
-	writel(ohci->hc_control, &ohci->regs->control);
+	ohci_writel(ohci->hc_control, &ohci->regs->control);
 
 	/* disable all interrupts */
 	mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
 			OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
 			OHCI_INTR_OC | OHCI_INTR_MIE);
-	writel(mask, &ohci->regs->intrdisable);
+	ohci_writel(mask, &ohci->regs->intrdisable);
 	/* clear all interrupts */
 	mask &= ~OHCI_INTR_MIE;
-	writel(mask, &ohci->regs->intrstatus);
+	ohci_writel(mask, &ohci->regs->intrstatus);
 	/* Choose the interrupts we care about now  - but w/o MIE */
 	mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
-	writel(mask, &ohci->regs->intrenable);
+	ohci_writel(mask, &ohci->regs->intrenable);
 
 #ifdef	OHCI_USE_NPS
 	/* required for AMD-756 and some Mac platforms */
-	writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
+	ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
 		&ohci->regs->roothub.a);
-	writel(RH_HS_LPSC, &ohci->regs->roothub.status);
+	ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status);
 #endif	/* OHCI_USE_NPS */
 
 #define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })

@@ -1792,13 +1786,13 @@ static int hc_interrupt(void)
 				!(m32_swap(ohci->hcca->done_head) & 0x01)) {
 		ints =  OHCI_INTR_WDH;
 	} else {
-		ints = readl(&regs->intrstatus);
+		ints = ohci_readl(&regs->intrstatus);
 		if (ints == ~(u32)0) {
 			ohci->disabled++;
 			err("%s device removed!", ohci->slot_name);
 			return -1;
 		} else {
-			ints &= readl(&regs->intrenable);
+			ints &= ohci_readl(&regs->intrenable);
 			if (ints == 0) {
 				dbg("hc_interrupt: returning..\n");
 				return 0xff;

@@ -1833,16 +1827,16 @@ static int hc_interrupt(void)
 
 	if (ints & OHCI_INTR_WDH) {
 		wait_ms(1);
-		writel(OHCI_INTR_WDH, &regs->intrdisable);
-		(void)readl(&regs->intrdisable); /* flush */
+		ohci_writel(OHCI_INTR_WDH, &regs->intrdisable);
+		(void)ohci_readl(&regs->intrdisable); /* flush */
 		stat = dl_done_list(&gohci);
-		writel(OHCI_INTR_WDH, &regs->intrenable);
-		(void)readl(&regs->intrdisable); /* flush */
+		ohci_writel(OHCI_INTR_WDH, &regs->intrenable);
+		(void)ohci_readl(&regs->intrdisable); /* flush */
 	}
 
 	if (ints & OHCI_INTR_SO) {
 		dbg("USB Schedule overrun\n");
-		writel(OHCI_INTR_SO, &regs->intrenable);
+		ohci_writel(OHCI_INTR_SO, &regs->intrenable);
 		stat = -1;
 	}
 

@@ -1850,13 +1844,13 @@ static int hc_interrupt(void)
 	if (ints & OHCI_INTR_SF) {
 		unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
 		wait_ms(1);
-		writel(OHCI_INTR_SF, &regs->intrdisable);
+		ohci_writel(OHCI_INTR_SF, &regs->intrdisable);
 		if (ohci->ed_rm_list[frame] != NULL)
-			writel(OHCI_INTR_SF, &regs->intrenable);
+			ohci_writel(OHCI_INTR_SF, &regs->intrenable);
 		stat = 0xff;
 	}
 
-	writel(ints, &regs->intrstatus);
+	ohci_writel(ints, &regs->intrstatus);
 	return stat;
 }
 

index 79aa79d..d977e8f 100644
@@ -7,6 +7,17 @@
  * usb-ohci.h
  */
 
+/*
+ * e.g. PCI controllers need this
+ */
+#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+# define ohci_readl(a) __swap_32(*((volatile u32 *)(a)))
+# define ohci_writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
+#else
+# define ohci_readl(a) (*((volatile u32 *)(a)))
+# define ohci_writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
+#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
+
 /* functions for doing board or CPU specific setup/cleanup */
 extern int usb_board_init(void);
 extern int usb_board_stop(void);

@@ -196,8 +207,8 @@ struct ohci_hcca {
 
 /*
  * This is the structure of the OHCI controller's memory mapped I/O
- * region.  This is Memory Mapped I/O.	You must use the readl() and
- * writel() macros defined in asm/io.h to access these!!
+ * region.  This is Memory Mapped I/O.	You must use the ohci_readl() and
+ * ohci_writel() macros defined in this file to access these!!
  */
 struct ohci_regs {
 	/* control and status registers */