Add support for TI OMAP4 SDP and Panda

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/cpu.c
rename to arch/arm/cpu/armv7/cpu.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/clock.c
rename to arch/arm/cpu/armv7/mx51/clock.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/iomux.c
rename to arch/arm/cpu/armv7/mx51/iomux.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/soc.c
rename to arch/arm/cpu/armv7/mx51/soc.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/speed.c
rename to arch/arm/cpu/armv7/mx51/speed.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/timer.c
rename to arch/arm/cpu/armv7/mx51/timer.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/board.c
rename to arch/arm/cpu/armv7/omap3/board.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/clock.c
rename to arch/arm/cpu/armv7/omap3/clock.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/emif4.c
rename to arch/arm/cpu/armv7/omap3/emif4.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/gpio.c
rename to arch/arm/cpu/armv7/omap3/gpio.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/mem.c
rename to arch/arm/cpu/armv7/omap3/mem.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
rename to arch/arm/cpu/armv7/omap3/sdrc.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/sys_info.c
rename to arch/arm/cpu/armv7/omap3/sys_info.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/syslib.c
rename to arch/arm/cpu/armv7/omap3/syslib.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/timer.c
rename to arch/arm/cpu/armv7/omap3/timer.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c
rename to arch/arm/cpu/armv7/s5pc1xx/clock.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c
rename to arch/arm/cpu/armv7/s5pc1xx/cpu_info.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c
rename to arch/arm/cpu/armv7/s5pc1xx/sromc.c

similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c
rename to arch/arm/cpu/armv7/s5pc1xx/timer.c

index fbba412..afd2728 100644
@@ -1,5 +1,5 @@
 /*
- * needed for arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
+ * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S
  *
  * These should be auto-generated
  */

index 6455d1d..e9f6625 100644
@@ -46,7 +46,7 @@
 /*
  * This the the zoom2, board specific, gpmc configuration for the
  * quad uart on the debug board.   The more general gpmc configurations
- * are setup at the cpu level in arch/arm/cpu/arm_cortexa8/omap3/mem.c
+ * are setup at the cpu level in arch/arm/cpu/armv7/omap3/mem.c
  *
  * The details of the setting of the serial gpmc setup are not available.
  * The values were provided by another party.

index 513d005..10af21b 100644
@@ -28,7 +28,7 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
 #define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */

index 1076de6..2815771 100644
@@ -32,7 +32,7 @@
 #define __CONFIG_H
 
 /* High Level Configuration Options */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */

index e018b21..ae5a791 100644
@@ -31,7 +31,7 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */

index af7c65a..c4aa220 100644
@@ -36,7 +36,7 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */

index 9eba003..3308ace 100644
@@ -26,7 +26,7 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */

index d4482d3..5439aa3 100644
@@ -36,7 +36,7 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */

index 1e88dc0..f612e0f 100644
@@ -32,7 +32,7 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */

index be9daf4..aaf929e 100644
@@ -33,7 +33,7 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */

index 171ec94..ff0dbd3 100644
@@ -28,7 +28,7 @@
 #define __CONFIG_H
 
 /* High Level Configuration Options */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
 #define CONFIG_S5PC1XX		1	/* which is in a S5PC1XX Family */
 #define CONFIG_S5PC110		1	/* which is in a S5PC110 */

index 09bce6d..76a47c4 100644
@@ -32,7 +32,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
 #define CONFIG_S5PC1XX		1	/* which is in a S5PC1XX Family */
 #define CONFIG_S5PC100		1	/* which is in a S5PC100 */

similarity index 96%
rename from arch/arm/cpu/armv7/omap3/timer.c
rename to arch/arm/cpu/armv7/omap-common/timer.c
index 401bfe6..69e285f 100644
@@ -84,6 +84,11 @@ void set_timer(ulong t)
 /* delay x useconds */
 void __udelay(unsigned long usec)
 {
+#if defined(CONFIG_OMAP44XX)
+	/* TODO temporary hack until OMAP4 clock setup routines are present */
+	if (usec > 1000)
+		usec = usec/1000;
+#endif
 	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
 	unsigned long now, last = readl(&timer_base->tcrr);
 

90 lines not on this page · raw message

59 lines not on this page · raw message

94 lines not on this page · raw message

118 lines not on this page · raw message

similarity index 64%
rename from arch/arm/cpu/armv7/omap3/reset.S
rename to arch/arm/include/asm/arch-omap4/sys_proto.h
index a53c408..6f4d3d5 100644
@@ -1,9 +1,6 @@
 /*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang <[email protected]>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

@@ -21,16 +18,20 @@
  * MA 02111-1307 USA
  */
 
-#include <config.h>
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/arch/omap4.h>
+#include <asm/io.h>
+
+struct omap_sysinfo {
+	char *board_string;
+};
+
+void watchdog_init(void);
+u32 get_device_type(void);
+void invalidate_dcache(u32);
+
+extern const struct omap_sysinfo sysinfo;
 
-.global reset_cpu
-reset_cpu:
-	ldr	r1, rstctl			@ get addr for global reset
-						@ reg
-	mov	r3, #0x2			@ full reset pll + mpu
-	str	r3, [r1]			@ force reset
-	mov	r0, r0
-_loop_forever:
-	b	_loop_forever
-rstctl:
-	.word	PRM_RSTCTRL
+#endif

62 lines not on this page · raw message

175 lines not on this page · raw message

61 lines not on this page · raw message

174 lines not on this page · raw message

new file mode 100644
index 0000000..e5d8b53
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE	0x4809C100
+#define OMAP_HSMMC2_BASE	0x480B4100
+#define OMAP_HSMMC3_BASE	0x480AD100
+
+typedef struct hsmmc {
+	unsigned char res1[0x10];
+	unsigned int sysconfig;		/* 0x10 */
+	unsigned int sysstatus;		/* 0x14 */
+	unsigned char res2[0x14];
+	unsigned int con;		/* 0x2C */
+	unsigned char res3[0xD4];
+	unsigned int blk;		/* 0x104 */
+	unsigned int arg;		/* 0x108 */
+	unsigned int cmd;		/* 0x10C */
+	unsigned int rsp10;		/* 0x110 */
+	unsigned int rsp32;		/* 0x114 */
+	unsigned int rsp54;		/* 0x118 */
+	unsigned int rsp76;		/* 0x11C */
+	unsigned int data;		/* 0x120 */
+	unsigned int pstate;		/* 0x124 */
+	unsigned int hctl;		/* 0x128 */
+	unsigned int sysctl;		/* 0x12C */
+	unsigned int stat;		/* 0x130 */
+	unsigned int ie;		/* 0x134 */
+	unsigned char res4[0x8];
+	unsigned int capa;		/* 0x140 */
+} hsmmc_t;
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET			(0x1 << 1)
+#define RESETDONE			(0x1 << 0)
+#define NOOPENDRAIN			(0x0 << 0)
+#define OPENDRAIN			(0x1 << 0)
+#define OD				(0x1 << 0)
+#define INIT_NOINIT			(0x0 << 1)
+#define INIT_INITSTREAM			(0x1 << 1)
+#define HR_NOHOSTRESP			(0x0 << 2)
+#define STR_BLOCK			(0x0 << 3)
+#define MODE_FUNC			(0x0 << 4)
+#define DW8_1_4BITMODE			(0x0 << 5)
+#define MIT_CTO				(0x0 << 6)
+#define CDP_ACTIVEHIGH			(0x0 << 7)
+#define WPP_ACTIVEHIGH			(0x0 << 8)
+#define RESERVED_MASK			(0x3 << 9)
+#define CTPL_MMC_SD			(0x0 << 11)
+#define BLEN_512BYTESLEN		(0x200 << 0)
+#define NBLK_STPCNT			(0x0 << 16)
+#define DE_DISABLE			(0x0 << 0)
+#define BCE_DISABLE			(0x0 << 1)
+#define ACEN_DISABLE			(0x0 << 2)
+#define DDIR_OFFSET			(4)
+#define DDIR_MASK			(0x1 << 4)
+#define DDIR_WRITE			(0x0 << 4)
+#define DDIR_READ			(0x1 << 4)
+#define MSBS_SGLEBLK			(0x0 << 5)
+#define RSP_TYPE_OFFSET			(16)
+#define RSP_TYPE_MASK			(0x3 << 16)
+#define RSP_TYPE_NORSP			(0x0 << 16)
+#define RSP_TYPE_LGHT136		(0x1 << 16)
+#define RSP_TYPE_LGHT48			(0x2 << 16)
+#define RSP_TYPE_LGHT48B		(0x3 << 16)
+#define CCCE_NOCHECK			(0x0 << 19)
+#define CCCE_CHECK			(0x1 << 19)
+#define CICE_NOCHECK			(0x0 << 20)
+#define CICE_CHECK			(0x1 << 20)
+#define DP_OFFSET			(21)
+#define DP_MASK				(0x1 << 21)
+#define DP_NO_DATA			(0x0 << 21)
+#define DP_DATA				(0x1 << 21)
+#define CMD_TYPE_NORMAL			(0x0 << 22)
+#define INDEX_OFFSET			(24)
+#define INDEX_MASK			(0x3f << 24)
+#define INDEX(i)			(i << 24)
+#define DATI_MASK			(0x1 << 1)
+#define DATI_CMDDIS			(0x1 << 1)
+#define DTW_1_BITMODE			(0x0 << 1)
+#define DTW_4_BITMODE			(0x1 << 1)
+#define SDBP_PWROFF			(0x0 << 8)
+#define SDBP_PWRON			(0x1 << 8)
+#define SDVS_1V8			(0x5 << 9)
+#define SDVS_3V0			(0x6 << 9)
+#define ICE_MASK			(0x1 << 0)
+#define ICE_STOP			(0x0 << 0)
+#define ICS_MASK			(0x1 << 1)
+#define ICS_NOTREADY			(0x0 << 1)
+#define ICE_OSCILLATE			(0x1 << 0)
+#define CEN_MASK			(0x1 << 2)
+#define CEN_DISABLE			(0x0 << 2)
+#define CEN_ENABLE			(0x1 << 2)
+#define CLKD_OFFSET			(6)
+#define CLKD_MASK			(0x3FF << 6)
+#define DTO_MASK			(0xF << 16)
+#define DTO_15THDTO			(0xE << 16)
+#define SOFTRESETALL			(0x1 << 24)
+#define CC_MASK				(0x1 << 0)
+#define TC_MASK				(0x1 << 1)
+#define BWR_MASK			(0x1 << 4)
+#define BRR_MASK			(0x1 << 5)
+#define ERRI_MASK			(0x1 << 15)
+#define IE_CC				(0x01 << 0)
+#define IE_TC				(0x01 << 1)
+#define IE_BWR				(0x01 << 4)
+#define IE_BRR				(0x01 << 5)
+#define IE_CTO				(0x01 << 16)
+#define IE_CCRC				(0x01 << 17)
+#define IE_CEB				(0x01 << 18)
+#define IE_CIE				(0x01 << 19)
+#define IE_DTO				(0x01 << 20)
+#define IE_DCRC				(0x01 << 21)
+#define IE_DEB				(0x01 << 22)
+#define IE_CERR				(0x01 << 28)
+#define IE_BADA				(0x01 << 29)
+
+#define VS30_3V0SUP			(1 << 25)
+#define VS18_1V8SUP			(1 << 26)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE		512
+#define MMC_CARD			0
+#define SD_CARD				1
+#define BYTE_MODE			0
+#define SECTOR_MODE			1
+#define CLK_INITSEQ			0
+#define CLK_400KHZ			1
+#define CLK_MISC			2
+
+typedef struct {
+	unsigned int card_type;
+	unsigned int version;
+	unsigned int mode;
+	unsigned int size;
+	unsigned int RCA;
+} mmc_card_data;
+
+#define mmc_reg_out(addr, mask, val)\
+	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+#endif /* MMC_HOST_DEF_H */

index bf650ba..e97d817 100644
@@ -30,7 +30,8 @@
 #include <i2c.h>
 #include <twl4030.h>
 #include <asm/io.h>
-#include <asm/arch/mmc.h>
+
+#include "omap3_mmc.h"
 
 const unsigned short mmc_transspeed_val[15][4] = {
 	{CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)},

@@ -81,13 +82,14 @@ block_dev_desc_t *mmc_get_dev(int dev)
 
 unsigned char mmc_board_init(void)
 {
-	t2_t *t2_base = (t2_t *)T2_BASE;
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
 #if defined(CONFIG_TWL4030_POWER)
 	twl4030_power_mmc_init();
 #endif
 
+#if defined(CONFIG_OMAP34XX)
+	t2_t *t2_base = (t2_t *)T2_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
 	writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
 		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 		&t2_base->pbias_lite);

@@ -105,6 +107,9 @@ unsigned char mmc_board_init(void)
 	writel(readl(&prcm_base->iclken1_core) | 
 		EN_MMC1 | EN_MMC2 | EN_MMC3,
 		&prcm_base->iclken1_core);
+#endif
+
+/* TODO add appropriate OMAP4 init */
 
 	return 1;
 }

similarity index 99%
rename from arch/arm/include/asm/arch-omap3/mmc.h
rename to drivers/mmc/omap3_mmc.h
index 196ffdc..cbb3dc3 100644
@@ -25,7 +25,7 @@
 #ifndef MMC_H
 #define MMC_H
 
-#include "mmc_host_def.h"
+#include <asm/arch/mmc_host_def.h>
 
 /* Responses */
 #define RSP_TYPE_NONE	(RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)

index 07ab93f..3a14d34 100644
@@ -94,12 +94,23 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 
+/* MMC */
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_SYS_MMC_SET_DEV		1
+#define CONFIG_DOS_PARTITION		1
+
 /* Flash */
 #define CONFIG_SYS_NO_FLASH	1
 
 /* commands to include */
 #include <config_cmd_default.h>
 
+/* Enabled commands */
+#define CONFIG_CMD_EXT2		/* EXT2 Support                 */
+#define CONFIG_CMD_FAT		/* FAT support                  */
+#define CONFIG_CMD_MMC		/* MMC support                  */
+
 /* Disabled commands */
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_FPGA		/* FPGA configuration Support   */

@@ -121,6 +132,31 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
+	"mmcdev=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc init ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"fi"
 
 #define CONFIG_AUTO_COMPLETE		1
 

index 5b96b2e..9302ecb 100644
@@ -93,12 +93,23 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 
+/* MMC */
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_SYS_MMC_SET_DEV		1
+#define CONFIG_DOS_PARTITION		1
+
 /* Flash */
 #define CONFIG_SYS_NO_FLASH	1
 
 /* commands to include */
 #include <config_cmd_default.h>
 
+/* Enabled commands */
+#define CONFIG_CMD_EXT2		/* EXT2 Support                 */
+#define CONFIG_CMD_FAT		/* FAT support                  */
+#define CONFIG_CMD_MMC		/* MMC support                  */
+
 /* Disabled commands */
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_FPGA		/* FPGA configuration Support   */

@@ -120,6 +131,31 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
+	"mmcdev=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc init ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"fi"
 
 #define CONFIG_AUTO_COMPLETE		1
 

index 490e03b..7a4a73a 100644
@@ -20,9 +20,10 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-#ifndef _I2C_H_
-#define _I2C_H_
+#ifndef _OMAP3_I2C_H_
+#define _OMAP3_I2C_H_
 
+#define I2C_BUS_MAX	3
 #define I2C_DEFAULT_BASE	I2C_BASE1
 
 struct i2c {

@@ -58,146 +59,4 @@ struct i2c {
 	unsigned short res15;
 };
 
-#define I2C_BUS_MAX	3
-
-/* I2C masks */
-
-/* I2C Interrupt Enable Register (I2C_IE): */
-#define I2C_IE_GC_IE	(1 << 5)
-#define I2C_IE_XRDY_IE	(1 << 4) /* Transmit data ready interrupt enable */
-#define I2C_IE_RRDY_IE	(1 << 3) /* Receive data ready interrupt enable */
-#define I2C_IE_ARDY_IE	(1 << 2) /* Register access ready interrupt enable */
-#define I2C_IE_NACK_IE	(1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_IE_AL_IE	(1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Status Register (I2C_STAT): */
-
-#define I2C_STAT_SBD	(1 << 15) /* Single byte data */
-#define I2C_STAT_BB	(1 << 12) /* Bus busy */
-#define I2C_STAT_ROVR	(1 << 11) /* Receive overrun */
-#define I2C_STAT_XUDF	(1 << 10) /* Transmit underflow */
-#define I2C_STAT_AAS	(1 << 9)  /* Address as slave */
-#define I2C_STAT_GC	(1 << 5)
-#define I2C_STAT_XRDY	(1 << 4)  /* Transmit data ready */
-#define I2C_STAT_RRDY	(1 << 3)  /* Receive data ready */
-#define I2C_STAT_ARDY	(1 << 2)  /* Register access ready */
-#define I2C_STAT_NACK	(1 << 1)  /* No acknowledgment interrupt enable */
-#define I2C_STAT_AL	(1 << 0)  /* Arbitration lost interrupt enable */
-
-/* I2C Interrupt Code Register (I2C_INTCODE): */
-
-#define I2C_INTCODE_MASK	7
-#define I2C_INTCODE_NONE	0
-#define I2C_INTCODE_AL		1	/* Arbitration lost */
-#define I2C_INTCODE_NAK		2	/* No acknowledgement/general call */
-#define I2C_INTCODE_ARDY	3	/* Register access ready */
-#define I2C_INTCODE_RRDY	4	/* Rcv data ready */
-#define I2C_INTCODE_XRDY	5	/* Xmit data ready */
-
-/* I2C Buffer Configuration Register (I2C_BUF): */
-
-#define I2C_BUF_RDMA_EN		(1 << 15) /* Receive DMA channel enable */
-#define I2C_BUF_XDMA_EN		(1 << 7)  /* Transmit DMA channel enable */
-
-/* I2C Configuration Register (I2C_CON): */
-
-#define I2C_CON_EN	(1 << 15)  /* I2C module enable */
-#define I2C_CON_BE	(1 << 14)  /* Big endian mode */
-#define I2C_CON_STB	(1 << 11)  /* Start byte mode (master mode only) */
-#define I2C_CON_MST	(1 << 10)  /* Master/slave mode */
-#define I2C_CON_TRX	(1 << 9)   /* Transmitter/receiver mode */
-				   /* (master mode only) */
-#define I2C_CON_XA	(1 << 8)   /* Expand address */
-#define I2C_CON_STP	(1 << 1)   /* Stop condition (master mode only) */
-#define I2C_CON_STT	(1 << 0)   /* Start condition (master mode only) */
-
-/* I2C System Test Register (I2C_SYSTEST): */
-
-#define I2C_SYSTEST_ST_EN	(1 << 15) /* System test enable */
-#define I2C_SYSTEST_FREE	(1 << 14) /* Free running mode, on brkpoint) */
-#define I2C_SYSTEST_TMODE_MASK	(3 << 12) /* Test mode select */
-#define I2C_SYSTEST_TMODE_SHIFT	(12)	  /* Test mode select */
-#define I2C_SYSTEST_SCL_I	(1 << 3)  /* SCL line sense input value */
-#define I2C_SYSTEST_SCL_O	(1 << 2)  /* SCL line drive output value */
-#define I2C_SYSTEST_SDA_I	(1 << 1)  /* SDA line sense input value */
-#define I2C_SYSTEST_SDA_O	(1 << 0)  /* SDA line drive output value */
-
-#define I2C_SCLL_SCLL		0
-#define I2C_SCLL_SCLL_M		0xFF
-#define I2C_SCLL_HSSCLL		8
-#define I2C_SCLH_HSSCLL_M	0xFF
-#define I2C_SCLH_SCLH		0
-#define I2C_SCLH_SCLH_M		0xFF
-#define I2C_SCLH_HSSCLH		8
-#define I2C_SCLH_HSSCLH_M	0xFF
-
-#define OMAP_I2C_STANDARD	100000
-#define OMAP_I2C_FAST_MODE	400000
-#define OMAP_I2C_HIGH_SPEED	3400000
-
-#define SYSTEM_CLOCK_12		12000000
-#define SYSTEM_CLOCK_13		13000000
-#define SYSTEM_CLOCK_192	19200000
-#define SYSTEM_CLOCK_96		96000000
-
-/* Use the reference value of 96MHz if not explicitly set by the board */
-#ifndef I2C_IP_CLK
-#define I2C_IP_CLK		SYSTEM_CLOCK_96
-#endif
-
-/*
- * The reference minimum clock for high speed is 19.2MHz.
- * The linux 2.6.30 kernel uses this value.
- * The reference minimum clock for fast mode is 9.6MHz
- * The reference minimum clock for standard mode is 4MHz
- * In TRM, the value of 12MHz is used.
- */
-#ifndef I2C_INTERNAL_SAMPLING_CLK
-#define I2C_INTERNAL_SAMPLING_CLK	19200000
-#endif
-
-/*
- * The equation for the low and high time is
- * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
- * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
- *
- * If the duty cycle is 50%
- *
- * tlow = scll + scll_trim = sampling clock / (2 * speed)
- * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
- *
- * In TRM
- * scll_trim = 7
- * sclh_trim = 5
- *
- * The linux 2.6.30 kernel uses
- * scll_trim = 6
- * sclh_trim = 6
- *
- * These are the trim values for standard and fast speed
- */
-#ifndef I2C_FASTSPEED_SCLL_TRIM
-#define I2C_FASTSPEED_SCLL_TRIM		6
-#endif
-#ifndef I2C_FASTSPEED_SCLH_TRIM
-#define I2C_FASTSPEED_SCLH_TRIM		6
-#endif
-
-/* These are the trim values for high speed */
-#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
-#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
-#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
-#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
-#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
-#endif
-
-#define I2C_PSC_MAX		0x0f
-#define I2C_PSC_MIN		0x00
-
-#endif /* _I2C_H_ */
+#endif /* _OMAP3_I2C_H_ */

74 lines not on this page · raw message

index ff18991..3256133 100644
@@ -25,6 +25,8 @@
 #include <asm/arch/i2c.h>
 #include <asm/io.h>
 
+#include "omap24xx_i2c.h"
+
 static void wait_for_bb (void);
 static u16 wait_for_pin (void);
 static void flush_fifo(void);

@@ -176,7 +178,8 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
 
 		status = wait_for_pin ();
 		if (status & I2C_STAT_RRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+    defined(CONFIG_OMAP44XX)
 			*value = readb (&i2c_base->data);
 #else
 			*value = readw (&i2c_base->data);

@@ -221,7 +224,8 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
 	status = wait_for_pin ();
 
 	if (status & I2C_STAT_XRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+    defined(CONFIG_OMAP44XX)
 		/* send out 1 byte */
 		writeb (regoffset, &i2c_base->data);
 		writew (I2C_STAT_XRDY, &i2c_base->stat);

@@ -274,7 +278,8 @@ static void flush_fifo(void)
 	while(1){
 		stat = readw(&i2c_base->stat);
 		if(stat == I2C_STAT_RRDY){
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+    defined(CONFIG_OMAP44XX)
 			readb(&i2c_base->data);
 #else
 			readw(&i2c_base->data);

@@ -435,3 +440,9 @@ int i2c_set_bus_num(unsigned int bus)
 
 	return 0;
 }
+
+int i2c_get_bus_num(void)
+{
+	return (int) current_bus;
+}
+

58 lines not on this page · raw message

index 3a14d34..8121554 100644
@@ -94,6 +94,15 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 
+/* I2C  */
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_I2C_MULTI_BUS		1
+
 /* MMC */
 #define CONFIG_MMC			1
 #define CONFIG_OMAP3_MMC		1

@@ -109,6 +118,7 @@
 /* Enabled commands */
 #define CONFIG_CMD_EXT2		/* EXT2 Support                 */
 #define CONFIG_CMD_FAT		/* FAT support                  */
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support                  */
 
 /* Disabled commands */

index 9302ecb..a15c5f5 100644
@@ -93,6 +93,15 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 
+/* I2C  */
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_I2C_MULTI_BUS		1
+
 /* MMC */
 #define CONFIG_MMC			1
 #define CONFIG_OMAP3_MMC		1

@@ -108,6 +117,7 @@
 /* Enabled commands */
 #define CONFIG_CMD_EXT2		/* EXT2 Support                 */
 #define CONFIG_CMD_FAT		/* FAT support                  */
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support                  */
 
 /* Disabled commands */