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msm: Add gpiolib devices to MSM7x30 and QSD8x50.

PATCH Superseded Gregory Bean 5 participants 13 messages Jun 18, 2010 – Jun 21, 2010

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm Qualcomm mailing list

v1 of 3 Superseded Latest is v3 →

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Gregory Bean

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#0 lore raw

cover msm: Add gpiolib devices to MSM7x30 and QSD8x50.

Hi folks:

Here is a proposed patch series which adds the configuration and devices needed to enable gpiolib on the MSM7x30 and QSD8x50 chipsets.

Patch 1 adds the register mapping information for all supported MSM/QSD targets. I wasn't sure about adding register definitions for boards which weren't yet using those definitions, but the alternative was to have each following patch change gpio_hw.h over and over, so I put all the definitions in at once. Thoughts?

Patch 2 adds the first target, the 7x30, as well as some generic macros to ease the definition of the gpio devices and their platform data, as this is long-winded, but mindless and repetitive work. I considered putting the generic macro-definitions in their own patch, but without any targets to use them it seemed a little silly to leave them on their own and I ended up attaching them to the first patch to use them - what do y'all think? Does it warrant being split up?

Patch 3 adds device configuration for the 8x50.

Thanks,

G

Gregory Bean (3):
msm: Add gpio register address mapping information.
msm: 7x30: Add gpio device configuration.
msm: 8x50: add gpio device configuration.

 arch/arm/mach-msm/board-msm7x30.c     |   29 ++++++++-
 arch/arm/mach-msm/board-qsd8x50.c     |   29 ++++++++-
 arch/arm/mach-msm/devices-msm7x30.c   |   23 +++++++
 arch/arm/mach-msm/devices-qsd8x50.c   |   23 +++++++
 arch/arm/mach-msm/devices.h           |   35 ++++++++++
 arch/arm/mach-msm/gpio_hw-7x30.h      |  112 +++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio_hw-7xxx.h      |   97 ++++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio_hw-8x50.h      |  112 +++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio_hw.h           |   35 ++++++++++
 arch/arm/mach-msm/include/mach/gpio.h |    2 +
 10 files changed, 493 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-msm/gpio_hw-7x30.h
 create mode 100644 arch/arm/mach-msm/gpio_hw-7xxx.h
 create mode 100644 arch/arm/mach-msm/gpio_hw-8x50.h
 create mode 100644 arch/arm/mach-msm/gpio_hw.h

--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

author
#1 lore raw

PATCH 1/3 msm: Add gpio register address mapping information.

Signed-off-by Gregory Bean <[email protected]>
---
 arch/arm/mach-msm/gpio_hw-7x30.h |  112 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio_hw-7xxx.h |   97 +++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio_hw-8x50.h |  112 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio_hw.h      |   35 ++++++++++++
 4 files changed, 356 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/gpio_hw-7x30.h
 create mode 100644 arch/arm/mach-msm/gpio_hw-7xxx.h
 create mode 100644 arch/arm/mach-msm/gpio_hw-8x50.h
 create mode 100644 arch/arm/mach-msm/gpio_hw.h
arch/arm/mach-msm/gpio_hw-7x30.h new file +112 -0
new file mode 100644
index 0000000..cedd465
@@ -0,0 +1,112 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_7X30_H
+#define __ARCH_ARM_MACH_MSM_GPIO_HW_7X30_H
+
+/* output value */
+#define GPIO_OUT_0         GPIO1_REG(0x00)   /* gpio  15-0   */
+#define GPIO_OUT_1         GPIO2_REG(0x00)   /* gpio  43-16  */
+#define GPIO_OUT_2         GPIO1_REG(0x04)   /* gpio  67-44  */
+#define GPIO_OUT_3         GPIO1_REG(0x08)   /* gpio  94-68  */
+#define GPIO_OUT_4         GPIO1_REG(0x0C)   /* gpio 106-95  */
+#define GPIO_OUT_5         GPIO1_REG(0x50)   /* gpio 133-107 */
+#define GPIO_OUT_6         GPIO1_REG(0xC4)   /* gpio 150-134 */
+#define GPIO_OUT_7         GPIO1_REG(0x214)  /* gpio 181-151 */
+
+/* same pin map as above, output enable */
+#define GPIO_OE_0          GPIO1_REG(0x10)
+#define GPIO_OE_1          GPIO2_REG(0x08)
+#define GPIO_OE_2          GPIO1_REG(0x14)
+#define GPIO_OE_3          GPIO1_REG(0x18)
+#define GPIO_OE_4          GPIO1_REG(0x1C)
+#define GPIO_OE_5          GPIO1_REG(0x54)
+#define GPIO_OE_6          GPIO1_REG(0xC8)
+#define GPIO_OE_7          GPIO1_REG(0x218)
+
+/* same pin map as above, input read */
+#define GPIO_IN_0          GPIO1_REG(0x34)
+#define GPIO_IN_1          GPIO2_REG(0x20)
+#define GPIO_IN_2          GPIO1_REG(0x38)
+#define GPIO_IN_3          GPIO1_REG(0x3C)
+#define GPIO_IN_4          GPIO1_REG(0x40)
+#define GPIO_IN_5          GPIO1_REG(0x44)
+#define GPIO_IN_6          GPIO1_REG(0xCC)
+#define GPIO_IN_7          GPIO1_REG(0x21C)
+
+/* same pin map as above, 1=edge 0=level interrupt */
+#define GPIO_INT_EDGE_0    GPIO1_REG(0x60)
+#define GPIO_INT_EDGE_1    GPIO2_REG(0x50)
+#define GPIO_INT_EDGE_2    GPIO1_REG(0x64)
+#define GPIO_INT_EDGE_3    GPIO1_REG(0x68)
+#define GPIO_INT_EDGE_4    GPIO1_REG(0x6C)
+#define GPIO_INT_EDGE_5    GPIO1_REG(0xC0)
+#define GPIO_INT_EDGE_6    GPIO1_REG(0xD0)
+#define GPIO_INT_EDGE_7    GPIO1_REG(0x240)
+
+/* same pin map as above, 1=positive 0=negative */
+#define GPIO_INT_POS_0     GPIO1_REG(0x70)
+#define GPIO_INT_POS_1     GPIO2_REG(0x58)
+#define GPIO_INT_POS_2     GPIO1_REG(0x74)
+#define GPIO_INT_POS_3     GPIO1_REG(0x78)
+#define GPIO_INT_POS_4     GPIO1_REG(0x7C)
+#define GPIO_INT_POS_5     GPIO1_REG(0xBC)
+#define GPIO_INT_POS_6     GPIO1_REG(0xD4)
+#define GPIO_INT_POS_7     GPIO1_REG(0x228)
+
+/* same pin map as above, interrupt enable */
+#define GPIO_INT_EN_0      GPIO1_REG(0x80)
+#define GPIO_INT_EN_1      GPIO2_REG(0x60)
+#define GPIO_INT_EN_2      GPIO1_REG(0x84)
+#define GPIO_INT_EN_3      GPIO1_REG(0x88)
+#define GPIO_INT_EN_4      GPIO1_REG(0x8C)
+#define GPIO_INT_EN_5      GPIO1_REG(0xB8)
+#define GPIO_INT_EN_6      GPIO1_REG(0xD8)
+#define GPIO_INT_EN_7      GPIO1_REG(0x22C)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define GPIO_INT_CLEAR_0   GPIO1_REG(0x90)
+#define GPIO_INT_CLEAR_1   GPIO2_REG(0x68)
+#define GPIO_INT_CLEAR_2   GPIO1_REG(0x94)
+#define GPIO_INT_CLEAR_3   GPIO1_REG(0x98)
+#define GPIO_INT_CLEAR_4   GPIO1_REG(0x9C)
+#define GPIO_INT_CLEAR_5   GPIO1_REG(0xB4)
+#define GPIO_INT_CLEAR_6   GPIO1_REG(0xDC)
+#define GPIO_INT_CLEAR_7   GPIO1_REG(0x230)
+
+/* same pin map as above, 1=interrupt pending */
+#define GPIO_INT_STATUS_0  GPIO1_REG(0xA0)
+#define GPIO_INT_STATUS_1  GPIO2_REG(0x70)
+#define GPIO_INT_STATUS_2  GPIO1_REG(0xA4)
+#define GPIO_INT_STATUS_3  GPIO1_REG(0xA8)
+#define GPIO_INT_STATUS_4  GPIO1_REG(0xAC)
+#define GPIO_INT_STATUS_5  GPIO1_REG(0xB0)
+#define GPIO_INT_STATUS_6  GPIO1_REG(0xE0)
+#define GPIO_INT_STATUS_7  GPIO1_REG(0x234)
+
+#endif
arch/arm/mach-msm/gpio_hw-7xxx.h new file +97 -0

97 lines not on this page · raw message

arch/arm/mach-msm/gpio_hw-8x50.h new file +112 -0

112 lines not on this page · raw message

arch/arm/mach-msm/gpio_hw.h new file +35 -0
new file mode 100644
index 0000000..627dea5
@@ -0,0 +1,35 @@
+/* Copyright (c) 2007, Google, Inc.
+ * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H
+#define __ARCH_ARM_MACH_MSM_GPIO_HW_H
+
+#include <mach/msm_iomap.h>
+
+#if defined(CONFIG_ARCH_MSM7X30)
+#define GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
+#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
+#else
+#define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
+#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
+#endif
+
+#if defined(CONFIG_ARCH_QSD8X50)
+#include "gpio_hw-8x50.h"
+#elif defined(CONFIG_ARCH_MSM7X30)
+#include "gpio_hw-7x30.h"
+#else
+#include "gpio_hw-7xxx.h"
+#endif
+
+#endif
Signature · 5 lines
1.7.0.4

--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
#2 lore raw

Re: [PATCH 1/3] msm: Add gpio register address mapping information.

Hi!

Quoted 7 lines
arch/arm/mach-msm/gpio_hw-7x30.h new file +4 -0
@@ -0,0 +1,112 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are

arch/arm/mach-msm/gpio_hw-7x30.h line 14

Quoted 10 lines
arch/arm/mach-msm/gpio_hw-7x30.h new file +10 -0
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.

Yeah. Either this can be replaced with GPL, and it such case just do so, or it can not, and then it can not be applied to kernel.

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#3 lore raw

Re: [PATCH 1/3] msm: Add gpio register address mapping information.

Quoted 14 lines · Pavel Machek

Hi!

Quoted 12 lines
arch/arm/mach-msm/gpio_hw-7x30.h new file +9 -0
@@ -0,0 +1,112 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
Quoted 9 lines

arch/arm/mach-msm/gpio_hw-7x30.h line 14

Quoted 5 lines
arch/arm/mach-msm/gpio_hw-7x30.h new file +5 -0
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.

Yeah. Either this can be replaced with GPL, and it such case just do so, or it can not, and then it can not be applied to kernel.

This is a standard BSD-style license so it's compatible w/ the GPL. Thanks.

- Bryan

Signature · 2 lines
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
#4 lore raw

Re: [PATCH 1/3] msm: Add gpio register address mapping information.

Quoted 5 lines
Quoted 3 lines

Yeah. Either this can be replaced with GPL, and it such case just do so, or it can not, and then it can not be applied to kernel.

This is a standard BSD-style license so it's compatible w/ the GPL. Thanks.

The kernel requires GPL, and its much much easier for everyone to state so explicitly to avoid future surprises (remember 4 clause BSD was once thought GPL compatible even by the FSF...)

If you want to make it clear it's also available BSD licensed in this form (at least until someone changes it) see the wording in files like drivers/char/random.c

That usually keeps all the lawyers happy.

Alan

#5 lore raw

Re: [PATCH 1/3] msm: Add gpio register address mapping information.

Quoted 9 lines · Alan Cox
Quoted 4 lines
Quoted 3 lines

Yeah. Either this can be replaced with GPL, and it such case just do so, or it can not, and then it can not be applied to kernel.

This is a standard BSD-style license so it's compatible w/ the GPL. Thanks.

The kernel requires GPL, and its much much easier for everyone to state so explicitly to avoid future surprises (remember 4 clause BSD was once thought GPL compatible even by the FSF...)

Quoted 7 lines

If you want to make it clear it's also available BSD licensed in this form (at least until someone changes it) see the wording in files like drivers/char/random.c

That usually keeps all the lawyers happy.

Alan

Keeping the lawyers happy certainly has it's challenges. Is it uncommon to use just a BSD-style license for headers? I understand that everyone would prefer just GPL. I'm primarily curious about preserving BSD licensing for headers under /include. A dual license would work, but would it also be frowned upon to use just a 3-clause BSD license like we have in this patch? Thanks.

- Bryan

Signature · 2 lines
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
#6 lore raw

Re: [PATCH 1/3] msm: Add gpio register address mapping information.

Quoted 3 lines

licensing for headers under /include. A dual license would work, but would it also be frowned upon to use just a 3-clause BSD license like we have in this patch? Thanks.

The problem if it is only 3 clause BSD is what happens if somehow somewhere 3 clause BSD and GPL turn out to be incompatible. The easiest way to avoid that is to explicitly put it under both.

It's not likely to happen but its also easy to protect against

#7 lore raw

Re: [PATCH 1/3] msm: Add gpio register address mapping information.

In reply to Alan Cox
Quoted 10 lines · Alan Cox
Quoted 5 lines
Quoted 3 lines

Yeah. Either this can be replaced with GPL, and it such case just do so, or it can not, and then it can not be applied to kernel.

This is a standard BSD-style license so it's compatible w/ the GPL. Thanks.

The kernel requires GPL, and its much much easier for everyone to state so explicitly to avoid future surprises (remember 4 clause BSD was once thought GPL compatible even by the FSF...)

Quoted 5 lines

If you want to make it clear it's also available BSD licensed in this form (at least until someone changes it) see the wording in files like drivers/char/random.c

That usually keeps all the lawyers happy.

I guess this is a fairly confusing issues .. I found a number of regular BSD licenses in the kernel , many under include/linux/ ,

include/linux/nfs4_acl.h

in fact most of nfsd is BSD only, at least directly in the .c files. There could be some statement someplace else that I missed.

include/net/ieee80211_radiotap.h
include/linux/quota.h

Just structures ..

Is it possible that no code header files can be BSD only? From looking at the directory that is kind of what it looks like.

Daniel

Signature · 2 lines
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
#8 lore raw

Re: [PATCH 1/3] msm: Add gpio register address mapping information.

In reply to Bryan Huntsman
Quoted 25 lines · Bryan Huntsman
Quoted 14 lines · Pavel Machek

Hi!

Quoted 12 lines
arch/arm/mach-msm/gpio_hw-7x30.h new file +9 -0
@@ -0,0 +1,112 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
Quoted 9 lines

arch/arm/mach-msm/gpio_hw-7x30.h line 14

Quoted 5 lines
arch/arm/mach-msm/gpio_hw-7x30.h new file +5 -0
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.

Yeah. Either this can be replaced with GPL, and it such case just do so, or it can not, and then it can not be applied to kernel.

Quoted 2 lines

This is a standard BSD-style license so it's compatible w/ the GPL. Thanks.

Not good enough for kernel. Stop trying to push this.
Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#9 lore raw

PATCH 2/3 msm: 7x30: Add gpio device configuration.

In reply to Gregory Bean

Add device configuration and board-init for gpio on the MSM7x30.

Signed-off-by Gregory Bean <[email protected]>
---
 arch/arm/mach-msm/board-msm7x30.c     |   29 +++++++++++++++++++++++++-
 arch/arm/mach-msm/devices-msm7x30.c   |   23 +++++++++++++++++++++
 arch/arm/mach-msm/devices.h           |   35 +++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/gpio.h |    2 +
 4 files changed, 87 insertions(+), 2 deletions(-)
arch/arm/mach-msm/board-msm7x30.c +27 -2
index edd5983..f1ae525 100644
@@ -55,7 +55,31 @@ static void msm7x30_init_uart2(void)
 }
 #endif
 
-static struct platform_device *devices[] __initdata = {
+/*
+ * Early devices are those which provide a system service which will be
+ * required by one or more of the function calls in msm7x30_init.
+ * These devices must be probed and online first in order for
+ * the init routine to run successfully.
+ */
+static struct platform_device *early_devices[] __initdata = {
+#ifdef CONFIG_GPIOLIB
+	&msm_gpio_devices[0],
+	&msm_gpio_devices[1],
+	&msm_gpio_devices[2],
+	&msm_gpio_devices[3],
+	&msm_gpio_devices[4],
+	&msm_gpio_devices[5],
+	&msm_gpio_devices[6],
+	&msm_gpio_devices[7],
+#endif
+};
+
+/*
+ * Late devices are those which are dependent upon services initialized
+ * by msm7x30_init, or which simply have no dependents and can have
+ * their initialization deferred.
+ */
+static struct platform_device *late_devices[] __initdata = {
 #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
         &msm_device_uart2,
 #endif

@@ -69,10 +93,11 @@ static void __init msm7x30_init_irq(void)
 
 static void __init msm7x30_init(void)
 {
+	platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
 #ifdef CONFIG_SERIAL_MSM_CONSOLE
 	msm7x30_init_uart2();
 #endif
-	platform_add_devices(devices, ARRAY_SIZE(devices));
+	platform_add_devices(late_devices, ARRAY_SIZE(late_devices));
 }
 
 static void __init msm7x30_map_io(void)
arch/arm/mach-msm/devices-msm7x30.c +23 -0
index b449e8a..995b1f7 100644
@@ -126,3 +126,26 @@ struct clk msm_clocks_7x30[] = {
 
 unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30);
 
+#ifdef CONFIG_GPIOLIB
+static struct msm7200a_gpio_platform_data gpio_platform_data[] = {
+	MSM7200A_GPIO_PLATFORM_DATA(0,   0,  15, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(1,  16,  43, INT_GPIO_GROUP2),
+	MSM7200A_GPIO_PLATFORM_DATA(2,  44,  67, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(3,  68,  94, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(4,  95, 106, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(5, 107, 133, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(6, 134, 150, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(7, 151, 181, INT_GPIO_GROUP1),
+};
+
+struct platform_device msm_gpio_devices[] = {
+	MSM7200A_GPIO_DEVICE(0, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(1, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(2, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(3, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(4, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(5, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(6, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(7, gpio_platform_data),
+};
+#endif
arch/arm/mach-msm/devices.h +35 -0
index 568443e..321d4db 100644
@@ -17,6 +17,8 @@
 #define __ARCH_ARM_MACH_MSM_DEVICES_H
 
 #include "clock.h"
+#include "gpio_hw.h"
+#include "msm7200a-gpio.h"
 
 extern struct platform_device msm_device_uart1;
 extern struct platform_device msm_device_uart2;

@@ -44,4 +46,37 @@ extern unsigned msm_num_clocks_7x30;
 extern struct clk msm_clocks_8x50[];
 extern unsigned msm_num_clocks_8x50;
 
+#ifdef CONFIG_GPIOLIB
+#define MSM7200A_GPIO_PLATFORM_DATA(ix, begin, end, irq)		\
+	[ix] = {							\
+		.gpio_base		= begin,			\
+		.ngpio			= end - begin + 1,		\
+		.irq_base		= MSM_GPIO_TO_INT(begin),	\
+		.irq_summary		= irq,				\
+		.latch_level_irqs	= false,			\
+		.regs = {						\
+			.in		= GPIO_IN_ ## ix,		\
+			.out		= GPIO_OUT_ ## ix,		\
+			.oe		= GPIO_OE_ ## ix,		\
+			.int_status	= GPIO_INT_STATUS_ ## ix,	\
+			.int_clear	= GPIO_INT_CLEAR_ ## ix,	\
+			.int_en		= GPIO_INT_EN_ ## ix,		\
+			.int_edge	= GPIO_INT_EDGE_ ## ix,		\
+			.int_pos	= GPIO_INT_POS_ ## ix,		\
+		},							\
+	}
+
+#define MSM7200A_GPIO_DEVICE(ix, pdata)			\
+	{						\
+		.name		= "msm7200a-gpio",	\
+		.id		= ix,			\
+		.num_resources	= 0,			\
+		.dev = {				\
+			.platform_data = &pdata[ix],	\
+		},					\
+	}
+
+extern struct platform_device msm_gpio_devices[];
+#endif
+
 #endif
arch/arm/mach-msm/include/mach/gpio.h +2 -0
index 83e47c0..ff80758 100644
@@ -16,6 +16,8 @@
 #ifndef __ASM_ARCH_MSM_GPIO_H
 #define __ASM_ARCH_MSM_GPIO_H
 
+#define ARCH_NR_GPIOS 512
+
 #include <asm-generic/gpio.h>
 
 #define gpio_get_value  __gpio_get_value
Signature · 5 lines
1.7.0.4

--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
author
#10 lore raw

PATCH 3/3 msm: 8x50: add gpio device configuration.

In reply to Gregory Bean

Add device configuration and board-init for gpio support on the QSD8x50.

Signed-off-by Gregory Bean <[email protected]>
---
 arch/arm/mach-msm/board-qsd8x50.c   |   29 +++++++++++++++++++++++++++--
 arch/arm/mach-msm/devices-qsd8x50.c |   23 +++++++++++++++++++++++
 2 files changed, 50 insertions(+), 2 deletions(-)
arch/arm/mach-msm/board-qsd8x50.c +27 -2
index e3cc807..9137002 100644
@@ -40,7 +40,31 @@ static struct msm_gpio uart3_config_data[] = {
 	{ GPIO_CFG(87, 1, GPIO_OUTPUT,  GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"},
 };
 
-static struct platform_device *devices[] __initdata = {
+/*
+ * Early devices are those which provide a system service which will be
+ * required by one or more of the function calls in qsd8x50_init.
+ * These devices must be probed and online first in order for
+ * the init routine to run successfully.
+ */
+static struct platform_device *early_devices[] __initdata = {
+#ifdef CONFIG_GPIOLIB
+	&msm_gpio_devices[0],
+	&msm_gpio_devices[1],
+	&msm_gpio_devices[2],
+	&msm_gpio_devices[3],
+	&msm_gpio_devices[4],
+	&msm_gpio_devices[5],
+	&msm_gpio_devices[6],
+	&msm_gpio_devices[7],
+#endif
+};
+
+/*
+ * Late devices are those which are dependent upon services initialized
+ * by qsd8x50_init, or which simply have no dependents and can have
+ * their initialization deferred.
+ */
+static struct platform_device *late_devices[] __initdata = {
 	&msm_device_uart3,
 };
 

@@ -64,8 +88,9 @@ static void __init qsd8x50_init_irq(void)
 
 static void __init qsd8x50_init(void)
 {
+	platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
 	msm8x50_init_uart3();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
+	platform_add_devices(late_devices, ARRAY_SIZE(late_devices));
 }
 
 MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
arch/arm/mach-msm/devices-qsd8x50.c +23 -0
index 4d4a507..b9f692e 100644
@@ -90,3 +90,26 @@ struct clk msm_clocks_8x50[] = {
 
 unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
 
+#ifdef CONFIG_GPIOLIB
+static struct msm7200a_gpio_platform_data gpio_platform_data[] = {
+	MSM7200A_GPIO_PLATFORM_DATA(0,   0,  15, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(1,  16,  42, INT_GPIO_GROUP2),
+	MSM7200A_GPIO_PLATFORM_DATA(2,  43,  67, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(3,  68,  94, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(4,  95, 103, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(5, 104, 121, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(6, 122, 152, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(7, 153, 164, INT_GPIO_GROUP1),
+};
+
+struct platform_device msm_gpio_devices[] = {
+	MSM7200A_GPIO_DEVICE(0, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(1, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(2, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(3, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(4, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(5, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(6, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(7, gpio_platform_data),
+};
+#endif
Signature · 5 lines
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--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
#11 lore raw

Re: [PATCH 3/3] msm: 8x50: add gpio device configuration.

Quoted 15 lines · Gregory Bean

Add device configuration and board-init for gpio support on the QSD8x50.

Signed-off-by Gregory Bean <[email protected]>
---
 arch/arm/mach-msm/board-qsd8x50.c   |   29 +++++++++++++++++++++++++++--
 arch/arm/mach-msm/devices-qsd8x50.c |   23 +++++++++++++++++++++++
 2 files changed, 50 insertions(+), 2 deletions(-)
arch/arm/mach-msm/board-qsd8x50.c +0 -0
index e3cc807..9137002 100644
@@ -40,7 +40,31 @@ static struct msm_gpio uart3_config_data[] = {
 	{ GPIO_CFG(87, 1, GPIO_OUTPUT,  GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"},
 };

arch/arm/mach-msm/board-qsd8x50.c static struct msm_gpio uart3_config_data[] = { · line 50

Quoted 10 lines
arch/arm/mach-msm/board-qsd8x50.c +8 -1
 
-static struct platform_device *devices[] __initdata = {
+/*
+ * Early devices are those which provide a system service which will be
+ * required by one or more of the function calls in qsd8x50_init.
+ * These devices must be probed and online first in order for
+ * the init routine to run successfully.
+ */
+static struct platform_device *early_devices[] __initdata = {
+#ifdef CONFIG_GPIOLIB

We can drop the ifdefs I think , cause there's no off state anymore.

Quoted 36 lines
arch/arm/mach-msm/board-qsd8x50.c +19 -1
+	&msm_gpio_devices[0],
+	&msm_gpio_devices[1],
+	&msm_gpio_devices[2],
+	&msm_gpio_devices[3],
+	&msm_gpio_devices[4],
+	&msm_gpio_devices[5],
+	&msm_gpio_devices[6],
+	&msm_gpio_devices[7],
+#endif
+};
+
+/*
+ * Late devices are those which are dependent upon services initialized
+ * by qsd8x50_init, or which simply have no dependents and can have
+ * their initialization deferred.
+ */
+static struct platform_device *late_devices[] __initdata = {
 	&msm_device_uart3,
 };
 

@@ -64,8 +88,9 @@ static void __init qsd8x50_init_irq(void)
 
 static void __init qsd8x50_init(void)
 {
+	platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
 	msm8x50_init_uart3();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
+	platform_add_devices(late_devices, ARRAY_SIZE(late_devices));
 }
 
 MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
arch/arm/mach-msm/devices-qsd8x50.c +0 -0
index 4d4a507..b9f692e 100644

arch/arm/mach-msm/devices-qsd8x50.c struct clk msm_clocks_8x50[] = { · line 93

Quoted 4 lines
arch/arm/mach-msm/devices-qsd8x50.c +1 -0
@@ -90,3 +90,26 @@ struct clk msm_clocks_8x50[] = {
 
 unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
 
+#ifdef CONFIG_GPIOLIB

Any this one.

Quoted 22 lines
arch/arm/mach-msm/devices-qsd8x50.c +22 -0
+static struct msm7200a_gpio_platform_data gpio_platform_data[] = {
+	MSM7200A_GPIO_PLATFORM_DATA(0,   0,  15, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(1,  16,  42, INT_GPIO_GROUP2),
+	MSM7200A_GPIO_PLATFORM_DATA(2,  43,  67, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(3,  68,  94, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(4,  95, 103, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(5, 104, 121, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(6, 122, 152, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(7, 153, 164, INT_GPIO_GROUP1),
+};
+
+struct platform_device msm_gpio_devices[] = {
+	MSM7200A_GPIO_DEVICE(0, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(1, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(2, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(3, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(4, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(5, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(6, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(7, gpio_platform_data),
+};
+#endif
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
#12 lore raw
In reply to Gregory Bean
Quoted 19 lines · Gregory Bean

Hi folks:

Here is a proposed patch series which adds the configuration and devices needed to enable gpiolib on the MSM7x30 and QSD8x50 chipsets.

Patch 1 adds the register mapping information for all supported MSM/QSD targets. I wasn't sure about adding register definitions for boards which weren't yet using those definitions, but the alternative was to have each following patch change gpio_hw.h over and over, so I put all the definitions in at once. Thoughts?

Patch 2 adds the first target, the 7x30, as well as some generic macros to ease the definition of the gpio devices and their platform data, as this is long-winded, but mindless and repetitive work. I considered putting the generic macro-definitions in their own patch, but without any targets to use them it seemed a little silly to leave them on their own and I ended up attaching them to the first patch to use them - what do y'all think? Does it warrant being split up?

Quoted 1 line

Patch 3 adds device configuration for the 8x50.

Does it bisect?

Daniel

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