smp: parallel smp boot option

From: Steve Muckle <[email protected]>

Some SMP configurations start all available cores in parallel through the kernel entrypoint, rather than secondary CPUs waiting to be brought out of reset into machine specific startup code.

---
 arch/arm/Kconfig       |    9 +++++++++
 arch/arm/kernel/head.S |    3 +++
 2 files changed, 12 insertions(+), 0 deletions(-)

index 021b1d5..39103d2 100644
@@ -1020,6 +1020,15 @@ config NR_CPUS
 	depends on SMP
 	default "4"
 
+config SMP_PARALLEL_START
+	bool "Parallel start of SMP cores"
+	depends on SMP
+	default n
+	help
+	  Say Y here if all CPUs boot to the kernel entrypoint in
+	  parallel, rather than non-master CPUs waiting to be brought
+	  out of reset into machine specific startup code.
+
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
 	depends on SMP && HOTPLUG && EXPERIMENTAL

index 4946c72..9730b7a 100644
@@ -78,6 +78,9 @@
 ENTRY(stext)
 	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
 						@ and irqs disabled
+#ifdef CONFIG_SMP_PARALLEL_START
+	bl	__smp_secondary_spin
+#endif
 	mrc	p15, 0, r9, c0, c0		@ get processor id
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?

1.7.1

-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Yeah, I missed part of it. It was spread across two commits.. Also it's against 2.6.32 , so it may be partly out of date.

Daniel

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Your OK with this hook? I was thinking it might be better to check if it's the book cpu or the secondary here instead of in arch/arm/mach-msm .

Steve, do you have any thoughts on that?

Daniel

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Not entirely. It would appear that it means you can never used a compressed kernel on MSM, since if you do, you'll have all CPUs in the system decompressing the kernel simultaneously.

If we have to have this hook, how about making it a weak reference rather than something dealt with by the configuration system?

This is something we're using until we get a more complex/featureful bootchain in place. It probably only has value in development platforms/early enablement. A weak reference seems fine or we could drop it alltogether.

thanks,
Steve

--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

If we do keep the hook, I think it'd be better to leave it up to the platform specific code to do the test, in case for some reason it's not as simple as reading the MPIDR register. It also keeps the impact to head.S minimal.

thanks,
Steve

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

From: Steve Muckle <[email protected]>

Current MSM8X60 platforms boot all available cores into the kernel entrypoint in parallel.

---
Additional stuff needed to get the last smp patch working, "smp: parallel smp boot option".

 arch/arm/mach-msm/Makefile  |    2 +
 arch/arm/mach-msm/headsmp.S |   57 ++++++++++++++++++++++
 arch/arm/mach-msm/platsmp.c |  112 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 171 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/headsmp.S
 create mode 100644 arch/arm/mach-msm/platsmp.c

index 31719cd..df0b9ad 100644
@@ -24,6 +24,8 @@ ifdef CONFIG_ARCH_QSD8X50
 	obj-$(CONFIG_MSM_SOC_REV_A) += acpuclock-8x50a.o
 endif
 
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
+
 obj-$(CONFIG_MSM_CPU_AVS) += avs.o avs_hw.o
 obj-$(CONFIG_CPU_V6) += idle-v6.o
 obj-$(CONFIG_CPU_V7) += idle-v7.o

1.7.1