i915: fix ironlake edp panel setup.
Subsystems (2)
Dave Airlie
maintainerPATCH 1/1 i915: fix ironlake edp panel setup.
From: Dave Airlie <[email protected]>
We've just gotten an eDP laptop, and kms was booting to a black screen.
as much as I hate Keith's magic * 3, it seems to work a lot better than the non-magic.
aligning the non-magic seems to make things a lot happier, and aligns better with what the bios appears to do, since the bios ends up using thehigher clock in VGA mode.
--- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +1 -1
@@ -133,7 +133,7 @@ intel_dp_link_required(struct drm_device *dev,struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;if (IS_eDP (intel_encoder) ||IS_PCH_eDP (dp_priv)) -return (pixel_clock * dev_priv->edp_bpp) /8 ; +return (pixel_clock *ALIGN (dev_priv->edp_bpp,8 )) /8 ;else return pixel_clock *3 ; }
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1.7.1
Quoted 6 lines · Dave Airlie
From: Dave Airlie <[email protected]>
We've just gotten an eDP laptop, and kms was booting to a black screen.
as much as I hate Keith's magic * 3, it seems to work a lot better than the non-magic.
My *3 was based on the belief that we transmit 3 bytes for each pixel, independent of the pixel format. It worked pretty well for most of the sizes I tried...
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FWIW, this didn't seem solve the boot issue I'm seeing with the Dell E6410...
Quoted 21 lines · Keith Packard
Quoted 6 lines · Dave Airlie
From: Dave Airlie <[email protected]>
We've just gotten an eDP laptop, and kms was booting to a black screen.
as much as I hate Keith's magic * 3, it seems to work a lot better than the non-magic.
My *3 was based on the belief that we transmit 3 bytes for each pixel, independent of the pixel format. It worked pretty well for most of the sizes I tried...
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Quoted 19 lines · Dave Airlie
From: Dave Airlie <[email protected]>
We've just gotten an eDP laptop, and kms was booting to a black screen.
as much as I hate Keith's magic * 3, it seems to work a lot better than the non-magic.
aligning the non-magic seems to make things a lot happier, and aligns better with what the bios appears to do, since the bios ends up using thehigher clock in VGA mode.
Signed-off-by Dave Airlie <[email protected]>--- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)drivers/gpu/drm/i915/intel_dp.c +0
-0
drivers/gpu/drm/i915/intel_dp.c intel_dp_link_required(struct drm_device *dev, · line 139
Quoted 8 lines
drivers/gpu/drm/i915/intel_dp.c +1
-1@@ -133,7 +133,7 @@ intel_dp_link_required(struct drm_device *dev,struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;if (IS_eDP (intel_encoder) ||IS_PCH_eDP (dp_priv)) -return (pixel_clock * dev_priv->edp_bpp) /8 ; +return (pixel_clock *ALIGN (dev_priv->edp_bpp,8 )) /8 ;else return pixel_clock *3 ; }
Dave, we've found this breaks one 1600x900 eDP panel on our side, although it might fix other panels requiring high rate even low rate can fit.
Modeline 0:"1600x900" 0 107840 1600 1691 1752 1904 900 906 917 944 0x8 0x0
Clock is 107840khz, and the color depth is 18. Max number of lane from DPCD is 1. So with your change, it will exceed 2.7Ghz.
We've been told that we should try from highest config to lower ones until training can succeed, that seems the only stable way to get correct clock for eDP.
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Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
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Dave Airlie
maintainerQuoted 32 lines · Zhenyu Wang
Quoted 23 lines · Dave Airlie
From: Dave Airlie <[email protected]>
We've just gotten an eDP laptop, and kms was booting to a black screen.
as much as I hate Keith's magic * 3, it seems to work a lot better than the non-magic.
aligning the non-magic seems to make things a lot happier, and aligns better with what the bios appears to do, since the bios ends up using thehigher clock in VGA mode.
Signed-off-by Dave Airlie <[email protected]>---
drivers/gpu/drm/i915/intel_dp.c | 2 +-1 files changed, 1 insertions(+), 1 deletions(-)drivers/gpu/drm/i915/intel_dp.c +1
-1@@ -133,7 +133,7 @@ intel_dp_link_required(struct drm_device *dev, struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) - return (pixel_clock * dev_priv->edp_bpp) / 8; + return (pixel_clock * ALIGN(dev_priv->edp_bpp, 8)) / 8;Quoted 4 lines
else
returnpixel_clock* 3;
}
--Dave, we've found this breaks one 1600x900 eDP panel on our side, although it might fix other panels requiring high rate even low rate can fit.
Quoted 9 lines
Modeline 0:"1600x900" 0 107840 1600 1691 1752 1904 900 906 917 944
0x80x0Clock is 107840khz, and the color depth is 18. Max number of lane from DPCD is 1. So with your change, it will exceed 2.7Ghz.
We've been told that we should try from highest config to lower ones until training can succeed, that seems the only stable way to get correct clock for eDP.
Can you try the latest patch I send to the list?
it uses the overheads given in the eDP spec, but they should apply to normal DP as well.
Dave.