i915: fix ironlake edp panel setup (v3)
Subsystems (2)
Dave Airlie
maintainerPATCH 1/1 i915: fix ironlake edp panel setup (v3)
From: Dave Airlie <[email protected]>
The eDP spec claims a 20% overhead for the 8:10 encoding scheme used on the wire. Take this into account when picking the lane/clock speed for the panel.
v3: some panels are out of spec, try our best to deal with them, don't refuse modes on eDP panels, and try the largest allowed settings if all else fails on eDP.
Signed-off-by Dave Airlie <[email protected]>
--- drivers/gpu/drm/i915/intel_dp.c | 27 ++++++++++++++++++++++++--- 1 files changed, 24 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +24 -3
@@ -139,6 +139,12 @@ intel_dp_link_required(struct drm_device *dev, }static int +intel_dp_max_data_rate (int max_link_clock,int max_lanes) +{ +return (max_link_clock * max_lanes *8 ) /10 ; +} + +static int intel_dp_mode_valid (struct drm_connector *connector,struct drm_display_mode *mode) {
@@ -147,8 +153,11 @@ intel_dp_mode_valid(struct drm_connector *connector,int max_link_clock =intel_dp_link_clock (intel_dp_max_link_bw (intel_encoder));int max_lanes =intel_dp_max_lane_count (intel_encoder); -if (intel_dp_link_required (connector->dev, intel_encoder, mode->clock) - > max_link_clock * max_lanes) +/* only refuse the mode on non eDP since we have seen some wierd eDP panels +which are outside spec tolerances but somehow work by magic */ +if (!IS_eDP (intel_encoder) && + (dp_intel_dp_link_required (connector->dev, intel_encoder, mode->clock) + >intel_dp_max_data_rate (max_link_clock, max_lanes)))return MODE_CLOCK_HIGH ;if (mode->clock <10000 )
@@ -509,7 +518,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,for (lane_count =1 ; lane_count <= max_lane_count; lane_count <<=1 ) {for (clock =0 ; clock <= max_clock; clock++) { -int link_avail =intel_dp_link_clock (bws[clock]) * lane_count; +int link_avail =intel_dp_max_data_rate (intel_dp_link_clock (bws[clock]), lane_count);if (intel_dp_link_required (encoder->dev, intel_encoder, mode->clock) <= link_avail) {
@@ -524,6 +533,18 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, } } } + +if (IS_eDP (intel_encoder)) { +/* okay we failed just pick the highest */ + dp_priv->lane_count = max_lane_count; + dp_priv->link_bw = bws[max_clock]; + adjusted_mode->clock =intel_dp_link_clock (dp_priv->link_bw); +DRM_DEBUG_KMS ("Force picking display port link bw %02x lane " +"count %d clock %d\n" , + dp_priv->link_bw, dp_priv->lane_count, + adjusted_mode->clock); +return true; + }return false; }
Signature · 1 line
1.7.1
Dear Dave,
just a small typo.
Quoted 5 lines
drivers/gpu/drm/i915/intel_dp.c +0
-0@@ -139,6 +139,12 @@ intel_dp_link_required(struct drm_device *dev,
[…]
drivers/gpu/drm/i915/intel_dp.c intel_dp_mode_valid(struct drm_connector *connector, · line 156
Quoted 11 lines
drivers/gpu/drm/i915/intel_dp.c +2
-2+static int intel_dp_mode_valid (struct drm_connector *connector,struct drm_display_mode *mode) {@@ -147,8 +153,11 @@ intel_dp_mode_valid(struct drm_connector *connector,int max_link_clock =intel_dp_link_clock (intel_dp_max_link_bw (intel_encoder));int max_lanes =intel_dp_max_lane_count (intel_encoder); -if (intel_dp_link_required (connector->dev, intel_encoder, mode->clock) - > max_link_clock * max_lanes) +/* only refuse the mode on non eDP since we have seen some wierd eDP panels
s/wierd/weired/
[…]
Thanks,
Paul
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