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mtd: nand_plat: add simple GPIO framework DEV_READY option

PATCH New Mike Frysinger 3 participants 4 messages Jul 5, 2010 – Jul 9, 2010

Subsystems (2)
Memory technology devices (MTD) NAND flash
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Mike Frysinger

author
#0 lore raw

PATCH 1/2 mtd: nand_plat: add simple GPIO framework DEV_READY option

Make it easy to use GPIOs for the DEV_READY pin by using the common GPIO framework. Also make the NAND_PLAT_INIT() define optional.

Signed-off-by Mike Frysinger <[email protected]>
---
 drivers/mtd/nand/nand_plat.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)
drivers/mtd/nand/nand_plat.c +11 -0
index b35492b..37a0206 100644
@@ -16,6 +16,10 @@
 
 #include <common.h>
 #include <asm/io.h>
+#ifdef NAND_PLAT_GPIO_DEV_READY
+# include <asm/gpio.h>
+# define NAND_PLAT_DEV_READY(chip) gpio_get_value(NAND_PLAT_GPIO_DEV_READY)
+#endif
 
 #include <nand.h>
 

@@ -43,7 +47,14 @@ static int plat_dev_ready(struct mtd_info *mtd)
 
 int board_nand_init(struct nand_chip *nand)
 {
+#ifdef NAND_PLAT_GPIO_DEV_READY
+	gpio_request(NAND_PLAT_GPIO_DEV_READY, "nand-plat");
+	gpio_direction_input(NAND_PLAT_GPIO_DEV_READY);
+#endif
+
+#ifdef NAND_PLAT_INIT
 	NAND_PLAT_INIT();
+#endif
 
 	nand->cmd_ctrl = plat_cmd_ctrl;
 	nand->dev_ready = plat_dev_ready;
Signature · 1 line
1.7.1.1
author
#1 lore raw

PATCH 2/2 Blackfin: convert plat-nand code to GPIO framework

Use the new GPIO framework code in both the Blackfin arch and the nand_plat driver to simplify things greatly.

Signed-off-by Mike Frysinger <[email protected]>

---
note: i can run this through the Blackfin tree if you want

 include/configs/bf537-pnav.h    |    9 +--------
 include/configs/bf537-stamp.h   |    9 +--------
 include/configs/bf561-acvilon.h |    8 +-------
 include/configs/ip04.h          |   10 +---------
 4 files changed, 4 insertions(+), 32 deletions(-)
include/configs/bf537-pnav.h +1 -8
index 8daebc8..39bbb41 100644
@@ -132,7 +132,6 @@
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY     PF12
 #define BFIN_NAND_WRITE(addr, cmd) \
 	do { \
 		bfin_write8(addr, cmd); \

@@ -141,13 +140,7 @@
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_PORTHIO() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-	do { \
-		bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \
-		bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \
-		bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \
-	} while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF12
 
 
 /*
include/configs/bf537-stamp.h +1 -8
index 3592862..96704d7 100644
@@ -155,7 +155,6 @@
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY     PF3
 #define BFIN_NAND_WRITE(addr, cmd) \
 	do { \
 		bfin_write8(addr, cmd); \

@@ -164,13 +163,7 @@
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_PORTFIO() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-	do { \
-		bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \
-		bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \
-		bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | BFIN_NAND_READY); \
-	} while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
 
 
 /*
include/configs/bf561-acvilon.h +1 -7
index 0be170c..ed8d944 100644
@@ -145,7 +145,6 @@
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
-#define BFIN_NAND_READY     PF10
 #define BFIN_NAND_WRITE(addr, cmd) \
 	do { \
 		bfin_write8(addr, cmd); \

@@ -154,12 +153,7 @@
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-	do { \
-		bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \
-		bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \
-	} while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
 
 
 /*
include/configs/ip04.h +1 -9
index 425a745..c024d78 100644
@@ -116,7 +116,6 @@
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY     PF10
 #define BFIN_NAND_WRITE(addr, cmd) \
 	do { \
 		bfin_write8(addr, cmd); \

@@ -125,14 +124,7 @@
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-	do { \
-		bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \
-		bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \
-		bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \
-		bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \
-	} while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
 
 
 /*
Signature · 1 line
1.7.1.1
#3 lore raw

PATCH 1/2 mtd: nand_plat: add simple GPIO framework DEV_READY option

In reply to Mike Frysinger
Quoted 7 lines · Mike Frysinger

Make it easy to use GPIOs for the DEV_READY pin by using the common GPIO framework. Also make the NAND_PLAT_INIT() define optional.

Signed-off-by Mike Frysinger <[email protected]>
---
 drivers/mtd/nand/nand_plat.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

Applied patches 1 and 2 to u-boot-nand-flash.

-Scott