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Split region allocation code from pci_bios_init_device()

PATCH In review Eduard - Gabriel Munteanu 2 participants 3 messages Aug 15, 2010 – Aug 18, 2010

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#0 lore raw

PATCH 1/2 Split region allocation code from pci_bios_init_device()

pci_bios_alloc() can be used to allocate space in the PCI region for other purposes. This is needed by the AMD IOMMU support code.

---
 src/pciinit.c |   17 +++++++++++++----
 1 files changed, 13 insertions(+), 4 deletions(-)
src/pciinit.c +13 -4
index 0556ee2..bfc669f 100644
@@ -75,6 +75,16 @@ static void pci_bios_init_bridges(u16 bdf)
     }
 }
 
+static inline u32 pci_bios_alloc(u32 *region, u32 size)
+{
+    u32 ret;
+
+    ret = ALIGN(*region, size);
+    *region = ret + size;
+
+    return ret;
+}
+
 static void pci_bios_init_device(u16 bdf)
 {
     int class;
@@ -146,14 +156,13 @@ static void pci_bios_init_device(u16 bdf)
             pci_config_writel(bdf, ofs, old);
 
             if (val != 0) {
-                u32 size = (~(val & mask)) + 1;
+                u32 base, size = (~(val & mask)) + 1;
                 if (val & PCI_BASE_ADDRESS_SPACE_IO)
                     paddr = &pci_bios_io_addr;
                 else
                     paddr = &pci_bios_mem_addr;
-                *paddr = ALIGN(*paddr, size);
-                pci_set_io_region_addr(bdf, i, *paddr);
-                *paddr += size;
+                base = pci_bios_alloc(paddr, size);
+                pci_set_io_region_addr(bdf, i, base);
             }
         }
         break;
Signature · 1 line
1.7.1
#1 lore raw

PATCH 2/2 AMD IOMMU support

This initializes the AMD IOMMU and creates ACPI tables for it.

---
 Makefile       |    2 +-
 src/acpi.c     |   79 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 src/iommu.c    |   64 +++++++++++++++++++++++++++++++++++++++++++++
 src/iommu.h    |   12 ++++++++
 src/pci.h      |    4 +++
 src/pci_ids.h  |    1 +
 src/pci_regs.h |    1 +
 src/pciinit.c  |   11 ++++++++
 8 files changed, 173 insertions(+), 1 deletions(-)
 create mode 100644 src/iommu.c
 create mode 100644 src/iommu.h
Makefile +1 -1
index fe0c1ce..98f253d 100644
@@ -14,7 +14,7 @@ OUT=out/
 SRCBOTH=misc.c pmm.c stacks.c output.c util.c block.c floppy.c ata.c mouse.c \
         kbd.c pci.c serial.c clock.c pic.c cdrom.c ps2port.c smp.c resume.c \
         pnpbios.c pirtable.c vgahooks.c ramdisk.c pcibios.c blockcmd.c \
-        usb.c usb-uhci.c usb-ohci.c usb-ehci.c usb-hid.c usb-msc.c
+        usb.c usb-uhci.c usb-ohci.c usb-ehci.c usb-hid.c usb-msc.c iommu.c
 SRC16=$(SRCBOTH) system.c disk.c apm.c font.c
 SRC32FLAT=$(SRCBOTH) post.c shadow.c memmap.c coreboot.c boot.c \
       acpi.c smm.c mptable.c smbios.c pciinit.c optionroms.c mtrr.c \
src/acpi.c +79 -0

103 lines not on this page · raw message

src/iommu.c new file +64 -0

64 lines not on this page · raw message

src/iommu.h new file +12 -0
new file mode 100644
index 0000000..105af25
@@ -0,0 +1,12 @@
+#ifndef __IOMMU_H
+#define __IOMMU_H
+
+#include "types.h"
+
+void iommu_init(int bdf, u32 base);
+int iommu_get_bdf(void);
+u8 iommu_get_cap_offset(void);
+u32 iommu_get_misc(void);
+
+#endif
+
src/pci.h +4 -0
index eea5b09..3f38a0e 100644
@@ -39,6 +39,10 @@ int pci_next(int bdf, int *pmax);
     for (MAX=0x0100, BDF=pci_next(0, &MAX)      \
          ; BDF >= 0                             \
          ; BDF=pci_next(BDF+1, &MAX))
+#define foreachcap(BDF, PTR, CAP)                                         \
+    for (PTR = PCI_CAPABILITY_LIST, CAP = pci_config_readb(BDF, PTR);     \
+         CAP;                                                             \
+         PTR = CAP + PCI_CAP_LIST_NEXT, CAP = pci_config_readb(BDF, PTR))
 
 // pirtable.c
 void create_pirtable(void);
src/pci_ids.h +1 -0
index 1800f1d..3c695b2 100644
@@ -72,6 +72,7 @@
 #define PCI_CLASS_SYSTEM_RTC		0x0803
 #define PCI_CLASS_SYSTEM_PCI_HOTPLUG	0x0804
 #define PCI_CLASS_SYSTEM_SDHCI		0x0805
+#define PCI_CLASS_SYSTEM_IOMMU          0x0806
 #define PCI_CLASS_SYSTEM_OTHER		0x0880
 
 #define PCI_BASE_CLASS_INPUT		0x09
src/pci_regs.h +1 -0
index e5effd4..600df4d 100644
@@ -208,6 +208,7 @@
 #define  PCI_CAP_ID_SHPC 	0x0C	/* PCI Standard Hot-Plug Controller */
 #define  PCI_CAP_ID_SSVID	0x0D	/* Bridge subsystem vendor/device ID */
 #define  PCI_CAP_ID_AGP3	0x0E	/* AGP Target PCI-PCI bridge */
+#define  PCI_CAP_ID_SEC     0x0F    /* Secure Device (AMD IOMMU) */
 #define  PCI_CAP_ID_EXP 	0x10	/* PCI Express */
 #define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
 #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
src/pciinit.c +11 -0
index bfc669f..cad9114 100644
@@ -85,6 +85,14 @@ static inline u32 pci_bios_alloc(u32 *region, u32 size)
     return ret;
 }
 
+static void pci_bios_init_iommu(u16 bdf)
+{
+    u32 base;
+
+    base = pci_bios_alloc(&pci_bios_mem_addr, 0x4000);
+    iommu_init(bdf, base);
+}
+
 static void pci_bios_init_device(u16 bdf)
 {
     int class;
@@ -130,6 +138,9 @@ static void pci_bios_init_device(u16 bdf)
             pci_set_io_region_addr(bdf, 0, 0x80800000);
         }
         break;
+    case PCI_CLASS_SYSTEM_IOMMU:
+        pci_bios_init_iommu(bdf);
+        break;
     default:
     default_map:
         /* default memory mappings */
Signature · 1 line
1.7.1
#2 lore raw

Re: [PATCH 2/2] AMD IOMMU support

Quoted 3 lines · Eduard - Gabriel Munteanu

This initializes the AMD IOMMU and creates ACPI tables for it.

There's some questions with how best to create ACPI tables in SeaBIOS/qemu. Can you separate the iommu init code from the acpi tables code?

Thanks,
-Kevin