perf, x86: P4 PMU - check for INSTR_COMPLETED being supported by cpu

INSTR_COMPLETED is supported on particular cpu models of Netburst family, add a check for that.

Signed-off-by Cyrill Gorcunov <[email protected]>

CC Lin Ming <[email protected]>

CC Stephane Eranian <[email protected]>

CC Ingo Molnar <[email protected]>

CC Frédéric Weisbecker <[email protected]>

CC Arnaldo Carvalho de Melo <[email protected]>

CC Peter Zijlstra <[email protected]>

---

Hi Ming, please review this patch, and if you happened to have this cpu models give it a try please (if you manage to find some spare time of course). To test it we need RAW event P4_EVENT_INSTR_COMPLETED passed on any model not mentioned in p4_event_match_cpu_model, and reverse ;)

 arch/x86/kernel/cpu/perf_event_p4.c |   30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

Index: linux-2.6.git/arch/x86/kernel/cpu/perf_event_p4.c
=====================================================================

arch/x86/kernel/cpu/perf_event_p4.c +30 -0

@@ -350,6 +350,11 @@ static __initconst const u64 p4_hw_cache
  },
 };
 
+/*
+ * If general events will ever have a reference to the
+ * P4_EVENT_INSTR_COMPLETED we would ought to check for
+ * cpu model match (see how it's done for RAW events)
+ */
 static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
   /* non-halted CPU clocks */
   [PERF_COUNT_HW_CPU_CYCLES] =

@@ -428,6 +433,27 @@ static u64 p4_pmu_event_map(int hw_event
 	return config;
 }
 
+/* check cpu model specifics */
+static bool p4_event_match_cpu_model(unsigned int event_idx)
+{
+	/* INSTR_COMPLETED event only exist for model 3, 4, 6 (Prescott) */
+	if (event_idx == P4_EVENT_INSTR_COMPLETED) {
+		if (boot_cpu_data.x86_model	!= 3 &&
+			boot_cpu_data.x86_model	!= 4 &&
+			boot_cpu_data.x86_model	!= 6) {
+			pr_warning("P4 PMU: Unsupported event: INSTR_COMPLETED\n");
+			return false;
+		}
+	}
+
+	/*
+	 * note the IQ_ESCR0, IQ_ESCR1 are available on models 1 and 2
+	 * only but since we don't use them at moment -- no check
+	 */
+
+	return true;
+}
+
 static int p4_validate_raw_event(struct perf_event *event)
 {
 	unsigned int v;

@@ -439,6 +465,10 @@ static int p4_validate_raw_event(struct 
 		return -EINVAL;
 	}
 
+	/* it may be unsupported */
+	if (!p4_event_match_cpu_model(v))
+		return -EINVAL;
+
 	/*
 	 * it may have some screwed PEBS bits
 	 */

Quoted 10 lines · Cyrill Gorcunov

INSTR_COMPLETED is supported on particular cpu models of Netburst family, add a check for that.

Signed-off-by Cyrill Gorcunov <[email protected]>

CC Lin Ming <[email protected]>

CC Stephane Eranian <[email protected]>

CC Ingo Molnar <[email protected]>

CC Frédéric Weisbecker <[email protected]>

CC Arnaldo Carvalho de Melo <[email protected]>

CC Peter Zijlstra <[email protected]>

Quoted 6 lines

---

Hi Ming, please review this patch, and if you happened to have this cpu models give it a try please (if you manage to find some spare time of course). To test it we need RAW event P4_EVENT_INSTR_COMPLETED passed on any model not mentioned in p4_event_match_cpu_model, and reverse ;)

I have model 2 and 6.

int main(int argc, char *argv[])

{
        u64 config = ((((P4_EVENT_INSTR_COMPLETED) << 25)   |
                        ((1ULL) << 9)) << 32)                      |
                        (0); /* no CCCR needed */

	printf("%llx\n", config);
}

Use above code to get the raw config value 5a00020000000000.

1. Test on model 2 p4, it falls into the check correctly.

# perf top -e r5a00020000000000

Error: perfcounter syscall returned with -1 (Invalid argument)

Fatal: No CONFIG_PERF_EVENTS=y kernel support configured?

#dmesg
P4 PMU: Unsupported event: INSTR_COMPLETED

2. Test on model 6 p4,

PerfTop: 0 irqs/sec kernel: nan% exact: nan% [1000Hz raw
0x5a00020000000000], (all, 16 CPUs)

It has problem, no data is collected.

I will check this.

Lin Ming

Quoted 59 lines

 arch/x86/kernel/cpu/perf_event_p4.c |   30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

Index: linux-2.6.git/arch/x86/kernel/cpu/perf_event_p4.c
=====================================================================

arch/x86/kernel/cpu/perf_event_p4.c +30 -0

@@ -350,6 +350,11 @@ static __initconst const u64 p4_hw_cache
  },
 };
 
+/*
+ * If general events will ever have a reference to the
+ * P4_EVENT_INSTR_COMPLETED we would ought to check for
+ * cpu model match (see how it's done for RAW events)
+ */
 static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
   /* non-halted CPU clocks */
   [PERF_COUNT_HW_CPU_CYCLES] =

@@ -428,6 +433,27 @@ static u64 p4_pmu_event_map(int hw_event
 	return config;
 }
 
+/* check cpu model specifics */
+static bool p4_event_match_cpu_model(unsigned int event_idx)
+{
+	/* INSTR_COMPLETED event only exist for model 3, 4, 6 (Prescott) */
+	if (event_idx == P4_EVENT_INSTR_COMPLETED) {
+		if (boot_cpu_data.x86_model	!= 3 &&
+			boot_cpu_data.x86_model	!= 4 &&
+			boot_cpu_data.x86_model	!= 6) {
+			pr_warning("P4 PMU: Unsupported event: INSTR_COMPLETED\n");
+			return false;
+		}
+	}
+
+	/*
+	 * note the IQ_ESCR0, IQ_ESCR1 are available on models 1 and 2
+	 * only but since we don't use them at moment -- no check
+	 */
+
+	return true;
+}
+
 static int p4_validate_raw_event(struct perf_event *event)
 {
 	unsigned int v;

@@ -439,6 +465,10 @@ static int p4_validate_raw_event(struct
 		return -EINVAL;
 	}
 
+	/* it may be unsupported */
+	if (!p4_event_match_cpu_model(v))
+		return -EINVAL;
+
 	/*
 	 * it may have some screwed PEBS bits
 	 */

Quoted 47 lines · Lin Ming

Quoted 10 lines · Cyrill Gorcunov

INSTR_COMPLETED is supported on particular cpu models of Netburst family, add a check for that.

Signed-off-by Cyrill Gorcunov <[email protected]>

CC Lin Ming <[email protected]>

CC Stephane Eranian <[email protected]>

CC Ingo Molnar <[email protected]>

CC Frédéric Weisbecker <[email protected]>

CC Arnaldo Carvalho de Melo <[email protected]>

CC Peter Zijlstra <[email protected]>

Quoted 6 lines

---

Hi Ming, please review this patch, and if you happened to have this cpu models give it a try please (if you manage to find some spare time of course). To test it we need RAW event P4_EVENT_INSTR_COMPLETED passed on any model not mentioned in p4_event_match_cpu_model, and reverse ;)

I have model 2 and 6.

int main(int argc, char *argv[])

{
        u64 config = ((((P4_EVENT_INSTR_COMPLETED) << 25)   |
                        ((1ULL) << 9)) << 32)                      |
                        (0); /* no CCCR needed */

	printf("%llx\n", config);
}

Use above code to get the raw config value 5a00020000000000.

1. Test on model 2 p4, it falls into the check correctly.

# perf top -e r5a00020000000000

Error: perfcounter syscall returned with -1 (Invalid argument)

Fatal: No CONFIG_PERF_EVENTS=y kernel support configured?

#dmesg
P4 PMU: Unsupported event: INSTR_COMPLETED

2. Test on model 6 p4,

PerfTop: 0 irqs/sec kernel: nan% exact: nan% [1000Hz raw
0x5a00020000000000], (all, 16 CPUs)

Quoted 4 lines

It has problem, no data is collected.

I will check this.

Thanks Ming, try to set both bogus and bogus bits in event mask

Quoted 64 lines

Lin Ming

Quoted 59 lines

 arch/x86/kernel/cpu/perf_event_p4.c |   30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

Index: linux-2.6.git/arch/x86/kernel/cpu/perf_event_p4.c
=====================================================================

arch/x86/kernel/cpu/perf_event_p4.c +30 -0

@@ -350,6 +350,11 @@ static __initconst const u64 p4_hw_cache
  },
 };
 
+/*
+ * If general events will ever have a reference to the
+ * P4_EVENT_INSTR_COMPLETED we would ought to check for
+ * cpu model match (see how it's done for RAW events)
+ */
 static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
   /* non-halted CPU clocks */
   [PERF_COUNT_HW_CPU_CYCLES] =

@@ -428,6 +433,27 @@ static u64 p4_pmu_event_map(int hw_event
 	return config;
 }
 
+/* check cpu model specifics */
+static bool p4_event_match_cpu_model(unsigned int event_idx)
+{
+	/* INSTR_COMPLETED event only exist for model 3, 4, 6 (Prescott) */
+	if (event_idx == P4_EVENT_INSTR_COMPLETED) {
+		if (boot_cpu_data.x86_model	!= 3 &&
+			boot_cpu_data.x86_model	!= 4 &&
+			boot_cpu_data.x86_model	!= 6) {
+			pr_warning("P4 PMU: Unsupported event: INSTR_COMPLETED\n");
+			return false;
+		}
+	}
+
+	/*
+	 * note the IQ_ESCR0, IQ_ESCR1 are available on models 1 and 2
+	 * only but since we don't use them at moment -- no check
+	 */
+
+	return true;
+}
+
 static int p4_validate_raw_event(struct perf_event *event)
 {
 	unsigned int v;

@@ -439,6 +465,10 @@ static int p4_validate_raw_event(struct
 		return -EINVAL;
 	}
 
+	/* it may be unsupported */
+	if (!p4_event_match_cpu_model(v))
+		return -EINVAL;
+
 	/*
 	 * it may have some screwed PEBS bits
 	 */

Quoted 50 lines · Cyrill Gorcunov

Quoted 49 lines · Lin Ming

Quoted 11 lines · Cyrill Gorcunov

INSTR_COMPLETED is supported on particular cpu models of Netburst family,
add a check for that.

Signed-off-by Cyrill Gorcunov <[email protected]>

CC Lin Ming <[email protected]>

CC Stephane Eranian <[email protected]>

CC Ingo Molnar <[email protected]>

CC Frédéric Weisbecker <[email protected]>

CC Arnaldo Carvalho de Melo <[email protected]>

CC Peter Zijlstra <[email protected]>

Quoted 7 lines

---

Hi Ming, please review this patch, and if you happened to have this cpu models give it a try please (if you manage to find some spare time of course). To test it we need RAW event P4_EVENT_INSTR_COMPLETED passed
on any model not mentioned in p4_event_match_cpu_model, and reverse ;)

I have model 2 and 6.

int main(int argc, char *argv[])

{
        u64 config = ((((P4_EVENT_INSTR_COMPLETED) << 25)   |
                        ((1ULL) << 9)) << 32)                      |
                        (0); /* no CCCR needed */

	printf("%llx\n", config);
}

Use above code to get the raw config value 5a00020000000000.

1. Test on model 2 p4, it falls into the check correctly.

# perf top -e r5a00020000000000

Error: perfcounter syscall returned with -1 (Invalid argument)

Fatal: No CONFIG_PERF_EVENTS=y kernel support configured?

#dmesg
P4 PMU: Unsupported event: INSTR_COMPLETED

2. Test on model 6 p4,

PerfTop: 0 irqs/sec kernel: nan% exact: nan% [1000Hz raw
0x5a00020000000000], (all, 16 CPUs)

Quoted 6 lines

Quoted 4 lines

It has problem, no data is collected.

I will check this.

Thanks Ming, try to set both bogus and bogus bits in event mask

Unfortunately, same result.

Lin Ming

Quoted 65 lines

Quoted 65 lines

Lin Ming

Quoted 60 lines

 arch/x86/kernel/cpu/perf_event_p4.c |   30
++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

Index: linux-2.6.git/arch/x86/kernel/cpu/perf_event_p4.c
=====================================================================

arch/x86/kernel/cpu/perf_event_p4.c +30 -0

@@ -350,6 +350,11 @@ static __initconst const u64 p4_hw_cache
  },
 };
 
+/*
+ * If general events will ever have a reference to the
+ * P4_EVENT_INSTR_COMPLETED we would ought to check for
+ * cpu model match (see how it's done for RAW events)
+ */
 static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
   /* non-halted CPU clocks */
   [PERF_COUNT_HW_CPU_CYCLES] =

@@ -428,6 +433,27 @@ static u64 p4_pmu_event_map(int hw_event
 	return config;
 }
 
+/* check cpu model specifics */
+static bool p4_event_match_cpu_model(unsigned int event_idx)
+{
+	/* INSTR_COMPLETED event only exist for model 3, 4, 6 (Prescott) */
+	if (event_idx == P4_EVENT_INSTR_COMPLETED) {
+		if (boot_cpu_data.x86_model	!= 3 &&
+			boot_cpu_data.x86_model	!= 4 &&
+			boot_cpu_data.x86_model	!= 6) {
+			pr_warning("P4 PMU: Unsupported event: INSTR_COMPLETED\n");
+			return false;
+		}
+	}
+
+	/*
+	 * note the IQ_ESCR0, IQ_ESCR1 are available on models 1 and 2
+	 * only but since we don't use them at moment -- no check
+	 */
+
+	return true;
+}
+
 static int p4_validate_raw_event(struct perf_event *event)
 {
 	unsigned int v;

@@ -439,6 +465,10 @@ static int p4_validate_raw_event(struct
 		return -EINVAL;
 	}
 
+	/* it may be unsupported */
+	if (!p4_event_match_cpu_model(v))
+		return -EINVAL;
+
 	/*
 	 * it may have some screwed PEBS bits
 	 */