Add non PAS wcss Q6 support for QCS404
Subsystems (5)
v3 cover Add non PAS wcss Q6 support for QCS404
Add non PAS(Peripheral Authentication System) WCSS remoteproc driver support and wcss clock/reset controls for QCS404 SOC. Add WCSS q6 bootup and shutdown sequence handled from Application Processor SubSystem(APSS).
Changes since v2:
Removed unused properties.
Refactored code to have common logic b/w ipq8074 and QCS404, wherever possible. Added compatible example.
Removed wcss-protected bool.
Changes since v1:
Corrected clock names as per comments in v1 patch.
Govind Singh (7):
dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings
clk: qcom: Add WCSS Q6DSP clock controller for QCS404
dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings
clk: qcom: Add WCSS gcc clock control for QCS404
remoteproc: qcom: wcss: populate hardcoded param using driver data
remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
remoteproc: qcom: wcss: explicitly request exclusive reset control
.../devicetree/bindings/clock/qcom,wcsscc.txt | 26 + .../bindings/remoteproc/qcom,q6v5.txt | 61 ++ drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-qcs404.c | 51 +- drivers/clk/qcom/wcsscc-qcs404.c | 297 +++++++++ drivers/remoteproc/qcom_q6v5_wcss.c | 574 +++++++++++++++++- include/dt-bindings/clock/qcom,gcc-qcs404.h | 3 + include/dt-bindings/clock/qcom,wcss-qcs404.h | 24 + 9 files changed, 1016 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,wcsscc.txt create mode 100644 drivers/clk/qcom/wcsscc-qcs404.c create mode 100644 include/dt-bindings/clock/qcom,wcss-qcs404.h
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 1/7 dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings
Add device tree bindings for WiFi QDSP subsystem clock controls found in OCS405 soc.
--- .../devicetree/bindings/clock/qcom,wcsscc.txt | 26 +++++++++++++++++++ include/dt-bindings/clock/qcom,wcss-qcs404.h | 24 +++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,wcsscc.txt create mode 100644 include/dt-bindings/clock/qcom,wcss-qcs404.h
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt new file +26 -0
@@ -0,0 +1,26 @@ +Qualcomm WCSS Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,qcs404-wcsscc" +- #clock-cells : from common clock binding, shall contain 1. +- reg : shall contain base register address and size, + in the order + Index-0 maps to WCSS_Q6SSTOP clocks register region + Index-1 maps to WCSS_TCSR register region + Index-2 maps to WCSS_QDSP6SS register region + +Optional properties : +- reg-names : register names of WCSS domain + "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss". + +Example: +The below node has to be defined in the cases where the WCSS peripheral loader +would bring the subsystem out of reset. + + clock_wcsscc: qcom,wcsscc@7000000 { + compatible = "qcom,qcs404-wcsscc"; + reg = <0x07500000 0x4e000>, <0x07550000 0x8012>, <0x07400000 0x104>; + reg-names = "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss"; + #clock-cells = <1>; + };
include/dt-bindings/clock/qcom,wcss-qcs404.h new file +24 -0
@@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_WCSS_QCS404_H +#define _DT_BINDINGS_CLK_WCSS_QCS404_H + +#define WCSS_AHBFABRIC_CBCR_CLK 0 +#define WCSS_AHBS_CBCR_CLK 1 +#define WCSS_TCM_CBCR_CLK 2 +#define WCSS_AHBM_CBCR_CLK 3 +#define WCSS_AXIM_CBCR_CLK 4 +#define WCSS_BCR_CBCR_CLK 5 +#define WCSS_LCC_CBCR_CLK 6 +#define WCSS_QDSP6SS_XO_CBCR_CLK 7 +#define WCSS_QDSP6SS_SLEEP_CBCR_CLK 8 +#define WCSS_QDSP6SS_GFMMUX_CLK 9 + +#define Q6SSTOP_QDSP6SS_RESET 0 +#define Q6SSTOP_QDSP6SS_CORE_RESET 1 +#define Q6SSTOP_QDSP6SS_BUS_RESET 2 +#define Q6SSTOP_BCR_RESET 3 +#endif
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Stephen Boyd
maintainerRe: [PATCH v3 1/7] dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings
Quoting Govind Singh (2018-12-15 02:35:51)
Quoted 5 lines
Add device tree bindings for WiFi QDSP subsystem clock controls found in OCS405 soc.
Signed-off-by Govind Singh <[email protected]>Reviewed-by Rob Herring <[email protected]>
It was?
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt line 6
Quoted 12 lines
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt new file +6
-0@@ -0,0 +1,26 @@ +Qualcomm WCSS Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,qcs404-wcsscc" +- #clock-cells : from common clock binding, shall contain 1.
Drop the full-stop please.
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt line 12
Quoted 6 lines
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt new file +6
-0+- reg : shall contain base register address and size, + in the order + Index-0 maps to WCSS_Q6SSTOP clocks register region + Index-1 maps to WCSS_TCSR register region + Index-2 maps to WCSS_QDSP6SS register region +
Index 0, Index 1, Index 2? Not sure why there's a hyphen there.
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt line 21
Quoted 9 lines
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt new file +9
-0+Optional properties : +- reg-names : register names of WCSS domain + "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss". + +Example: +The below node has to be defined in the cases where the WCSS peripheral loader +would bring the subsystem out of reset. + + clock_wcsscc: qcom,wcsscc@7000000 {
clock-controller@7000000
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt line 23
Quoted 2 lines
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt new file +2
-0+ compatible = "qcom,qcs404-wcsscc"; + reg = <0x07500000 0x4e000>, <0x07550000 0x8012>, <0x07400000 0x104>;
And then that unit address doesn't match the first offset so that needs fixing too.
Quoted 3 lines
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt new file +3
-0+ reg-names = "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss"; + #clock-cells = <1>; + };
Re: [PATCH v3 1/7] dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings
Quoted 15 lines · Stephen Boyd
Quoting Govind Singh (2018-12-15 02:35:51)
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt line 12
Quoted 13 lines
Add device tree bindings for WiFi QDSP subsystem clock controls found in OCS405 soc.
+- reg : shall contain base register address and
size,(quoted diff) +2
-0+ in the order + Index-0 maps to WCSS_Q6SSTOP clocks registerregion
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt new file +3
-0+ Index-1 maps to WCSS_TCSR register region + Index-2 maps to WCSS_QDSP6SS register region +
Quoted 2 lines
Index 0, Index 1, Index 2? Not sure why there's a hyphen there.
Fixed in v4.
Quoted 13 lines
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt line 21
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt new file +6
-0+Optional properties : +- reg-names : register names of WCSS domain + "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss". + +Example: +The below node has to be defined in the cases where the WCSSperipheral loader
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt new file +3
-0+would bring the subsystem out of reset. + + clock_wcsscc: qcom,wcsscc@7000000 {clock-controller@7000000
Quoted 7 lines
Quoted 3 lines
(quoted diff) +2
-0+ compatible = "qcom,qcs404-wcsscc"; + reg = <0x07500000 0x4e000>, <0x07550000 0x8012>,<
0x074000000x104>;And then that unit address doesn't match the first offset so that needs fixing too.
Fixed in V4.
Quoted 4 lines
Documentation/devicetree/bindings/clock/qcom,wcsscc.txt line 26
Quoted 4 lines
+ reg-names = "
wcss_q6sstop", "wcnss_tcsr",
"wcss_qdsp6ss";Documentation/devicetree/bindings/clock/qcom,wcsscc.txt new file +2
-0+ #clock-cells = <1>; + };
BR,
Govind
PATCH v3 2/7 clk: qcom: Add WCSS Q6DSP clock controller for QCS404
In reply to Govind SinghAdd support for the WCSS QDSP clock control used on qcs404 based devices. This would allow wcss remoteproc driver to control the required WCSS QDSP clock/reset controls to bring the subsystem out of reset and shutdown the WCSS QDSP.
--- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/wcsscc-qcs404.c | 297 +++++++++++++++++++++++++++++++ 3 files changed, 307 insertions(+) create mode 100644 drivers/clk/qcom/wcsscc-qcs404.c
drivers/clk/qcom/Kconfig +9 -0
@@ -222,6 +222,15 @@ config QCS_GCC_404 Say Y if you want to use multimedia devices or peripheral devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc. +config QCS_WCSSCC_404 + tristate "QCS404 WCSS Clock Controller" + depends on COMMON_CLK_QCOM + select QCS_GCC_404 + help + Support for the WCSS clock controller on QCS404 devices. + Say Y if you want to use the WCSS branch clocks of the WCSS clock + controller to reset the WCSS subsystem. + config SDM_GCC_845 tristate "SDM845 Global Clock Controller" select QCOM_GDSC
drivers/clk/qcom/Makefile +1 -0
@@ -38,6 +38,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o +obj-$(CONFIG_QCS_WCSSCC_404) += wcsscc-qcs404.o obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
drivers/clk/qcom/wcsscc-qcs404.c new file +297 -0
297 lines not on this page · raw message
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Stephen Boyd
maintainerRe: [PATCH v3 2/7] clk: qcom: Add WCSS Q6DSP clock controller for QCS404
Quoting Govind Singh (2018-12-15 02:35:52)
drivers/clk/qcom/Kconfig config QCS_GCC_404 · line 227
Quoted 11 lines
drivers/clk/qcom/Kconfig +3
-0@@ -222,6 +222,15 @@ config QCS_GCC_404 Say Y if you want to use multimedia devices or peripheral devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc. +config QCS_WCSSCC_404 + tristate "QCS404 WCSS Clock Controller" + depends on COMMON_CLK_QCOM
This is going away, so you can drop this depends on statement soon.
Quoted 15 lines
drivers/clk/qcom/Kconfig +6
-0+ select QCS_GCC_404 + help + Support for the WCSS clock controller on QCS404 devices. + Say Y if you want to use the WCSS branch clocks of the WCSS clock + controller to reset the WCSS subsystem. + config SDM_GCC_845 tristate "SDM845 Global Clock Controller" select QCOM_GDSCdrivers/clk/qcom/wcsscc-qcs404.c new file +0
-0
drivers/clk/qcom/wcsscc-qcs404.c line 10
Quoted 10 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +10
-0@@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +*/ + +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/of_address.h>
Is this used?
drivers/clk/qcom/wcsscc-qcs404.c line 11
Quoted 1 line
drivers/clk/qcom/wcsscc-qcs404.c new file +1
-0+#include <linux/clk.h>
Is this used?
drivers/clk/qcom/wcsscc-qcs404.c line 14
Quoted 3 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +3
-0+#include <linux/clk-provider.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h>
Is this used?
drivers/clk/qcom/wcsscc-qcs404.c line 17
Quoted 3 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +3
-0+ +#include <dt-bindings/clock/qcom,wcss-qcs404.h> +#include <linux/reset-controller.h>
Cool, but where are the resets? Also, please put <linux/*.h> before any dt-bindings includes.
drivers/clk/qcom/wcsscc-qcs404.c line 25
Quoted 8 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +8
-0+ +#include "clk-regmap.h" +#include "clk-branch.h" +#include "common.h" +#include "reset.h" + +/* Q6SSTOP clocks. These clocks are voted +* during by remoteproc client when loaded from
This sentence doesn't parse easily. "during by"?
drivers/clk/qcom/wcsscc-qcs404.c line 26
Quoted 1 line
drivers/clk/qcom/wcsscc-qcs404.c new file +1
-0+* user space, soc hang is seen when CCF turns
SoC? Or just system hang?
drivers/clk/qcom/wcsscc-qcs404.c line 27
Quoted 1 line
drivers/clk/qcom/wcsscc-qcs404.c new file +1
-0+* off unused clocks. As a temp solution use
Temporary?
drivers/clk/qcom/wcsscc-qcs404.c line 29
Quoted 2 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +2
-0+* CLK_IGNORE_UNUSED flags which prevent these +* clocks from being gated during bootup.
Ok.. but userspace is after CLK_IGNORE_UNUSED would process these clks? So we're keeping them on from the bootloader why? Something is using these clks during that operation but after that point they need to be turned off?
Quoted 10 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +10
-0+*/ + +static int wcss_clocks_qcs404_probe (struct platform_device *pdev,int index, +const struct qcom_cc_desc *desc) +{ +struct regmap *regmap; +struct resource *res; +void __iomem *base; + + res =platform_get_resource (pdev,IORESOURCE_MEM , index);
drivers/clk/qcom/wcsscc-qcs404.c line 250
Quoted 10 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +10
-0+ base =devm_ioremap_resource (&pdev->dev, res); +if (IS_ERR (base)) +return -ENOMEM ; + + regmap =devm_regmap_init_mmio (&pdev->dev, base, desc->config); +if (IS_ERR (regmap)) +return PTR_ERR (regmap); + +return qcom_cc_really_probe (pdev, desc, regmap); +}
You're the second user of this "probe on reg region" logic. Please extract it out of the lpasscc driver and put it into common.c so it can be reused by the two drivers.
Quoted 29 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +29
-0+ +static int wcss_cc_qcs404_probe (struct platform_device *pdev) +{ +const struct qcom_cc_desc *desc; +int ret; + + wcss_regmap_config.name ="wcss_q6sstop" ; + desc = &wcss_q6sstop_qcs404_desc; + + ret =wcss_clocks_qcs404_probe (pdev,0 , desc); +if (ret) +return ret; + + wcss_regmap_config.name ="wcnss_tcsr" ; + desc = &wcnss_tcsr_qcs404_desc; + + ret =wcss_clocks_qcs404_probe (pdev,1 , desc); +if (ret) +return ret; + + wcss_regmap_config.name ="wcss_qdsp6ss" ; + desc = &wcnss_qdsp6ss_qcs404_desc; + +return wcss_clocks_qcs404_probe (pdev,2 , desc); +} + +static struct platform_driver wcss_cc_qcs404_driver = { + .probe = wcss_cc_qcs404_probe, + .driver = {
drivers/clk/qcom/wcsscc-qcs404.c line 295
Quoted 10 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +10
-0+ .name = "qcs404-wcsscc", + .of_match_table = wcss_cc_qcs404_match_table, + }, +}; + +static int __init wcss_cc_qcs404_init (void ) +{ +return platform_driver_register (&wcss_cc_qcs404_driver); +} +subsys_initcall (wcss_cc_qcs404_init);
Where is the driver removal exit function?
drivers/clk/qcom/wcsscc-qcs404.c line 90
Quoted 2 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +2
-0+ +MODULE_LICENSE ("GPL v2" );
MODULE_DESCRIPTION?
Re: [PATCH v3 2/7] clk: qcom: Add WCSS Q6DSP clock controller for QCS404
Quoted 9 lines · Stephen Boyd
Quoting Govind Singh (2018-12-15 02:35:52)
Quoted 8 lines
drivers/clk/qcom/Kconfig +0
-0@@ -222,6 +222,15 @@ config QCS_GCC_404 Say Y if you want to use multimedia devices or peripheral devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
Quoted 6 lines
drivers/clk/qcom/Kconfig config QCS_GCC_404 · line 227
Quoted 3 lines
drivers/clk/qcom/Kconfig +3
-0+config QCS_WCSSCC_404 + tristate "QCS404 WCSS Clock Controller" + depends on COMMON_CLK_QCOMThis is going away, so you can drop this depends on statement soon.
Removed in v4.
Quoted 29 lines
Quoted 16 lines
drivers/clk/qcom/Kconfig +4
-0+ select QCS_GCC_404 + help + Support for the WCSS clock controller on QCS404 devices. + Say Y if you want to use the WCSS branch clocks of the WCSSclock
drivers/clk/qcom/Kconfig +2
-0+ controller to reset the WCSS subsystem. + config SDM_GCC_845 tristate "SDM845 Global Clock Controller" select QCOM_GDSCdrivers/clk/qcom/wcsscc-qcs404.c new file +0
-0drivers/clk/qcom/wcsscc-qcs404.c line 10
Quoted 10 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +10
-0@@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +*/ + +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/of_address.h> Is this used?
Quoted 4 lines
drivers/clk/qcom/wcsscc-qcs404.c line 11
Quoted 1 line
drivers/clk/qcom/wcsscc-qcs404.c new file +1
-0+#include <linux/clk.h> Is this used?
Removed unnecessary includes and cleanup suggested by you in v4.
Quoted 9 lines
drivers/clk/qcom/wcsscc-qcs404.c line 29
Quoted 3 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +2
-0+* CLK_IGNORE_UNUSED flags which prevent these +* clocks from being gated during bootup. Ok.. but userspace is after
CLK_IGNORE_UNUSEDwould process these clks? So we're keeping them on from the bootloader why? Something is using these clks during that operation but after that point they need to be turned off?
Yes remote proc will process this clock during rproc start. I discussed this issue with Bjorn. I will seek his help.
Need to root cause why these clocks are voted from bootloader.
Quoted 18 lines
Quoted 18 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +3
-0+*/ + +static int wcss_clocks_qcs404_probe(struct platform_device *pdev, intindex,
drivers/clk/qcom/wcsscc-qcs404.c new file +12
-0+ const struct qcom_cc_desc *desc) +{ +struct regmap *regmap; +struct resource *res; +void __iomem *base; + + res =platform_get_resource (pdev,IORESOURCE_MEM , index); + base =devm_ioremap_resource (&pdev->dev, res); +if (IS_ERR (base)) +return -ENOMEM ; + + regmap = devm_regmap_init_mmio(&pdev->dev, base,
desc->config);
+ if (IS_ERR(regmap))
Quoted 9 lines
drivers/clk/qcom/wcsscc-qcs404.c line 250
Quoted 4 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +4
-0+return PTR_ERR (regmap); + +return qcom_cc_really_probe (pdev, desc, regmap); +}You're the second user of this "probe on reg region" logic. Please extract it out of the lpasscc driver and put it into
common.cso it can be reused by the two drivers.
I have addressed in v4.
Quoted 33 lines
Quoted 33 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +33
-0+ +static int wcss_cc_qcs404_probe (struct platform_device *pdev) +{ +const struct qcom_cc_desc *desc; +int ret; + + wcss_regmap_config.name ="wcss_q6sstop" ; + desc = &wcss_q6sstop_qcs404_desc; + + ret =wcss_clocks_qcs404_probe (pdev,0 , desc); +if (ret) +return ret; + + wcss_regmap_config.name ="wcnss_tcsr" ; + desc = &wcnss_tcsr_qcs404_desc; + + ret =wcss_clocks_qcs404_probe (pdev,1 , desc); +if (ret) +return ret; + + wcss_regmap_config.name ="wcss_qdsp6ss" ; + desc = &wcnss_qdsp6ss_qcs404_desc; + +return wcss_clocks_qcs404_probe (pdev,2 , desc); +} + +static struct platform_driver wcss_cc_qcs404_driver = { + .probe = wcss_cc_qcs404_probe, + .driver = { + .name ="qcs404-wcsscc" , + .of_match_table = wcss_cc_qcs404_match_table, + }, +};
Quoted 9 lines
drivers/clk/qcom/wcsscc-qcs404.c line 295
Quoted 6 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +6
-0+ +static int __init wcss_cc_qcs404_init (void ) +{ +return platform_driver_register (&wcss_cc_qcs404_driver); +} +subsys_initcall (wcss_cc_qcs404_init);Where is the driver removal exit function?
My bad, added in v4.
Quoted 4 lines
drivers/clk/qcom/wcsscc-qcs404.c
Quoted 2 lines
drivers/clk/qcom/wcsscc-qcs404.c new file +2
-0+ +MODULE_LICENSE ("GPL v2" );
MODULE_DESCRIPTION?
BR,
Govind
PATCH v3 3/7 dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings
In reply to Govind SinghAdd device tree bindings for WiFi QDSP gcc clock controls found in QCS404 soc.
--- include/dt-bindings/clock/qcom,gcc-qcs404.h | 3 +++ 1 file changed, 3 insertions(+)
include/dt-bindings/clock/qcom,gcc-qcs404.h +3 -0
@@ -146,6 +146,8 @@#define GCC_MDP_TBU_CLK 138#define GCC_QDSS_DAP_CLK 139#define GCC_DCC_XO_CLK 140 +#define GCC_WCSS_Q6_AHB_CBCR_CLK 141 +#define GCC_WCSS_Q6_AXIM_CBCR_CLK 142#define GCC_GENI_IR_BCR 0#define GCC_USB_HS_BCR 1
@@ -168,5 +170,6 @@#define GCC_PCIE_0_CORE_STICKY_ARES 18#define GCC_PCIE_0_SLEEP_ARES 19#define GCC_PCIE_0_PIPE_ARES 20 +#define GCC_WDSP_RESTART 21#endif
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Stephen Boyd
maintainerRe: [PATCH v3 3/7] dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings
Quoting Govind Singh (2018-12-15 02:35:53)
Quoted 14 lines
Add device tree bindings for WiFi QDSP gcc clock controls found in QCS404 soc.
Signed-off-by Govind Singh <[email protected]>Reviewed-by Rob Herring <[email protected]>--- include/dt-bindings/clock/qcom,gcc-qcs404.h | 3 +++ 1 file changed, 3 insertions(+)include/dt-bindings/clock/qcom,gcc-qcs404.h +0
-0
include/dt-bindings/clock/qcom,gcc-qcs404.h line 150
Quoted 5 lines
include/dt-bindings/clock/qcom,gcc-qcs404.h +2
-0@@ -146,6 +146,8 @@#define GCC_MDP_TBU_CLK 138#define GCC_QDSS_DAP_CLK 139#define GCC_DCC_XO_CLK 140 +#define GCC_WCSS_Q6_AHB_CBCR_CLK 141 +#define GCC_WCSS_Q6_AXIM_CBCR_CLK 142
Does the register really call it FOO_CBCR_CLK? I'd prefer we drop the CBCR part unless you really want it to keep it.
Quoted 3 lines
include/dt-bindings/clock/qcom,gcc-qcs404.h +0
-0#define GCC_GENI_IR_BCR 0#define GCC_USB_HS_BCR 1
Re: [PATCH v3 3/7] dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings
Quoted 10 lines · Stephen Boyd
Quoting Govind Singh (2018-12-15 02:35:53)
Quoted 9 lines
Add device tree bindings for WiFi QDSP gcc clock controls found in QCS404 soc.
Signed-off-by Govind Singh <[email protected]>Reviewed-by Rob Herring <[email protected]>--- include/dt-bindings/clock/qcom,gcc-qcs404.h | 3 +++ 1 file changed, 3 insertions(+)
Quoted 14 lines
include/dt-bindings/clock/qcom,gcc-qcs404.h line 150
Quoted 10 lines
include/dt-bindings/clock/qcom,gcc-qcs404.h +2
-0@@ -146,6 +146,8 @@#define GCC_MDP_TBU_CLK 138#define GCC_QDSS_DAP_CLK 139#define GCC_DCC_XO_CLK 140 +#define GCC_WCSS_Q6_AHB_CBCR_CLK 141 +#define GCC_WCSS_Q6_AXIM_CBCR_CLK 142Does the register really call it
FOO_CBCR_CLK? I'd prefer we drop the CBCR part unless you really want it to keep it.
Thanks, removed CBCR in v4.
Quoted 3 lines
Quoted 3 lines
include/dt-bindings/clock/qcom,gcc-qcs404.h +0
-0#define GCC_GENI_IR_BCR 0#define GCC_USB_HS_BCR 1
PATCH v3 4/7 clk: qcom: Add WCSS gcc clock control for QCS404
In reply to Govind SinghAdd support for the WCSS QDSP gcc clock control used on qcs404 based devices. This would allow wcss remoteproc driver to control the required gcc clocks to bring the subsystem out of reset.
--- drivers/clk/qcom/gcc-qcs404.c | 51 ++++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-)
drivers/clk/qcom/gcc-qcs404.c +50 -1
@@ -2520,6 +2520,32 @@ static struct clk_branch gcc_usb_hs_system_clk = { }, }; +static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = { + .halt_reg =0x1e004 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x1e004 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_wdsp_q6ss_ahbs_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wdsp_q6ss_axim_clk = { + .halt_reg =0x1e008 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x1e008 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_wdsp_q6ss_axim_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_hw *gcc_qcs404_hws[] = { &cxo.hw, };
@@ -2661,6 +2687,9 @@ static struct clk_regmap *gcc_qcs404_clocks[] = { [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr, + [GCC_WCSS_Q6_AHB_CBCR_CLK] = NULL, + [GCC_WCSS_Q6_AXIM_CBCR_CLK] = NULL, + };static const struct qcom_reset_map gcc_qcs404_resets[] = {
@@ -2685,6 +2714,21 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = { [GCC_PCIE_0_SLEEP_ARES] = {0x3e040, 1}, [GCC_PCIE_0_PIPE_ARES] = {0x3e040, 0}, [GCC_EMAC_BCR] = { 0x4e000 }, + [GCC_GENI_IR_BCR] = {0x0F000}, + [GCC_USB_HS_BCR] = {0x41000}, + [GCC_USB2_HS_PHY_ONLY_BCR] = {0x41034}, + [GCC_QUSB2_PHY_BCR] = {0x4103C}, + [GCC_USB_HS_PHY_CFG_AHB_BCR] = {0x0000C, 1}, + [GCC_USB2A_PHY_BCR] = {0x0000C, 0}, + [GCC_USB3_PHY_BCR] = {0x39004}, + [GCC_USB_30_BCR] = {0x39000}, + [GCC_USB3PHY_PHY_BCR] = {0x39008}, + [GCC_PCIE_0_BCR] = {0x3E000}, + [GCC_PCIE_0_PHY_BCR] = {0x3E004}, + [GCC_PCIE_0_LINK_DOWN_BCR] = {0x3E038}, + [GCC_PCIEPHY_0_PHY_BCR] = {0x3E03C}, + [GCC_EMAC_BCR] = {0x4E000}, + [GCC_WDSP_RESTART] = {0x19000}, };static const struct regmap_config gcc_qcs404_regmap_config = {
@@ -2695,7 +2739,7 @@ static const struct regmap_config gcc_qcs404_regmap_config = { .fast_io = true, }; -static const struct qcom_cc_desc gcc_qcs404_desc = { +static struct qcom_cc_desc gcc_qcs404_desc = { .config = &gcc_qcs404_regmap_config, .clks = gcc_qcs404_clocks, .num_clks =ARRAY_SIZE (gcc_qcs404_clocks),
@@ -2726,6 +2770,11 @@ static int gcc_qcs404_probe(struct platform_device *pdev)return ret; } +#ifdef CONFIG_QCS_WCSSCC_404 + gcc_qcs404_clocks[GCC_WCSS_Q6_AHB_CBCR_CLK ] = &gcc_wdsp_q6ss_ahbs_clk.clkr; + gcc_qcs404_clocks[GCC_WCSS_Q6_AXIM_CBCR_CLK ] = &gcc_wdsp_q6ss_axim_clk.clkr; +#endif +return qcom_cc_really_probe (pdev, &gcc_qcs404_desc, regmap); }
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v3 4/7] clk: qcom: Add WCSS gcc clock control for QCS404
Quoted 1 line · Govind Singh
drivers/clk/qcom/gcc-qcs404.c +0
-0
[..]
drivers/clk/qcom/gcc-qcs404.c static int gcc_qcs404_probe(struct platform_device *pdev) · line 2773
Quoted 5 lines
drivers/clk/qcom/gcc-qcs404.c +1
-0@@ -2726,6 +2770,11 @@ static int gcc_qcs404_probe(struct platform_device *pdev)return ret; } +#ifdef CONFIG_QCS_WCSSCC_404
We don't do compile time configuration of things like this, expect all variants of QCS404 (regardless of security solution) to run off the same kernel binary.
Instead use the recently introduced "protected-clocks" property.
Regards,
Bjorn
Re: [PATCH v3 4/7] clk: qcom: Add WCSS gcc clock control for QCS404
Quoted 8 lines · Bjorn Andersson
Quoted 1 line · Govind Singh
drivers/clk/qcom/gcc-qcs404.c +0
-0[..]
Quoted 5 lines
drivers/clk/qcom/gcc-qcs404.c +0
-0@@ -2726,6 +2770,11 @@ static int gcc_qcs404_probe(struct platform_device *pdev)return ret; }
Quoted 8 lines
drivers/clk/qcom/gcc-qcs404.c static int gcc_qcs404_probe(struct platform_device *pdev) · line 2773
Quoted 1 line
drivers/clk/qcom/gcc-qcs404.c +1
-0+#ifdef CONFIG_QCS_WCSSCC_404 We don't do compile time configuration of things like this, expect all variants of QCS404 (regardless of security solution) to run off the same kernel binary.
Instead use the recently introduced "protected-clocks" property.
Fixed in v4. Seems LPASS is no more using "protected-clocks", i used "unprotected-clocks" property to avoid inverted logic.
Quoted 2 lines
Regards,
Bjorn
Stephen Boyd
maintainerRe: [PATCH v3 4/7] clk: qcom: Add WCSS gcc clock control for QCS404
In reply to Govind SinghQuoting Govind Singh (2018-12-15 02:35:54)
drivers/clk/qcom/gcc-qcs404.c static int gcc_qcs404_probe(struct platform_device *pdev) · line 2775
Quoted 7 lines
drivers/clk/qcom/gcc-qcs404.c +3
-0@@ -2726,6 +2770,11 @@ static int gcc_qcs404_probe(struct platform_device *pdev)return ret; } +#ifdef CONFIG_QCS_WCSSCC_404 + gcc_qcs404_clocks[GCC_WCSS_Q6_AHB_CBCR_CLK ] = &gcc_wdsp_q6ss_ahbs_clk.clkr; + gcc_qcs404_clocks[GCC_WCSS_Q6_AXIM_CBCR_CLK ] = &gcc_wdsp_q6ss_axim_clk.clkr;
What is going on with the tabs here? Why is it under an ifdef?
Quoted 9 lines
drivers/clk/qcom/gcc-qcs404.c +2
-0+#endif +return qcom_cc_really_probe (pdev, &gcc_qcs404_desc, regmap); }Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 5/7 remoteproc: qcom: wcss: populate hardcoded param using driver data
In reply to Govind SinghQ6 based WiFi fw loading is supported across different targets, ex: IPQ8074/QCS404. In order to support different fw names/pas id etc, populate hardcoded param using driver data.
--- drivers/remoteproc/qcom_q6v5_wcss.c | 40 ++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 6 deletions(-)
drivers/remoteproc/qcom_q6v5_wcss.c +34 -6
@@ -8,6 +8,7 @@#include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> +#include <linux/of_device.h> #include <linux/of_reserved_mem.h> #include <linux/platform_device.h> #include <linux/regmap.h>
@@ -16,7 +17,6 @@#include "qcom_common.h" #include "qcom_q6v5.h" -#define WCSS_CRASH_REASON 421/* Q6SS Register Offsets */ #define Q6SS_RESET_REG 0x014
@@ -70,6 +70,14 @@#define TCSR_WCSS_CLK_MASK 0x1F#define TCSR_WCSS_CLK_ENABLE 0x14 +struct wcss_data { +void (*pas_handover)(struct qcom_q6v5 *q6v5); +const char *firmware_name; +int crash_reason_smem; +int version; +int pas_id; +}; +struct q6v5_wcss {struct device *dev;
@@ -91,6 +99,10 @@ struct q6v5_wcss {phys_addr_t mem_reloc;void *mem_region;size_t mem_size; + +int crash_reason_smem; +int pas_id; +int version; };static int q6v5_wcss_reset (struct q6v5_wcss *wcss)
@@ -427,7 +439,7 @@ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) wcss->mem_size, &wcss->mem_reloc); } -static const struct rproc_ops q6v5_wcss_ops = { +static const struct rproc_ops q6v5_wcss_ipq8074_ops = { .start = q6v5_wcss_start, .stop = q6v5_wcss_stop, .da_to_va = q6v5_wcss_da_to_va,
@@ -527,12 +539,17 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)static int q6v5_wcss_probe (struct platform_device *pdev) { +const struct wcss_data *desc;struct q6v5_wcss *wcss;struct rproc *rproc;int ret; - rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ops, -"IPQ8074/q6_fw.mdt" ,sizeof (*wcss)); + desc =of_device_get_match_data (&pdev->dev); +if (!desc) +return -EINVAL ; + + rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops, + desc->firmware_name,sizeof (*wcss));if (!rproc) {dev_err (&pdev->dev,"failed to allocate rproc\n" );return -ENOMEM ;
@@ -540,6 +557,9 @@ static int q6v5_wcss_probe(struct platform_device *pdev) wcss = rproc->priv; wcss->dev = &pdev->dev; + wcss->pas_id = desc->pas_id; + wcss->version = desc->version; + wcss->crash_reason_smem = desc->crash_reason_smem; ret =q6v5_wcss_init_mmio (wcss, pdev);if (ret)
@@ -553,7 +573,8 @@ static int q6v5_wcss_probe(struct platform_device *pdev)if (ret) goto free_rproc; - ret =qcom_q6v5_init (&wcss->q6v5, pdev, rproc,WCSS_CRASH_REASON ,NULL ); + ret =qcom_q6v5_init (&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, + desc->pas_handover);if (ret) goto free_rproc;
@@ -581,8 +602,15 @@ static int q6v5_wcss_remove(struct platform_device *pdev)return 0 ; } +static const struct wcss_data wcss_ipq8074_res_init = { + .firmware_name ="IPQ8074/q6_fw.mdt" , + .crash_reason_smem =421 , + .pas_handover =NULL , +}; +static const struct of_device_id q6v5_wcss_of_match[] = { - { .compatible ="qcom,ipq8074-wcss-pil" }, + { .compatible ="qcom,ipq8074-wcss-pil" , .data = &wcss_ipq8074_res_init }, + { }, };MODULE_DEVICE_TABLE (of, q6v5_wcss_of_match);
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Stephen Boyd
maintainerRe: [PATCH v3 5/7] remoteproc: qcom: wcss: populate hardcoded param using driver data
Quoting Govind Singh (2018-12-15 02:35:55)
Quoted 13 lines
drivers/remoteproc/qcom_q6v5_wcss.c +0
-1@@ -16,7 +17,6 @@#include "qcom_common.h" #include "qcom_q6v5.h" -#define WCSS_CRASH_REASON 421/* Q6SS Register Offsets */ #define Q6SS_RESET_REG 0x014
drivers/remoteproc/qcom_q6v5_wcss.c line 77
Quoted 8 lines
drivers/remoteproc/qcom_q6v5_wcss.c +5
-0@@ -70,6 +70,14 @@#define TCSR_WCSS_CLK_MASK 0x1F#define TCSR_WCSS_CLK_ENABLE 0x14 +struct wcss_data { +void (*pas_handover)(struct qcom_q6v5 *q6v5); +const char *firmware_name; +int crash_reason_smem; +int version;
version can be negative?
drivers/remoteproc/qcom_q6v5_wcss.c line 78
Quoted 1 line
drivers/remoteproc/qcom_q6v5_wcss.c +1
-0+int pas_id;
And the pas_id can be negative too?
Quoted 16 lines
drivers/remoteproc/qcom_q6v5_wcss.c +4
-1+}; +struct q6v5_wcss {struct device *dev;@@ -553,7 +573,8 @@ static int q6v5_wcss_probe(struct platform_device *pdev)if (ret) goto free_rproc; - ret =qcom_q6v5_init (&wcss->q6v5, pdev, rproc,WCSS_CRASH_REASON ,NULL ); + ret =qcom_q6v5_init (&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, + desc->pas_handover);if (ret) goto free_rproc;
drivers/remoteproc/qcom_q6v5_wcss.c static int q6v5_wcss_remove(struct platform_device *pdev) · line 607
Quoted 6 lines
drivers/remoteproc/qcom_q6v5_wcss.c +3
-0@@ -581,8 +602,15 @@ static int q6v5_wcss_remove(struct platform_device *pdev)return 0 ; } +static const struct wcss_data wcss_ipq8074_res_init = { + .firmware_name ="IPQ8074/q6_fw.mdt" , + .crash_reason_smem =421 ,
Why destroy the #define and inline it here? Keep the define around and use it here instead?
drivers/remoteproc/qcom_q6v5_wcss.c static int q6v5_wcss_remove(struct platform_device *pdev) · line 608
Quoted 1 line
drivers/remoteproc/qcom_q6v5_wcss.c +1
-0+ .pas_handover = NULL,
This surely isn't needed to be assigned to NULL.
PATCH v3 6/7 remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
In reply to Govind SinghAdd non PAS WCSS remoteproc driver support for QCS404 SOC. Add WCSS q6 bootup and shutdown sequence handled from Application Processor SubSystem(APSS).
--- .../bindings/remoteproc/qcom,q6v5.txt | 61 ++ drivers/remoteproc/qcom_q6v5_wcss.c | 544 +++++++++++++++++- 2 files changed, 577 insertions(+), 28 deletions(-)
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +61 -0
@@ -13,6 +13,7 @@ on the Qualcomm Hexagon core. "qcom,msm8974-mss-pil" "qcom,msm8996-mss-pil" "qcom,sdm845-mss-pil" + "qcom,qcs404-wcss-pil" - reg: Usage: required
@@ -153,3 +154,63 @@ Hexagon, as it is found on MSM8974 boards. memory-region = <&mpss_region>; }; }; + + remoteproc-wcss { + compatible = "qcom,qcs404-wcss-pil"; + reg = <0x07400000 0x00104>, <0x07500000 0x4e000>; + reg-names = "qdsp6", "q6stop"; + + interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>, + <&gcc GCC_WCSS_Q6_AHB_CBCR_CLK>, + <&gcc GCC_WCSS_Q6_AXIM_CBCR_CLK>, + + <&clock_wcsscc WCSS_AHBFABRIC_CBCR_CLK>, + <&clock_wcsscc WCSS_LCC_CBCR_CLK>, + <&clock_wcsscc WCSS_AHBS_CBCR_CLK>, + <&clock_wcsscc WCSS_TCM_CBCR_CLK>, + <&clock_wcsscc WCSS_AHBM_CBCR_CLK>, + <&clock_wcsscc WCSS_AXIM_CBCR_CLK>, + <&clock_wcsscc WCSS_QDSP6SS_XO_CBCR_CLK>, + <&clock_wcsscc WCSS_QDSP6SS_SLEEP_CBCR_CLK>, + <&clock_wcsscc WCSS_QDSP6SS_GFMMUX_CLK>, + <&clock_wcsscc WCSS_BCR_CBCR_CLK>; + + clock-names = "xo", "gcc_abhs_cbcr", "gcc_axim_cbcr", + "wcss_ahbfabric_cbcr", "wcnss_csr_cbcr", + "wcnss_ahbs_cbcr", "wcnss_tcm_slave_cbcr", + "wcnss_abhm_cbcr", "wcnss_axim_cbcr", + "wcnss_qdsp6ss_xo_cbcr", "wcnss_sleep_cbcr", + "wcnss_core_gfm", "wcss_bcr_cbcr"; + resets = <&gcc GCC_WDSP_RESTART>, + <&clock_wcsscc Q6SSTOP_QDSP6SS_RESET>, + <&clock_wcsscc Q6SSTOP_QDSP6SS_CORE_RESET>, + <&clock_wcsscc Q6SSTOP_QDSP6SS_BUS_RESET>, + <&clock_wcsscc Q6SSTOP_BCR_RESET>; + reset-names = "wcss_reset", "wcss_q6_reset", + "wcss_q6_core_reset", "wcss_q6_bus_reset", + "wcss_q6_bcr_reset"; + + memory-region = <&wlan_fw_mem>; + + qcom,smem-states = <&wcss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + qcom,halt-regs = <&tcsr_wlan_q6 0x18000>; + glink-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <1>; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 16>; + + label = "wcss"; + }; + }; +
drivers/remoteproc/qcom_q6v5_wcss.c +516 -28
701 lines not on this page · raw message
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Stephen Boyd
maintainerRe: [PATCH v3 6/7] remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
Quoting Govind Singh (2018-12-15 02:35:56)
Quoted 18 lines
drivers/remoteproc/qcom_q6v5_wcss.c +4
-0@@ -83,12 +105,32 @@ struct q6v5_wcss {void __iomem *reg_base;void __iomem *rmb_base; +void __iomem *q6stop_base;struct regmap *halt_map;u32 halt_q6;u32 halt_wcss;u32 halt_nc; +struct clk *xo; +struct clk *ahbfabric_cbcr_clk; +struct clk *gcc_abhs_cbcr;
drivers/remoteproc/qcom_q6v5_wcss.c struct q6v5_wcss { · line 127
Quoted 10 lines
drivers/remoteproc/qcom_q6v5_wcss.c +10
-0+struct clk *gcc_axim_cbcr; +struct clk *lcc_csr_cbcr; +struct clk *ahbs_cbcr; +struct clk *tcm_slave_cbcr; +struct clk *qdsp6ss_abhm_cbcr; +struct clk *qdsp6ss_sleep_cbcr; +struct clk *qdsp6ss_axim_cbcr; +struct clk *qdsp6ss_xo_cbcr; +struct clk *qdsp6ss_core_gfmux; +struct clk *wcss_bcr_cbcr;
You should look into clk_bulk_prepare_enable() or just clk_bulk_get_all() to greatly simplify this patch.
Quoted 23 lines
drivers/remoteproc/qcom_q6v5_wcss.c +6
-2+struct regulator *cx_supply; + +struct qcom_rproc_glink glink_subdev; +struct qcom_rproc_ssr ssr_subdev; +struct qcom_sysmon *sysmon; +struct reset_control *wcss_aon_reset;struct reset_control *wcss_reset;struct reset_control *wcss_q6_reset;@@ -99,9 +141,7 @@ struct q6v5_wcss {phys_addr_t mem_reloc;void *mem_region;size_t mem_size; -int crash_reason_smem; -int pas_id;int version; };@@ -245,6 +285,197 @@ static int q6v5_wcss_start(struct rproc *rproc)return ret; }
[...]
Quoted 13 lines
drivers/remoteproc/qcom_q6v5_wcss.c +13
-0+ +/* Assert resets, stop core */ + val =readl (wcss->reg_base +Q6SS_RESET_REG ); + val |=Q6SS_CORE_ARES |Q6SS_BUS_ARES_ENABLE |Q6SS_STOP_CORE ; +writel (val, wcss->reg_base +Q6SS_RESET_REG ); + +/* Program the QDSP6SS PWR_CTL register */ +writel (0x01700000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +writel (0x03700000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +writel (0x03300000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); +
drivers/remoteproc/qcom_q6v5_wcss.c static int q6v5_wcss_start(struct rproc *rproc) · line 377
Quoted 10 lines
drivers/remoteproc/qcom_q6v5_wcss.c +10
-0+writel (0x033C0000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +/* +* Enable memories by turning on the QDSP6 memory foot/head switch, one +* bank at a time to avoid in-rush current +*/ +for (idx =28 ; idx >=0 ; idx--) { +writel ((readl (wcss->reg_base +Q6SS_MEM_PWR_CTL ) | + (1 << idx)), wcss->reg_base +Q6SS_MEM_PWR_CTL ); + }
Smells like it should be in a power domain driver, but I guess it gets a little hard because clks have to be powered on first and in some order.
Quoted 40 lines
drivers/remoteproc/qcom_q6v5_wcss.c +23
-6+ +writel (0x031C0000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); +writel (0x030C0000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + + val =readl (wcss->reg_base +Q6SS_RESET_REG ); + val &= ~Q6SS_CORE_ARES ; +writel (val, wcss->reg_base +Q6SS_RESET_REG ); + +/* Enable the Q6 core clock at the GFM, Q6SSTOP_QDSP6SS_GFMUX_CTL */ + ret =clk_prepare_enable (wcss->qdsp6ss_core_gfmux); +if (ret) + goto disable_gcc_axim_cbcr_clk; + +/* Enable sleep clock branch needed for BCR circuit */ + ret =clk_prepare_enable (wcss->wcss_bcr_cbcr); +if (ret) + goto disable_core_gfmux_clk; + +return 0 ;@@ -475,35 +781,60 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)static int q6v5_wcss_init_mmio (struct q6v5_wcss *wcss,struct platform_device *pdev) { -struct of_phandle_args args; +unsigned int halt_reg[MAX_HALT_REG ] = {0 }; +struct device_node *syscon;struct resource *res;int ret; res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"qdsp6" ); - wcss->reg_base =devm_ioremap_resource (&pdev->dev, res); + wcss->reg_base =devm_ioremap (&pdev->dev, res->start, +resource_size (res));if (IS_ERR (wcss->reg_base))return PTR_ERR (wcss->reg_base); - res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"rmb" ); - wcss->rmb_base =devm_ioremap_resource (&pdev->dev, res); -if (IS_ERR (wcss->rmb_base)) -return PTR_ERR (wcss->rmb_base);
drivers/remoteproc/qcom_q6v5_wcss.c static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss) · line 804
Quoted 10 lines
drivers/remoteproc/qcom_q6v5_wcss.c +10
-0+if (wcss->version ==WCSS_QCS404 ) { + res =platform_get_resource_byname (pdev,IORESOURCE_MEM , +"q6stop" ); +if (!res) { +dev_err (&pdev->dev,"invalid q6stop_base resource\n" ); +return -EINVAL ; + } + + wcss->q6stop_base =devm_ioremap (&pdev->dev, res->start, +resource_size (res));
Why can't devm_ioremap_resource() be used here?
Quoted 18 lines
drivers/remoteproc/qcom_q6v5_wcss.c +11
-3+if (IS_ERR (wcss->q6stop_base)) +return PTR_ERR (wcss->q6stop_base); + }else { + res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"rmb" ); + wcss->rmb_base =devm_ioremap_resource (&pdev->dev, res); +if (IS_ERR (wcss->rmb_base)) +return PTR_ERR (wcss->rmb_base); + } - ret =of_parse_phandle_with_fixed_args (pdev->dev.of_node, -"qcom,halt-regs" ,3 ,0 , &args); -if (ret <0 ) { + syscon =of_parse_phandle (pdev->dev.of_node, +"qcom,halt-regs" ,0 ); +if (!syscon) {dev_err (&pdev->dev,"failed to parse qcom,halt-regs\n" );return -EINVAL ; }
Rob Herring
maintainerRe: [PATCH v3 6/7] remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
In reply to Govind SinghQuoted 7 lines · Govind Singh
Add non PAS WCSS remoteproc driver support for QCS404 SOC. Add WCSS q6 bootup and shutdown sequence handled from Application Processor SubSystem(APSS).
Signed-off-by Govind Singh <[email protected]>--- .../bindings/remoteproc/qcom,q6v5.txt | 61 ++
Please add acks/reviewed-bys when posting new versions.
In the future, please split bindings to a separate patch.
Quoted 2 lines
drivers/remoteproc/qcom_q6v5_wcss.c | 544 +++++++++++++++++- 2 files changed, 577 insertions(+), 28 deletions(-)
PATCH v3 7/7 remoteproc: qcom: wcss: explicitly request exclusive reset control
In reply to Govind SinghUse request exclusive reset control for wcss reset controls.
--- drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/remoteproc/qcom_q6v5_wcss.c +3 -3
@@ -756,20 +756,20 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss,struct device *dev = wcss->dev;if (aon_reset_required) { - wcss->wcss_aon_reset =devm_reset_control_get (dev,"wcss_aon_reset" ); + wcss->wcss_aon_reset =devm_reset_control_get_exclusive (dev,"wcss_aon_reset" );if (IS_ERR (wcss->wcss_aon_reset)) {dev_err (wcss->dev,"fail to acquire wcss_aon_reset\n" );return PTR_ERR (wcss->wcss_aon_reset); } } - wcss->wcss_reset =devm_reset_control_get (dev,"wcss_reset" ); + wcss->wcss_reset =devm_reset_control_get_exclusive (dev,"wcss_reset" );if (IS_ERR (wcss->wcss_reset)) {dev_err (wcss->dev,"unable to acquire wcss_reset\n" );return PTR_ERR (wcss->wcss_reset); } - wcss->wcss_q6_reset =devm_reset_control_get (dev,"wcss_q6_reset" ); + wcss->wcss_q6_reset =devm_reset_control_get_exclusive (dev,"wcss_q6_reset" );if (IS_ERR (wcss->wcss_q6_reset)) {dev_err (wcss->dev,"unable to acquire wcss_q6_reset\n" );return PTR_ERR (wcss->wcss_q6_reset);
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