OMAP: idle path errata fixes

PATCH Superseded Nishanth Menon 4 participants 15 messages Nov 29, 2010 – Dec 2, 2010

Subsystems (4)

Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP power management support

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Nishanth Menon

author

2010-11-29 20:19 UTC #1 lore raw

PATCH v2 1/5 OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all

From: Richard Woodruff <[email protected]>

Analysis in TI kernel with ETM showed that using cache mapped flush in kernel instead of SO mapped flush cost drops by 65% (3.39mS down to 1.17mS) for clean_l2 which is used during sleep sequences. Overall:
- speed up
- unfortunately there isn't a good alternative flush method today
- code reduction and less maintenance and potential bug in unmaintained code

This also fixes the bug with the clean_l2 function usage.

Reported-by Tony Lindgren <[email protected]>

[[email protected]: ported rkw's proposal to 2.6.37-rc2]

Signed-off-by Nishanth Menon <[email protected]>

Signed-off-by Richard Woodruff <[email protected]>

---
v2: typo correction 'reuse'
v1: http://marc.info/?l=linux-omap&m=129013171325210&w=2

 arch/arm/mach-omap2/sleep34xx.S |   79 ++++++--------------------------------
 1 files changed, 13 insertions(+), 66 deletions(-)

arch/arm/mach-omap2/sleep34xx.S +13 ~~-66~~

index 2fb205a..2c20fcf 100644
@@ -520,72 +520,17 @@ clean_caches:
 	cmp	r9, #1 /* Check whether L2 inval is required or not*/
 	bne	skip_l2_inval
 clean_l2:
-	/* read clidr */
-	mrc     p15, 1, r0, c0, c0, 1
-	/* extract loc from clidr */
-	ands    r3, r0, #0x7000000
-	/* left align loc bit field */
-	mov     r3, r3, lsr #23
-	/* if loc is 0, then no need to clean */
-	beq     finished
-	/* start clean at cache level 0 */
-	mov     r10, #0
-loop1:
-	/* work out 3x current cache level */
-	add     r2, r10, r10, lsr #1
-	/* extract cache type bits from clidr*/
-	mov     r1, r0, lsr r2
-	/* mask of the bits for current cache only */
-	and     r1, r1, #7
-	/* see what cache we have at this level */
-	cmp     r1, #2
-	/* skip if no cache, or just i-cache */
-	blt     skip
-	/* select current cache level in cssr */
-	mcr     p15, 2, r10, c0, c0, 0
-	/* isb to sych the new cssr&csidr */
-	isb
-	/* read the new csidr */
-	mrc     p15, 1, r1, c0, c0, 0
-	/* extract the length of the cache lines */
-	and     r2, r1, #7
-	/* add 4 (line length offset) */
-	add     r2, r2, #4
-	ldr     r4, assoc_mask
-	/* find maximum number on the way size */
-	ands    r4, r4, r1, lsr #3
-	/* find bit position of way size increment */
-	clz     r5, r4
-	ldr     r7, numset_mask
-	/* extract max number of the index size*/
-	ands    r7, r7, r1, lsr #13
-loop2:
-	mov     r9, r4
-	/* create working copy of max way size*/
-loop3:
-	/* factor way and cache number into r11 */
-	orr     r11, r10, r9, lsl r5
-	/* factor index number into r11 */
-	orr     r11, r11, r7, lsl r2
-	/*clean & invalidate by set/way */
-	mcr     p15, 0, r11, c7, c10, 2
-	/* decrement the way*/
-	subs    r9, r9, #1
-	bge     loop3
-	/*decrement the index */
-	subs    r7, r7, #1
-	bge     loop2
-skip:
-	add     r10, r10, #2
-	/* increment cache number */
-	cmp     r3, r10
-	bgt     loop1
-finished:
-	/*swith back to cache level 0 */
-	mov     r10, #0
-	/* select current cache level in cssr */
-	mcr     p15, 2, r10, c0, c0, 0
-	isb
+	/*
+	 * Jump out to kernel flush routine
+	 *  - reuse that code is better
+	 *  - it executes in a cached space so is faster than refetch per-block
+	 *  - should be faster and will change with kernel
+	 *  - 'might' have to copy address, load and jump to it
+	 */
+	ldr r1, kernel_flush
+	mov lr, pc
+	bx  r1
+
 skip_l2_inval:
 	/* Data memory barrier and Data sync barrier */
 	mov     r1, #0

@@ -668,5 +613,7 @@ cache_pred_disable_mask:
 	.word	0xFFFFE7FB
 control_stat:
 	.word	CONTROL_STAT
+kernel_flush:
+	.word v7_flush_dcache_all
 ENTRY(omap34xx_cpu_suspend_sz)
 	.word	. - omap34xx_cpu_suspend

Signature · 1 line

1.6.3.3

Nishanth Menon

author

2010-11-29 20:19 UTC #2 lore raw

PATCH v2 2/5 OMAP3: PM: Erratum i581 support: dll kick strategy

In reply to Nishanth Menon

From: Peter 'p2' De Schrijver <[email protected]>

Erratum i581 impacts OMAP3 platforms.
PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing the DPLL not to be locked at times.

IMPORTANT:
*) This is not a complete workaround implementation as recommended by the silicon erratum. this is a support logic for detecting lockups and attempting to recover where possible and is known to provide stability in multiple platforms.
*) This code is mostly important for inactive and retention. The ROM code waits for the maximum dll lock time when resuming from off mode. So for off mode this code isn't really needed.

This should eventually get refactored as part of cleanups to sleep34xx.S

Signed-off-by Peter 'p2' De Schrijver <[email protected]>

---
v2: typo correction- erratum, support, added comment from Peter from the
thread to commit message
v1: http://marc.info/?l=linux-omap&m=129013172525234&w=2

 arch/arm/mach-omap2/sleep34xx.S |   52 +++++++++++++++++++++++++++++++++++---
 1 files changed, 47 insertions(+), 5 deletions(-)

arch/arm/mach-omap2/sleep34xx.S +47 -5

index 2c20fcf..3fbd1e5 100644
@@ -42,6 +42,7 @@
 				OMAP3430_PM_PREPWSTST)
 #define PM_PWSTCTRL_MPU_P	OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
 #define CM_IDLEST1_CORE_V	OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
+#define CM_IDLEST_CKGEN_V	OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
 #define SRAM_BASE_P		0x40200000
 #define CONTROL_STAT		0x480022F0
 #define SCRATCHPAD_MEM_OFFS	0x310 /* Move this as correct place is

@@ -554,31 +555,67 @@ skip_l2_inval:
 
 /* Make sure SDRC accesses are ok */
 wait_sdrc_ok:
+
+/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */
+	ldr	r4, cm_idlest_ckgen
+wait_dpll3_lock:
+	ldr	r5, [r4]
+	tst	r5, #1
+	beq	wait_dpll3_lock
+
         ldr     r4, cm_idlest1_core
+wait_sdrc_ready:
         ldr     r5, [r4]
-        and     r5, r5, #0x2
-        cmp     r5, #0
-        bne     wait_sdrc_ok
+        tst     r5, #0x2
+        bne     wait_sdrc_ready
+	/* allow DLL powerdown upon hw idle req */
         ldr     r4, sdrc_power
         ldr     r5, [r4]
         bic     r5, r5, #0x40
         str     r5, [r4]
-wait_dll_lock:
+is_dll_in_lock_mode:
+
         /* Is dll in lock mode? */
         ldr     r4, sdrc_dlla_ctrl
         ldr     r5, [r4]
         tst     r5, #0x4
         bxne    lr
         /* wait till dll locks */
-        ldr     r4, sdrc_dlla_status
+wait_dll_lock_timed:
+	ldr	r4, wait_dll_lock_counter
+	add	r4, r4, #1
+	str	r4, wait_dll_lock_counter
+	ldr	r4, sdrc_dlla_status
+        mov	r6, #8		/* Wait 20uS for lock */
+wait_dll_lock:
+	subs	r6, r6, #0x1
+	beq	kick_dll
         ldr     r5, [r4]
         and     r5, r5, #0x4
         cmp     r5, #0x4
         bne     wait_dll_lock
         bx      lr
 
+	/* disable/reenable DLL if not locked */
+kick_dll:
+	ldr	r4, sdrc_dlla_ctrl
+	ldr	r5, [r4]
+	mov	r6, r5
+	bic	r6, #(1<<3)	/* disable dll */
+	str	r6, [r4]
+	dsb
+	orr	r6, r6, #(1<<3)	/* enable dll */
+	str	r6, [r4]
+	dsb
+	ldr	r4, kick_counter
+	add	r4, r4, #1
+	str	r4, kick_counter
+	b	wait_dll_lock_timed
+
 cm_idlest1_core:
 	.word	CM_IDLEST1_CORE_V
+cm_idlest_ckgen:
+	.word	CM_IDLEST_CKGEN_V
 sdrc_dlla_status:
 	.word	SDRC_DLLA_STATUS_V
 sdrc_dlla_ctrl:

@@ -615,5 +652,10 @@ control_stat:
 	.word	CONTROL_STAT
 kernel_flush:
 	.word v7_flush_dcache_all
+	/* these 2 words need to be at the end !!! */
+kick_counter:
+	.word	0
+wait_dll_lock_counter:
+	.word	0
 ENTRY(omap34xx_cpu_suspend_sz)
 	.word	. - omap34xx_cpu_suspend

Signature · 1 line

1.6.3.3

Nishanth Menon

author

2010-11-29 20:19 UTC #3 lore raw

PATCH v2 3/5 OMAP3630: PM: Erratum i608: disable RTA

In reply to Nishanth Menon

Erratum id: i608
RTA (Retention Till Access) feature is not supported and leads to device stability issues when enabled. This impacts modules with embedded memories on OMAP3630

Workaround is to disable RTA on boot and coming out of core off. For disabling rta coming out of off mode, we do this by overriding the restore pointer for 3630 to allow us restore handler as the first point of entry before caches are touched and is common for GP and HS devices. to disable earlier than this could be possible by modifying the ppa for HS devices, but not for GP devices.

Signed-off-by Ambresh K <[email protected]>

Signed-off-by Nishanth Menon <[email protected]>

---
v2: fixed missing b restore for 3430 es3.1 code.
introduced erratum handling logic here splitting it out of uart errata typo fixes for erratum
v1: http://marc.info/?l=linux-omap&m=129013172825240&w=2

 arch/arm/mach-omap2/control.c   |    5 ++++-
 arch/arm/mach-omap2/control.h   |    5 +++++
 arch/arm/mach-omap2/pm34xx.c    |   23 +++++++++++++++++++++++
 arch/arm/mach-omap2/sleep34xx.S |   26 ++++++++++++++++++++++++++
 4 files changed, 58 insertions(+), 1 deletions(-)

arch/arm/mach-omap2/control.c +4 -1

index 1fa3294..728f268 100644
@@ -241,7 +241,10 @@ void omap3_save_scratchpad_contents(void)
 
 	/* Populate the Scratchpad contents */
 	scratchpad_contents.boot_config_ptr = 0x0;
-	if (omap_rev() != OMAP3430_REV_ES3_0 &&
+	if (cpu_is_omap3630())
+		scratchpad_contents.public_restore_ptr =
+			virt_to_phys(get_omap3630_restore_pointer());
+	else if (omap_rev() != OMAP3430_REV_ES3_0 &&
 					omap_rev() != OMAP3430_REV_ES3_1)
 		scratchpad_contents.public_restore_ptr =
 			virt_to_phys(get_restore_pointer());

arch/arm/mach-omap2/control.h +5 -0

index b6c6b7c..d7911c5 100644
@@ -204,6 +204,10 @@
 #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
 #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
 
+/* 36xx-only RTA - Retention till Accesss control registers and bits */
+#define OMAP36XX_CONTROL_MEM_RTA_CTRL	0x40C
+#define OMAP36XX_RTA_DISABLE		0x0
+
 /* 34xx D2D idle-related pins, handled by PM core */
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254

@@ -347,6 +351,7 @@ extern void omap3_save_scratchpad_contents(void);
 extern void omap3_clear_scratchpad_contents(void);
 extern u32 *get_restore_pointer(void);
 extern u32 *get_es3_restore_pointer(void);
+extern u32 *get_omap3630_restore_pointer(void);
 extern u32 omap3_arm_context[128];
 extern void omap3_control_save_context(void);
 extern void omap3_control_restore_context(void);

arch/arm/mach-omap2/pm34xx.c +23 -0

index 75c0cd1..bd426cc 100644
@@ -54,6 +54,10 @@
 #define OMAP343X_TABLE_VALUE_OFFSET	   0xc0
 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
 
+#define RTA_ERRATUM_i608		(1 << 0)
+static u16 pm34xx_errata;
+#define IS_PM34XX_ERRATUM(id)		(pm34xx_errata & (id))
+
 struct power_state {
 	struct powerdomain *pwrdm;
 	u32 next_state;

@@ -979,6 +983,14 @@ void omap_push_sram_idle(void)
 				save_secure_ram_context_sz);
 }
 
+static void pm_errata_configure(void)
+{
+	if (cpu_is_omap34xx()) {
+		if (cpu_is_omap3630())
+			pm34xx_errata |= RTA_ERRATUM_i608;
+	}
+}
+
 static int __init omap3_pm_init(void)
 {
 	struct power_state *pwrst, *tmp;

@@ -988,6 +1000,8 @@ static int __init omap3_pm_init(void)
 	if (!cpu_is_omap34xx())
 		return -ENODEV;
 
+	pm_errata_configure();
+
 	printk(KERN_ERR "Power Management for TI OMAP3.\n");
 
 	/* XXX prcm_setup_regs needs to be before enabling hw

@@ -1035,6 +1049,15 @@ static int __init omap3_pm_init(void)
 	pm_idle = omap3_pm_idle;
 	omap3_idle_init();
 
+	/*
+	 * RTA is disabled during initialization as per erratum i608
+	 * it is safer to disable rta by the bootloader, but we would like
+	 * to be doubly sure here and prevent any mishaps.
+	 */
+	if (IS_PM34XX_ERRATUM(RTA_ERRATUM_i608))
+		omap_ctrl_writel(OMAP36XX_RTA_DISABLE,
+			OMAP36XX_CONTROL_MEM_RTA_CTRL);
+
 	clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 		omap3_secure_ram_storage =

arch/arm/mach-omap2/sleep34xx.S +26 -0

index 3fbd1e5..cc3507b 100644
@@ -45,6 +45,8 @@
 #define CM_IDLEST_CKGEN_V	OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
 #define SRAM_BASE_P		0x40200000
 #define CONTROL_STAT		0x480022F0
+#define CONTROL_MEM_RTA_CTRL	(OMAP343X_CTRL_BASE\
+					+ OMAP36XX_CONTROL_MEM_RTA_CTRL)
 #define SCRATCHPAD_MEM_OFFS	0x310 /* Move this as correct place is
 				       * available */
 #define SCRATCHPAD_BASE_P	(OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\

@@ -99,6 +101,14 @@ ENTRY(get_restore_pointer)
         ldmfd   sp!, {pc}     @ restore regs and return
 ENTRY(get_restore_pointer_sz)
         .word   . - get_restore_pointer
+	.text
+/* Function call to get the restore pointer for 3630 resume from OFF */
+ENTRY(get_omap3630_restore_pointer)
+        stmfd   sp!, {lr}     @ save registers on stack
+	adr	r0, restore_3630
+        ldmfd   sp!, {pc}     @ restore regs and return
+ENTRY(get_omap3630_restore_pointer_sz)
+        .word   . - get_omap3630_restore_pointer
 
 	.text
 /* Function call to get the restore pointer for for ES3 to resume from OFF */

@@ -246,6 +256,20 @@ copy_to_sram:
 	bne	copy_to_sram
 	ldr	r1, sram_base
 	blx	r1
+	b	restore
+
+restore_3630:
+	/*b restore_es3630*/		@ Enable to debug restore code
+	ldr	r1, pm_prepwstst_core_p
+	ldr	r2, [r1]
+	and	r2, r2, #0x3
+	cmp	r2, #0x0	@ Check if previous power state of CORE is OFF
+	bne	restore
+	/* Disable rta before giving control */
+	ldr	r1, control_mem_rta
+	mov	r2, #OMAP36XX_RTA_DISABLE
+	str	r2, [r1]
+	/* Fall thru for the remaining logic */
 restore:
 	/* b restore*/  @ Enable to debug restore code
         /* Check what was the reason for mpu reset and store the reason in r9*/

@@ -650,6 +674,8 @@ cache_pred_disable_mask:
 	.word	0xFFFFE7FB
 control_stat:
 	.word	CONTROL_STAT
+control_mem_rta:
+	.word	CONTROL_MEM_RTA_CTRL
 kernel_flush:
 	.word v7_flush_dcache_all
 	/* these 2 words need to be at the end !!! */

Signature · 1 line

1.6.3.3

Varadarajan, Charulatha

2010-11-30 06:07 UTC #4 lore raw

Re: [PATCH 3/5] OMAP3630: PM: Erratum i608: disable RTA

Nishant,

Quoted 5 lines · Nishanth Menon

Erratum id: i608
RTA (Retention Till Access) feature is not supported and leads to device stability issues when enabled. This impacts modules with embedded memories on OMAP3630

Quoted 8 lines

Workaround is to disable RTA on boot and coming out of core off. For disabling rta coming out of off mode, we do this by overriding the restore pointer for 3630 to allow us restore handler as the first point of entry before caches are touched and is common for GP and HS devices. to disable earlier than this could be possible by modifying the ppa for HS devices, but not for GP devices.
Signed-off-by Ambresh K <[email protected]>

not in Cc?

Quoted 68 lines

Signed-off-by Nishanth Menon <[email protected]>

arch/arm/mach-omap2/control.c | 5 ++++- arch/arm/mach-omap2/control.h | 5 +++++ arch/arm/mach-omap2/pm34xx.c | 23 +++++++++++++++++++++++ arch/arm/mach-omap2/sleep34xx.S | 26 ++++++++++++++++++++++++++

 4 files changed, 58 insertions(+), 1 deletions(-)

arch/arm/mach-omap2/control.c +4 -1

index 1fa3294..728f268 100644
@@ -241,7 +241,10 @@ void omap3_save_scratchpad_contents(void)
 
        /* Populate the Scratchpad contents */
        scratchpad_contents.boot_config_ptr = 0x0;
-       if (omap_rev() != OMAP3430_REV_ES3_0 &&
+       if (cpu_is_omap3630())
+               scratchpad_contents.public_restore_ptr =
+                       virt_to_phys(get_omap3630_restore_pointer());
+       else if (omap_rev() != OMAP3430_REV_ES3_0 &&
                                        omap_rev() != OMAP3430_REV_ES3_1)

scratchpad_contents.public_restore_ptr = virt_to_phys(get_restore_pointer());

arch/arm/mach-omap2/control.h +5 -0

index b6c6b7c..d7911c5 100644
@@ -204,6 +204,10 @@
  #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
  #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
 
+/* 36xx-only RTA - Retention till Accesss control registers and bits */
+#define OMAP36XX_CONTROL_MEM_RTA_CTRL  0x40C
+#define OMAP36XX_RTA_DISABLE           0x0
+
  /* 34xx D2D idle-related pins, handled by PM core */
  #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
  #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254

@@ -347,6 +351,7 @@ extern void omap3_save_scratchpad_contents(void);
  extern void omap3_clear_scratchpad_contents(void);
  extern u32 *get_restore_pointer(void);
  extern u32 *get_es3_restore_pointer(void);
+extern u32 *get_omap3630_restore_pointer(void);
  extern u32 omap3_arm_context[128];
  extern void omap3_control_save_context(void);
  extern void omap3_control_restore_context(void);

arch/arm/mach-omap2/pm34xx.c +4 -0

index 75c0cd1..bd426cc 100644
@@ -54,6 +54,10 @@
  #define OMAP343X_TABLE_VALUE_OFFSET       0xc0
  #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
 
+#define RTA_ERRATUM_i608               (1 << 0)
+static u16 pm34xx_errata;
+#define IS_PM34XX_ERRATUM(id)          (pm34xx_errata & (id))
+
  struct power_state {
        struct powerdomain *pwrdm;
        u32 next_state;

arch/arm/mach-omap2/pm34xx.c void omap_push_sram_idle(void) · line 989

Quoted 7 lines

arch/arm/mach-omap2/pm34xx.c +4 -0

@@ -979,6 +983,14 @@ void omap_push_sram_idle(void)
                                save_secure_ram_context_sz);
  }
 
+static void pm_errata_configure(void)
+{
+       if (cpu_is_omap34xx()) {
+               if (cpu_is_omap3630())

Is it required to have both the cpu_is checks*? Why?

arch/arm/mach-omap2/pm34xx.c void omap_push_sram_idle(void) · line 993

Quoted 4 lines

arch/arm/mach-omap2/pm34xx.c +4 -0

+                       pm34xx_errata |= RTA_ERRATUM_i608;
+       }
+}
+

<<snip>>
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Nishanth Menon

author

2010-11-30 14:15 UTC #5 lore raw

Re: [PATCH 3/5] OMAP3630: PM: Erratum i608: disable RTA

Varadarajan, Charulatha had written, on 11/30/2010 12:07 AM, the following:

Quoted 15 lines

Nishant,
Quoted 12 lines · Nishanth Menon
Erratum id: i608
RTA (Retention Till Access) feature is not supported and leads to device stability issues when enabled. This impacts modules with embedded memories on OMAP3630
Workaround is to disable RTA on boot and coming out of core off. For disabling rta coming out of off mode, we do this by overriding the restore pointer for 3630 to allow us restore handler as the first point of entry before caches are touched and is common for GP and HS devices. to disable earlier than this could be possible by modifying the ppa for HS devices, but not for GP devices.

Quoted 3 lines

Quoted 1 line
Signed-off-by Ambresh K <[email protected]>
not in Cc?

It was initially written by me and co-developed with Ambresh and I took it up back again for upstreaming :)

Quoted 72 lines

Signed-off-by Nishanth Menon <[email protected]>

 arch/arm/mach-omap2/control.c   |    5 ++++-
 arch/arm/mach-omap2/control.h   |    5 +++++
 arch/arm/mach-omap2/pm34xx.c    |   23 +++++++++++++++++++++++
 arch/arm/mach-omap2/sleep34xx.S |   26 ++++++++++++++++++++++++++
 4 files changed, 58 insertions(+), 1 deletions(-)

arch/arm/mach-omap2/control.c +4 -1

index 1fa3294..728f268 100644
@@ -241,7 +241,10 @@ void omap3_save_scratchpad_contents(void)
 
       /* Populate the Scratchpad contents */
       scratchpad_contents.boot_config_ptr = 0x0;
-       if (omap_rev() != OMAP3430_REV_ES3_0 &&
+       if (cpu_is_omap3630())
+               scratchpad_contents.public_restore_ptr =
+                       virt_to_phys(get_omap3630_restore_pointer());
+       else if (omap_rev() != OMAP3430_REV_ES3_0 &&
                                       omap_rev() != OMAP3430_REV_ES3_1)
               scratchpad_contents.public_restore_ptr =
                       virt_to_phys(get_restore_pointer());

arch/arm/mach-omap2/control.h +5 -0

index b6c6b7c..d7911c5 100644
@@ -204,6 +204,10 @@
 #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
 #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
 
+/* 36xx-only RTA - Retention till Accesss control registers and bits */
+#define OMAP36XX_CONTROL_MEM_RTA_CTRL  0x40C
+#define OMAP36XX_RTA_DISABLE           0x0
+
 /* 34xx D2D idle-related pins, handled by PM core */
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254

@@ -347,6 +351,7 @@ extern void omap3_save_scratchpad_contents(void);
 extern void omap3_clear_scratchpad_contents(void);
 extern u32 *get_restore_pointer(void);
 extern u32 *get_es3_restore_pointer(void);
+extern u32 *get_omap3630_restore_pointer(void);
 extern u32 omap3_arm_context[128];
 extern void omap3_control_save_context(void);
 extern void omap3_control_restore_context(void);

arch/arm/mach-omap2/pm34xx.c +4 -0

index 75c0cd1..bd426cc 100644
@@ -54,6 +54,10 @@
 #define OMAP343X_TABLE_VALUE_OFFSET       0xc0
 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
 
+#define RTA_ERRATUM_i608               (1 << 0)
+static u16 pm34xx_errata;
+#define IS_PM34XX_ERRATUM(id)          (pm34xx_errata & (id))
+
 struct power_state {
       struct powerdomain *pwrdm;
       u32 next_state;

@@ -979,6 +983,14 @@ void omap_push_sram_idle(void)
                               save_secure_ram_context_sz);
 }

Quoted 6 lines

arch/arm/mach-omap2/pm34xx.c void omap_push_sram_idle(void) · line 989
Quoted 4 lines
arch/arm/mach-omap2/pm34xx.c +4 -0
+static void pm_errata_configure(void)
+{
+       if (cpu_is_omap34xx()) {
+               if (cpu_is_omap3630())
Is it required to have both the cpu_is checks*? Why?

hmm... good point.. pm_init already checks of cpu_is_omap34xx() and returns.. I guess I was simply paranoid -> I will remove this in next rev. thanks.

Signature · 2 lines

Regards,
Nishanth Menon

Nishanth Menon

author

2010-11-29 20:19 UTC #6 lore raw

PATCH v2 4/5 OMAP3630: PM: Disable L2 cache while invalidating L2 cache

In reply to Nishanth Menon

From: Peter 'p2' De Schrijver <[email protected]>

This disables L2 cache before invalidating it and reenables it afterwards. This is be done according to ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from "public side" while, on OMAP3430, this is done in the "secure side".

[[email protected]: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630]

Signed-off-by Nishanth Menon <[email protected]>

Signed-off-by Eduardo Valentin <[email protected]>

Signed-off-by Peter 'p2' De Schrijver <[email protected]>

---
v2: rebased out to this series independent of HS bugfixes
v1: http://marc.info/?l=linux-omap&m=129013171125204&w=2

 arch/arm/mach-omap2/pm.h        |    6 ++++++
 arch/arm/mach-omap2/pm34xx.c    |    3 +++
 arch/arm/mach-omap2/sleep34xx.S |   30 ++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+), 0 deletions(-)

arch/arm/mach-omap2/pm.h +6 -0

index 0d75bfd..aff39d0 100644
@@ -85,4 +85,10 @@ extern unsigned int save_secure_ram_context_sz;
 extern unsigned int omap24xx_cpu_suspend_sz;
 extern unsigned int omap34xx_cpu_suspend_sz;
 
+#if defined(CONFIG_PM)
+extern void enable_omap3630_toggle_l2_on_restore(void);
+#else
+static inline void enable_omap3630_toggle_l2_on_restore(void) { }
+#endif
+
 #endif

arch/arm/mach-omap2/pm34xx.c +3 -0

index bd426cc..e0ade5f 100644
@@ -988,6 +988,9 @@ static void pm_errata_configure(void)
 	if (cpu_is_omap34xx()) {
 		if (cpu_is_omap3630())
 			pm34xx_errata |= RTA_ERRATUM_i608;
+		/* Enable the l2 cache toggling in sleep logic */
+		if (cpu_is_omap3630())
+			enable_omap3630_toggle_l2_on_restore();
 	}
 }

arch/arm/mach-omap2/sleep34xx.S +30 -0

index cc3507b..d2eda01 100644
@@ -111,6 +111,19 @@ ENTRY(get_omap3630_restore_pointer_sz)
         .word   . - get_omap3630_restore_pointer
 
 	.text
+/*
+ * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
+ * This function sets up a fflag that will allow for this toggling to take
+ * place on 3630. Hopefully some version in the future maynot need this
+ */
+ENTRY(enable_omap3630_toggle_l2_on_restore)
+        stmfd   sp!, {lr}     @ save registers on stack
+	/* Setup so that we will disable and enable l2 */
+	mov	r1, #0x1
+	str	r1, l2dis_3630
+        ldmfd   sp!, {pc}     @ restore regs and return
+
+	.text
 /* Function call to get the restore pointer for for ES3 to resume from OFF */
 ENTRY(get_es3_restore_pointer)
 	stmfd	sp!, {lr}	@ save registers on stack

@@ -283,6 +296,14 @@ restore:
         moveq   r9, #0x3        @ MPU OFF => L1 and L2 lost
 	movne	r9, #0x1	@ Only L1 and L2 lost => avoid L2 invalidation
 	bne	logic_l1_restore
+
+	ldr	r0, l2dis_3630
+	cmp	r0, #0x1	@ should we disable L2 on 3630?
+	bne	skipl2dis
+	mrc	p15, 0, r0, c1, c0, 1
+	bic	r0, r0, #2	@ disable L2 cache
+	mcr	p15, 0, r0, c1, c0, 1
+skipl2dis:
 	ldr	r0, control_stat
 	ldr	r1, [r0]
 	and	r1, #0x700

@@ -343,6 +364,13 @@ smi:    .word 0xE1600070		@ Call SMI monitor (smieq)
 	mov	r12, #0x2
 	.word 0xE1600070	@ Call SMI monitor (smieq)
 logic_l1_restore:
+	ldr	r1, l2dis_3630
+	cmp	r1, #0x1	@ Do we need to re-enable L2 on 3630?
+	bne	skipl2reen
+	mrc	p15, 0, r1, c1, c0, 1
+	orr	r1, r1, #2	@ re-enable L2 cache
+	mcr	p15, 0, r1, c1, c0, 1
+skipl2reen:
 	mov	r1, #0
 	/* Invalidate all instruction caches to PoU
 	 * and flush branch target cache */

@@ -678,6 +706,8 @@ control_mem_rta:
 	.word	CONTROL_MEM_RTA_CTRL
 kernel_flush:
 	.word v7_flush_dcache_all
+l2dis_3630:
+	.word 0
 	/* these 2 words need to be at the end !!! */
 kick_counter:
 	.word	0

Signature · 1 line

1.6.3.3

Varadarajan, Charulatha

2010-11-30 06:12 UTC #7 lore raw

Re: [PATCH 4/5 v2] OMAP3630: PM: Disable L2 cache while invalidating L2 cache

Nishant,

Quoted 40 lines · Nishanth Menon

From: Peter 'p2' De Schrijver <[email protected]>
This disables L2 cache before invalidating it and reenables it afterwards. This is be done according to ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from "public side" while, on OMAP3430, this is done in the "secure side".
[[email protected]: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630]
Signed-off-by Nishanth Menon <[email protected]>
Signed-off-by Eduardo Valentin <[email protected]>
Signed-off-by Peter 'p2' De Schrijver <[email protected]>
---
v2: rebased out to this series independent of HS bugfixes
v1: http://marc.info/?l=linux-omap&m=129013171125204&w=2
arch/arm/mach-omap2/pm.h | 6 ++++++ arch/arm/mach-omap2/pm34xx.c | 3 +++ arch/arm/mach-omap2/sleep34xx.S | 30 ++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/pm.h +6 -0
index 0d75bfd..aff39d0 100644
@@ -85,4 +85,10 @@ extern unsigned int save_secure_ram_context_sz;
  extern unsigned int omap24xx_cpu_suspend_sz;
  extern unsigned int omap34xx_cpu_suspend_sz;
 
+#if defined(CONFIG_PM)
+extern void enable_omap3630_toggle_l2_on_restore(void);
+#else
+static inline void enable_omap3630_toggle_l2_on_restore(void) { }
+#endif
+
  #endif
arch/arm/mach-omap2/pm34xx.c +0 -0
index bd426cc..e0ade5f 100644

arch/arm/mach-omap2/pm34xx.c static void pm_errata_configure(void) · line 993

Quoted 6 lines

arch/arm/mach-omap2/pm34xx.c +3 -0

@@ -988,6 +988,9 @@ static void pm_errata_configure(void)
        if (cpu_is_omap34xx()) {
                if (cpu_is_omap3630())
                        pm34xx_errata |= RTA_ERRATUM_i608;
+               /* Enable the l2 cache toggling in sleep logic */
+               if (cpu_is_omap3630())
+                       enable_omap3630_toggle_l2_on_restore();

This can simply be like this:
...
...
- if (cpu_is_omap3630())

+         if (cpu_is_omap3630()) {
                         pm34xx_errata |= RTA_ERRATUM_i608;

+ /* Enable the l2 cache toggling in sleep logic */
+ enable_omap3630_toggle_l2_on_restore();
+ }
...
...

arch/arm/mach-omap2/pm34xx.c static void pm_errata_configure(void) · line 996

Quoted 3 lines

arch/arm/mach-omap2/pm34xx.c +0 -0
        }
  }
 

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Nishanth Menon

author

2010-11-30 14:18 UTC #8 lore raw

Re: [PATCH 4/5 v2] OMAP3630: PM: Disable L2 cache while invalidating L2 cache

Varadarajan, Charulatha had written, on 11/30/2010 12:12 AM, the following:

Quoted 16 lines

arch/arm/mach-omap2/pm34xx.c static void pm_errata_configure(void) · line 993

Quoted 11 lines

arch/arm/mach-omap2/pm34xx.c +3 -0

index bd426cc..e0ade5f 100644
@@ -988,6 +988,9 @@ static void pm_errata_configure(void)
       if (cpu_is_omap34xx()) {
               if (cpu_is_omap3630())
                       pm34xx_errata |= RTA_ERRATUM_i608;
+               /* Enable the l2 cache toggling in sleep logic */
+               if (cpu_is_omap3630())
+                       enable_omap3630_toggle_l2_on_restore();

This can simply be like this:
...
...

arch/arm/mach-omap2/pm34xx.c static void pm_errata_configure(void)

Quoted 6 lines

arch/arm/mach-omap2/pm34xx.c +4 -1

-         if (cpu_is_omap3630())
+         if (cpu_is_omap3630()) {
                         pm34xx_errata |= RTA_ERRATUM_i608;
+                        /* Enable the l2 cache toggling in sleep logic */
+                       enable_omap3630_toggle_l2_on_restore();
+          }

There are two ways to arrange code there:
a) based on silicon revision enable all erratas
b) arrange it per errata case

In the original series there are additional erratas like the uart one which basically makes (a) a dirty implementation. I chose to go with (b). but personally, I am open to either and have no strong feeling abt it. mebbe others can also comment as to which way you'd like to see this organized.

Signature · 2 lines

Regards,
Nishanth Menon

TAO HU

2010-11-30 06:50 UTC #9 lore raw

Re: [PATCH 4/5 v2] OMAP3630: PM: Disable L2 cache while invalidating L2 cache

In reply to Nishanth Menon

Hi, Nishanth Menon
What would happen without this patch? L2 data corruption after back from OFF mode?

Signature · 2 lines

Best Regards
Hu Tao

Quoted 114 lines · Nishanth Menon

From: Peter 'p2' De Schrijver <[email protected]>
This disables L2 cache before invalidating it and reenables it afterwards. This is be done according to ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from "public side" while, on OMAP3430, this is done in the "secure side".
[[email protected]: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630]
Signed-off-by Nishanth Menon <[email protected]>
Signed-off-by Eduardo Valentin <[email protected]>
Signed-off-by Peter 'p2' De Schrijver <[email protected]>
---
v2: rebased out to this series independent of HS bugfixes
v1: http://marc.info/?l=linux-omap&m=129013171125204&w=2
arch/arm/mach-omap2/pm.h | 6 ++++++ arch/arm/mach-omap2/pm34xx.c | 3 +++ arch/arm/mach-omap2/sleep34xx.S | 30 ++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/pm.h +6 -0
index 0d75bfd..aff39d0 100644
@@ -85,4 +85,10 @@ extern unsigned int save_secure_ram_context_sz;
  extern unsigned int omap24xx_cpu_suspend_sz;
  extern unsigned int omap34xx_cpu_suspend_sz;
 
+#if defined(CONFIG_PM)
+extern void enable_omap3630_toggle_l2_on_restore(void);
+#else
+static inline void enable_omap3630_toggle_l2_on_restore(void) { }
+#endif
+
  #endif
arch/arm/mach-omap2/pm34xx.c +3 -0
index bd426cc..e0ade5f 100644
@@ -988,6 +988,9 @@ static void pm_errata_configure(void)
        if (cpu_is_omap34xx()) {
                if (cpu_is_omap3630())
                        pm34xx_errata |= RTA_ERRATUM_i608;
+               /* Enable the l2 cache toggling in sleep logic */
+               if (cpu_is_omap3630())
+                       enable_omap3630_toggle_l2_on_restore();
        }
  }
 
arch/arm/mach-omap2/sleep34xx.S +0 -0
index cc3507b..d2eda01 100644
@@ -111,6 +111,19 @@ ENTRY(get_omap3630_restore_pointer_sz)
.word . - get_omap3630_restore_pointer
.text
arch/arm/mach-omap2/sleep34xx.S +13 -0
+/*
+ * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
+ * This function sets up a fflag that will allow for this toggling to take
+ * place on 3630. Hopefully some version in the future maynot need this
+ */
+ENTRY(enable_omap3630_toggle_l2_on_restore)
+        stmfd   sp!, {lr}     @ save registers on stack
+       /* Setup so that we will disable and enable l2 */
+       mov     r1, #0x1
+       str     r1, l2dis_3630
+        ldmfd   sp!, {pc}     @ restore regs and return
+
+       .text
/* Function call to get the restore pointer for for ES3 to resume from OFF */ ENTRY(get_es3_restore_pointer)
stmfd sp!, {lr} @ save registers on stack
arch/arm/mach-omap2/sleep34xx.S +0 -0
@@ -283,6 +296,14 @@ restore:
moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation bne logic_l1_restore
arch/arm/mach-omap2/sleep34xx.S +8 -0
+
+       ldr     r0, l2dis_3630
+       cmp     r0, #0x1        @ should we disable L2 on 3630?
+       bne     skipl2dis
+       mrc     p15, 0, r0, c1, c0, 1
+       bic     r0, r0, #2      @ disable L2 cache
+       mcr     p15, 0, r0, c1, c0, 1
+skipl2dis:
ldr r0, control_stat
ldr r1, [r0]
and r1, #0x700
arch/arm/mach-omap2/sleep34xx.S +0 -0
@@ -343,6 +364,13 @@ smi:    .word 0xE1600070           @ Call SMI monitor (smieq)
mov r12, #0x2
.word 0xE1600070 @ Call SMI monitor (smieq) logic_l1_restore:
+ ldr r1, l2dis_3630
+ cmp r1, #0x1 @ Do we need to re-enable L2 on 3630?
+ bne skipl2reen
+ mrc p15, 0, r1, c1, c0, 1
+ orr r1, r1, #2 @ re-enable L2 cache
+ mcr p15, 0, r1, c1, c0, 1
+skipl2reen:
mov r1, #0
/* Invalidate all instruction caches to PoU
* and flush branch target cache */
arch/arm/mach-omap2/sleep34xx.S +0 -0
@@ -678,6 +706,8 @@ control_mem_rta:
.word CONTROL_MEM_RTA_CTRL kernel_flush:
.word v7_flush_dcache_all +l2dis_3630:
+ .word 0
/* these 2 words need to be at the end !!! */ kick_counter:
.word 0
--
1.6.3.3

Quoted 5 lines

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Nishanth Menon

author

2010-11-30 14:18 UTC #10 lore raw

Re: [PATCH 4/5 v2] OMAP3630: PM: Disable L2 cache while invalidating L2 cache

TAO HU had written, on 11/30/2010 12:03 AM, the following:

Quoted 3 lines

What would happen without this patch? L2 data corruption after back from OFF mode?

I believe yes.

Signature · 2 lines

Regards,
Nishanth Menon

TAO HU

2010-12-01 08:56 UTC #11 lore raw

Re: [PATCH 4/5 v2] OMAP3630: PM: Disable L2 cache while invalidating L2 cache

Hi, Nishanth Menon

One more question.

Do we need to implement the same thing in bootloader?
I.e. Do we need to disable L2 prior invalidating L2 for OMAP3630 1st boot up?

Quoted 11 lines · Nishanth Menon

TAO HU had written, on 11/30/2010 12:03 AM, the following:
Quoted 4 lines
What would happen without this patch? L2 data corruption after back from OFF mode?
I believe yes.
--
Regards,
Nishanth Menon

Signature · 2 lines

Best Regards
Hu Tao

Nishanth Menon

author

2010-12-01 14:39 UTC #12 lore raw

Re: [PATCH 4/5 v2] OMAP3630: PM: Disable L2 cache while invalidating L2 cache

TAO HU had written, on 12/01/2010 02:56 AM, the following:

Quoted 2 lines

Do we need to implement the same thing in bootloader?
I.e. Do we need to disable L2 prior invalidating L2 for OMAP3630 1st boot up?

Though out of context for this email list (linux kernel :)), I believe it wont hurt to do this as a standard procedure.
---
Regards,
Nishanth Menon

Santosh Shilimkar

2010-12-02 05:05 UTC #13 lore raw

RE: [PATCH 4/5 v2] OMAP3630: PM: Disable L2 cache while invalidating L2 cache

Quoted 9 lines

-----Original Message-----
From: [email protected] [mailto:linux-omap- [email protected]] On Behalf Of Nishanth Menon
Sent: Wednesday, December 01, 2010 8:09 PM
To: TAO HU
Cc: TAO HU; linux-omap; Jean; Tony; Kevin; Vishwa
Subject: Re: [PATCH 4/5 v2] OMAP3630: PM: Disable L2 cache while invalidating L2 cache

Quoted 6 lines

TAO HU had written, on 12/01/2010 02:56 AM, the following:
Quoted 2 lines
Do we need to implement the same thing in bootloader?
I.e. Do we need to disable L2 prior invalidating L2 for OMAP3630 1st
boot up?
Though out of context for this email list (linux kernel :)), I believe it wont hurt to do this as a standard procedure.

You should always invalidate the cache before enabling it. Now if at the 1st boot-up if the ROM code / boot-loader is doing this, you don't have do it.

At least from kernel point of it's responsibility of boot-loaders/boot-straps to keep the caches invalidated. That's why the generic kernel don't invalidate them before enabling them.

RMK has documeneted this. Read " 2. Loader Checks"
http://www.arm.linux.org.uk/developer/noboot-checklist/

Regards,
Santosh

Nishanth Menon

author

2010-11-29 20:19 UTC #14 lore raw

PATCH v2 5/5 OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2

In reply to Nishanth Menon

From: Eduardo Valentin <[email protected]>

Limitation i583: Self_Refresh Exit issue after OFF mode

Issue:
When device is waking up from OFF mode, then SDRC state machine sends inappropriate sequence violating JEDEC standards.

Impact:
OMAP3630 < ES1.2 is impacted as follows depending on the platform:
CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable, while
for all other sysclk frequencies, varied levels of instability seen based on varied parameters.
CS1: impacted

This patch takes option #3 as recommended by the Silicon erratum:
Avoid core power domain transitioning to OFF mode. Power consumption impact is expected in this case.
To do this, we route OFF requests to RET request on the impacted revisions of silicon.

[[email protected]: rebased the code to 2.6.37-rc2- short circuit code changed a bit]

Signed-off-by Nishanth Menon <[email protected]>

Signed-off-by Eduardo Valentin <[email protected]>

---
v2: rebased to this patch series instead of depending on hs changes
fix typo for macro definition
v1: http://marc.info/?l=linux-omap&m=129013173425266&w=2

 arch/arm/mach-omap2/pm34xx.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

arch/arm/mach-omap2/pm34xx.c +14 -0

index e0ade5f..6f33631 100644
@@ -55,6 +55,7 @@
 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
 
 #define RTA_ERRATUM_i608		(1 << 0)
+#define SDRC_WAKEUP_ERRATUM_i583	(1 << 1)
 static u16 pm34xx_errata;
 #define IS_PM34XX_ERRATUM(id)		(pm34xx_errata & (id))

@@ -399,6 +400,17 @@ void omap_sram_idle(void)
 	}
 
 	/* CORE */
+	/*
+	 * Erratum i583: implementation for ES rev < Es1.2 on 3630
+	 * We cannot enable OFF mode in a stable form for previous
+	 * revisions, transition instead to RET
+	 */
+	if (IS_PM34XX_ERRATUM(SDRC_WAKEUP_ERRATUM_i583) &&
+			(core_next_state == PWRDM_POWER_OFF)) {
+		pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
+		core_next_state = PWRDM_POWER_RET;
+	}
+
 	if (core_next_state < PWRDM_POWER_ON) {
 		omap_uart_prepare_idle(0);
 		omap_uart_prepare_idle(1);

@@ -991,6 +1003,8 @@ static void pm_errata_configure(void)
 		/* Enable the l2 cache toggling in sleep logic */
 		if (cpu_is_omap3630())
 			enable_omap3630_toggle_l2_on_restore();
+		if (cpu_is_omap3630() && (omap_rev() < OMAP3630_REV_ES1_2))
+			pm34xx_errata |= SDRC_WAKEUP_ERRATUM_i583;
 	}
 }

Signature · 1 line

1.6.3.3