OMAP: Adding Smartreflex and Voltage driver support

index b6c6b7c..fef6bcc 100644
@@ -148,6 +148,15 @@
 #define OMAP343X_CONTROL_TEST_KEY_11	(OMAP2_CONTROL_GENERAL + 0x00f4)
 #define OMAP343X_CONTROL_TEST_KEY_12	(OMAP2_CONTROL_GENERAL + 0x00f8)
 #define OMAP343X_CONTROL_TEST_KEY_13	(OMAP2_CONTROL_GENERAL + 0x00fc)
+#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
+#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
+#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
+#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
+#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
+#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
+#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
+#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
+#define OMAP343X_CONTROL_FUSE_SR        (OMAP2_CONTROL_GENERAL + 0x0130)
 #define OMAP343X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)
 #define OMAP343X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)
 #define OMAP343X_CONTROL_DEBOBS(i)	(OMAP2_CONTROL_GENERAL + 0x01B0 \

@@ -164,6 +173,14 @@
 #define OMAP343X_CONTROL_SRAMLDO5	(OMAP2_CONTROL_GENERAL + 0x02C0)
 #define OMAP343X_CONTROL_CSI		(OMAP2_CONTROL_GENERAL + 0x02C4)
 
+/* OMAP3630 only CONTROL_GENERAL register offsets */
+#define OMAP3630_CONTROL_FUSE_OPP1G_VDD1        (OMAP2_CONTROL_GENERAL + 0x0110)
+#define OMAP3630_CONTROL_FUSE_OPP50_VDD1        (OMAP2_CONTROL_GENERAL + 0x0114)
+#define OMAP3630_CONTROL_FUSE_OPP100_VDD1       (OMAP2_CONTROL_GENERAL + 0x0118)
+#define OMAP3630_CONTROL_FUSE_OPP120_VDD1       (OMAP2_CONTROL_GENERAL + 0x0120)
+#define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
+#define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
+
 /* AM35XX only CONTROL_GENERAL register offsets */
 #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
 #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)

index 6ec2ee1..1648a14 100644
@@ -20,6 +20,7 @@
 
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
+#include <plat/voltage.h>
 
 static struct omap_device_pm_latency *pm_lats;
 

@@ -145,3 +146,10 @@ static int __init omap2_common_pm_init(void)
 }
 postcore_initcall(omap2_common_pm_init);
 
+static int __init omap2_common_pm_late_init(void)
+{
+	omap_voltage_late_init();
+
+	return 0;
+}
+late_initcall(omap2_common_pm_late_init);

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index 7eaa8ed..9567aee 100644
@@ -34,6 +34,7 @@
 #include <linux/ioport.h>
 #include <linux/mutex.h>
 #include <plat/cpu.h>
+#include <plat/voltage.h>
 
 struct omap_device;
 

@@ -436,6 +437,8 @@ struct omap_hwmod_class {
  * @main_clk: main clock: OMAP clock name
  * @_clk: pointer to the main struct clk (filled in at runtime)
  * @opt_clks: other device clocks that drivers can request (0..*)
+ * @vdd_name: voltage domain name
+ * @voltdm: pointer to voltage domain (filled in at runtime)
  * @masters: ptr to array of OCP ifs that this hwmod can initiate on
  * @slaves: ptr to array of OCP ifs that this hwmod can respond on
  * @dev_attr: arbitrary device attributes that can be passed to the driver

@@ -479,6 +482,8 @@ struct omap_hwmod {
 	const char			*main_clk;
 	struct clk			*_clk;
 	struct omap_hwmod_opt_clk	*opt_clks;
+	char				*vdd_name;
+	struct voltagedomain		*voltdm;
 	struct omap_hwmod_ocp_if	**masters; /* connect to *_IA */
 	struct omap_hwmod_ocp_if	**slaves;  /* connect to *_TA */
 	void				*dev_attr;

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index 1648a14..7c64533 100644
@@ -22,6 +22,8 @@
 #include <plat/clockdomain.h>
 #include <plat/voltage.h>
 
+#include "pm.h"
+
 static struct omap_device_pm_latency *pm_lats;
 
 static struct device *mpu_dev;

@@ -149,6 +151,7 @@ postcore_initcall(omap2_common_pm_init);
 static int __init omap2_common_pm_late_init(void)
 {
 	omap_voltage_late_init();
+	omap_devinit_smartreflex();
 
 	return 0;
 }

index a43e069..b19d46e 100644
@@ -11,6 +11,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PM_H
 #define __ARCH_ARM_MACH_OMAP2_PM_H
 
+#include <linux/err.h>
 #include <plat/powerdomain.h>
 
 extern void *omap3_secure_ram_storage;

@@ -99,4 +100,15 @@ extern unsigned int save_secure_ram_context_sz;
 extern unsigned int omap24xx_cpu_suspend_sz;
 extern unsigned int omap34xx_cpu_suspend_sz;
 
+#ifdef CONFIG_OMAP_SMARTREFLEX
+extern int omap_devinit_smartreflex(void);
+extern void omap_enable_smartreflex_on_init(void);
+#else
+static inline int omap_devinit_smartreflex(void)
+{
+	return -EINVAL;
+}
+
+static inline void omap_enable_smartreflex_on_init(void) {}
+#endif
 #endif

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index cb97ecf..4ff9244 100644
@@ -18,6 +18,7 @@
 #include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
+#include <plat/smartreflex.h>
 
 #include "omap_hwmod_common_data.h"
 

@@ -39,6 +40,8 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod;
 static struct omap_hwmod omap3xxx_l4_core_hwmod;
 static struct omap_hwmod omap3xxx_l4_per_hwmod;
 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
+static struct omap_hwmod omap34xx_sr1_hwmod;
+static struct omap_hwmod omap34xx_sr2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {

@@ -169,9 +172,47 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
+	{
+		.pa_start	= OMAP34XX_SR1_BASE,
+		.pa_end		= OMAP34XX_SR1_BASE + SZ_1K - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap34xx_sr1_hwmod,
+	.clk		= "sr_l4_ick",
+	.addr		= omap3_sr1_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap3_sr1_addr_space),
+	.user		= OCP_USER_MPU,
+};
+
+/* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
+	{
+		.pa_start	= OMAP34XX_SR2_BASE,
+		.pa_end		= OMAP34XX_SR2_BASE + SZ_1K - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap34xx_sr2_hwmod,
+	.clk		= "sr_l4_ick",
+	.addr		= omap3_sr2_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap3_sr2_addr_space),
+	.user		= OCP_USER_MPU,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 	&omap3xxx_l3_main__l4_core,
+	&omap3_l4_core__sr1,
+	&omap3_l4_core__sr2,
 };
 
 /* Master interfaces on the L4_CORE interconnect */

@@ -509,6 +550,135 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 
+/* SR common */
+static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
+	.clkact_shift	= 20,
+};
+
+static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
+	.sysc_offs	= 0x24,
+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
+	.clockact	= CLOCKACT_TEST_ICLK,
+	.sysc_fields	= &omap34xx_sr_sysc_fields,
+};
+
+static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
+	.name = "smartreflex",
+	.sysc = &omap34xx_sr_sysc,
+	.rev  = 1,
+};
+
+static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
+	.sidle_shift	= 24,
+	.enwkup_shift	= 26
+};
+
+static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
+	.sysc_offs	= 0x38,
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+			SYSC_NO_CACHE),
+	.sysc_fields	= &omap36xx_sr_sysc_fields,
+};
+
+static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
+	.name = "smartreflex",
+	.sysc = &omap36xx_sr_sysc,
+	.rev  = 2,
+};
+
+/* SR1 */
+static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
+	&omap3_l4_core__sr1,
+};
+
+static struct omap_hwmod omap34xx_sr1_hwmod = {
+	.name		= "sr1_hwmod",
+	.class		= &omap34xx_smartreflex_hwmod_class,
+	.main_clk	= "sr1_fck",
+	.vdd_name	= "mpu",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_EN_SR1_SHIFT,
+			.module_offs = WKUP_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
+		},
+	},
+	.slaves		= omap3_sr1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap3_sr1_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
+					CHIP_IS_OMAP3430ES3_0 |
+					CHIP_IS_OMAP3430ES3_1),
+	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
+};
+
+static struct omap_hwmod omap36xx_sr1_hwmod = {
+	.name		= "sr1_hwmod",
+	.class		= &omap36xx_smartreflex_hwmod_class,
+	.main_clk	= "sr1_fck",
+	.vdd_name	= "mpu",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_EN_SR1_SHIFT,
+			.module_offs = WKUP_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
+		},
+	},
+	.slaves		= omap3_sr1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap3_sr1_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+};
+
+/* SR2 */
+static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
+	&omap3_l4_core__sr2,
+};
+
+static struct omap_hwmod omap34xx_sr2_hwmod = {
+	.name		= "sr2_hwmod",
+	.class		= &omap34xx_smartreflex_hwmod_class,
+	.main_clk	= "sr2_fck",
+	.vdd_name	= "core",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_EN_SR2_SHIFT,
+			.module_offs = WKUP_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
+		},
+	},
+	.slaves		= omap3_sr2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap3_sr2_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
+					CHIP_IS_OMAP3430ES3_0 |
+					CHIP_IS_OMAP3430ES3_1),
+	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
+};
+
+static struct omap_hwmod omap36xx_sr2_hwmod = {
+	.name		= "sr2_hwmod",
+	.class		= &omap36xx_smartreflex_hwmod_class,
+	.main_clk	= "sr2_fck",
+	.vdd_name	= "core",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_EN_SR2_SHIFT,
+			.module_offs = WKUP_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
+		},
+	},
+	.slaves		= omap3_sr2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap3_sr2_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 	&omap3xxx_l3_main_hwmod,
 	&omap3xxx_l4_core_hwmod,

@@ -521,6 +691,10 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 	&omap3xxx_uart2_hwmod,
 	&omap3xxx_uart3_hwmod,
 	&omap3xxx_uart4_hwmod,
+	&omap34xx_sr1_hwmod,
+	&omap34xx_sr2_hwmod,
+	&omap36xx_sr1_hwmod,
+	&omap36xx_sr2_hwmod,
 	NULL,
 };
 

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index 35275ba..b895ceb 100644
@@ -1046,6 +1046,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 	/* Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
 	 * Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
 	 * SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
+	 * Also enable the smartreflex I2S bit.
 	 */
 
 	if (twl_class_is_4030()) {

@@ -1053,6 +1054,18 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		temp &= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \
 		I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
 		twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
+
+		/* The smartreflex bit on twl4030 needs to be enabled by
+		 * default irrespective of whether smartreflex module is
+		 * enabled on the OMAP side or not. This is because without
+		 * this bit enabled the voltage scaling through
+		 * vp forceupdate does not function properly.
+		 */
+		twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
+			TWL4030_PM_RECEIVER_DCDC_GLOBAL_CFG);
+		temp |= SMARTREFLEX_ENABLE;
+		twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+			TWL4030_PM_RECEIVER_DCDC_GLOBAL_CFG);
 	}
 
 	status = add_children(pdata, id->driver_data);

index c760991..d392f06 100644
@@ -434,6 +434,17 @@ static inline int twl6030_mmc_card_detect(struct device *dev, int slot)
 
 /*----------------------------------------------------------------------*/
 
+/*
+ * PM Receiver module register offsets (use TWL4030_MODULE_PM_RECEIVER)
+ */
+
+#define TWL4030_PM_RECEIVER_DCDC_GLOBAL_CFG	0x06
+
+/* Smartreflex I2S bus enable/ vmode enable bit */
+#define SMARTREFLEX_ENABLE			BIT(3)
+
+/*----------------------------------------------------------------------*/
+
 /* Power bus message definitions */
 
 /* The TWL4030/5030 splits its power-management resources (the various

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index 7c64533..6c161a3 100644
@@ -150,7 +150,11 @@ postcore_initcall(omap2_common_pm_init);
 
 static int __init omap2_common_pm_late_init(void)
 {
+	/* Init the OMAP TWL parameters */
+	omap3_twl_init();
+	/* Init the voltage layer */
 	omap_voltage_late_init();
+	/* Smartreflex device init */
 	omap_devinit_smartreflex();
 
 	return 0;

index b19d46e..0c83b8b 100644
@@ -111,4 +111,14 @@ static inline int omap_devinit_smartreflex(void)
 
 static inline void omap_enable_smartreflex_on_init(void) {}
 #endif
+
+#ifdef CONFIG_TWL4030_CORE
+extern int omap3_twl_init(void);
+#else
+static inline int omap3_twl_init(void)
+{
+	return -EINVAL;
+}
+#endif
+
 #endif

index eee23d0..52a05b3 100644
@@ -31,6 +31,7 @@
 #include "pm.h"
 
 #define SMARTREFLEX_NAME_LEN	16
+#define NVALUE_NAME_LEN		40
 #define SR_DISABLE_TIMEOUT	200
 
 struct omap_sr {

@@ -817,8 +818,9 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 	struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
 	struct omap_sr_data *pdata = pdev->dev.platform_data;
 	struct resource *mem, *irq;
-	struct dentry *vdd_dbg_dir, *dbg_dir;
-	int ret = 0;
+	struct dentry *vdd_dbg_dir, *dbg_dir, *nvalue_dir;
+	struct omap_volt_data *volt_data;
+	int i, ret = 0;
 
 	if (!sr_info) {
 		dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",

@@ -897,6 +899,46 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 
 	(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir,
 				(void *)sr_info, &pm_sr_fops);
+	(void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir,
+			&sr_info->err_weight);
+	(void) debugfs_create_x32("errmaxlimit", S_IRUGO, dbg_dir,
+			&sr_info->err_maxlimit);
+	(void) debugfs_create_x32("errminlimit", S_IRUGO, dbg_dir,
+			&sr_info->err_minlimit);
+
+	nvalue_dir = debugfs_create_dir("nvalue", dbg_dir);
+	if (IS_ERR(nvalue_dir)) {
+		dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
+			"for n-values\n", __func__);
+		return PTR_ERR(nvalue_dir);
+	}
+
+	omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
+	if (!volt_data) {
+		dev_warn(&pdev->dev, "%s: No Voltage table for the"
+			" corresponding vdd vdd_%s. Cannot create debugfs"
+			"entries for n-values\n",
+			__func__, sr_info->voltdm->name);
+		return -ENODATA;
+	}
+
+	for (i = 0; i < sr_info->nvalue_count; i++) {
+		char *name;
+		char volt_name[32];
+
+		name = kzalloc(NVALUE_NAME_LEN + 1, GFP_KERNEL);
+		if (!name) {
+			dev_err(&pdev->dev, "%s: Unable to allocate memory"
+				" for n-value directory name\n",  __func__);
+			return -ENOMEM;
+		}
+
+		strcpy(name, "volt_");
+		sprintf(volt_name, "%d", volt_data[i].volt_nominal);
+		strcat(name, volt_name);
+		(void) debugfs_create_x32(name, S_IRUGO | S_IWUGO, nvalue_dir,
+				&(sr_info->nvalue_table[i].nvalue));
+	}
 
 	return ret;
 

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index 6c161a3..819cf42 100644
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/err.h>
+#include <linux/opp.h>
 
 #include <plat/omap-pm.h>
 #include <plat/omap_device.h>

@@ -139,6 +140,76 @@ err:
 	return ret;
 }
 
+/*
+ * This API is to be called during init to put the various voltage
+ * domains to the voltage as per the opp table. Typically we boot up
+ * at the nominal voltage. So this function finds out the rate of
+ * the clock associated with the voltage domain, finds out the correct
+ * opp entry and puts the voltage domain to the voltage specifies
+ * in the opp entry
+ */
+static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
+						struct device *dev)
+{
+	struct voltagedomain *voltdm;
+	struct clk *clk;
+	struct opp *opp;
+	unsigned long freq, bootup_volt;
+
+	if (!vdd_name || !clk_name || !dev) {
+		printk(KERN_ERR "%s: Invalid parameters!\n", __func__);
+		goto exit;
+	}
+
+	voltdm = omap_voltage_domain_lookup(vdd_name);
+	if (IS_ERR(voltdm)) {
+		printk(KERN_ERR "%s: Unable to get vdd pointer for vdd_%s\n",
+			__func__, vdd_name);
+		goto exit;
+	}
+
+	clk =  clk_get(NULL, clk_name);
+	if (IS_ERR(clk)) {
+		printk(KERN_ERR "%s: unable to get clk %s\n",
+			__func__, clk_name);
+		goto exit;
+	}
+
+	freq = clk->rate;
+	clk_put(clk);
+
+	opp = opp_find_freq_ceil(dev, &freq);
+	if (IS_ERR(opp)) {
+		printk(KERN_ERR "%s: unable to find boot up OPP for vdd_%s\n",
+			__func__, vdd_name);
+		goto exit;
+	}
+
+	bootup_volt = opp_get_voltage(opp);
+	if (!bootup_volt) {
+		printk(KERN_ERR "%s: unable to find voltage corresponding"
+			"to the bootup OPP for vdd_%s\n", __func__, vdd_name);
+		goto exit;
+	}
+
+	omap_voltage_scale_vdd(voltdm, bootup_volt);
+	return 0;
+
+exit:
+	printk(KERN_ERR "%s: Unable to put vdd_%s to its init voltage\n\n",
+		__func__, vdd_name);
+	return -EINVAL;
+}
+
+static void __init omap3_init_voltages(void)
+{
+	if (!cpu_is_omap34xx())
+		return;
+
+	omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev);
+	omap2_set_init_voltage("core", "l3_ick", l3_dev);
+}
+
 static int __init omap2_common_pm_init(void)
 {
 	omap2_init_processor_devices();

@@ -152,8 +223,13 @@ static int __init omap2_common_pm_late_init(void)
 {
 	/* Init the OMAP TWL parameters */
 	omap3_twl_init();
+
 	/* Init the voltage layer */
 	omap_voltage_late_init();
+
+	/* Initialize the voltages */
+	omap3_init_voltages();
+
 	/* Smartreflex device init */
 	omap_devinit_smartreflex();
 

index 6e91748..f28c778 100644
@@ -150,6 +150,8 @@ struct omap_vdd_info {
 	bool vp_enabled;
 	int (*volt_scale) (struct omap_vdd_info *vdd,
 		unsigned long target_volt);
+	u32 (*read_reg)(s16 inst, u16 idx);
+	u32 (*write_reg)(u32 val, s16 inst, u16 idx);
 };
 
 static struct omap_vdd_info *vdd_info;

@@ -321,7 +323,7 @@ static int vp_volt_debug_get(void *data, u64 *val)
 		return -EINVAL;
 	}
 
-	vsel = prm_read_mod_reg(vdd->vp_reg.prm_mod, vdd->vp_offs.voltage);
+	vsel = vdd->read_reg(vdd->vp_reg.prm_mod, vdd->vp_offs.voltage);
 	pr_notice("curr_vsel = %x\n", vsel);
 
 	if (!vdd->pmic_info->vsel_to_uv) {

@@ -375,19 +377,19 @@ static void vp_latch_vsel(struct omap_vdd_info *vdd)
 
 	vsel = vdd->pmic_info->uv_to_vsel(uvdc);
 
-	vpconfig = prm_read_mod_reg(mod, vdd->vp_offs.vpconfig);
+	vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
 	vpconfig &= ~(vdd->vp_reg.vpconfig_initvoltage_mask |
 			vdd->vp_reg.vpconfig_initvdd);
 	vpconfig |= vsel << vdd->vp_reg.vpconfig_initvoltage_shift;
 
-	prm_write_mod_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+	vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
 
 	/* Trigger initVDD value copy to voltage processor */
-	prm_write_mod_reg((vpconfig | vdd->vp_reg.vpconfig_initvdd), mod,
+	vdd->write_reg((vpconfig | vdd->vp_reg.vpconfig_initvdd), mod,
 			vdd->vp_offs.vpconfig);
 
 	/* Clear initVDD copy trigger bit */
-	prm_write_mod_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+	vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
 }
 
 /* Generic voltage init functions */

@@ -402,19 +404,19 @@ static void __init vp_init(struct omap_vdd_info *vdd)
 		(vdd->vp_reg.vpconfig_errorgain <<
 		vdd->vp_reg.vpconfig_errorgain_shift) |
 		vdd->vp_reg.vpconfig_timeouten;
-	prm_write_mod_reg(vp_val, mod, vdd->vp_offs.vpconfig);
+	vdd->write_reg(vp_val, mod, vdd->vp_offs.vpconfig);
 
 	vp_val = ((vdd->vp_reg.vstepmin_smpswaittimemin <<
 		vdd->vp_reg.vstepmin_smpswaittimemin_shift) |
 		(vdd->vp_reg.vstepmin_stepmin <<
 		vdd->vp_reg.vstepmin_stepmin_shift));
-	prm_write_mod_reg(vp_val, mod, vdd->vp_offs.vstepmin);
+	vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmin);
 
 	vp_val = ((vdd->vp_reg.vstepmax_smpswaittimemax <<
 		vdd->vp_reg.vstepmax_smpswaittimemax_shift) |
 		(vdd->vp_reg.vstepmax_stepmax <<
 		vdd->vp_reg.vstepmax_stepmax_shift));
-	prm_write_mod_reg(vp_val, mod, vdd->vp_offs.vstepmax);
+	vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmax);
 
 	vp_val = ((vdd->vp_reg.vlimitto_vddmax <<
 		vdd->vp_reg.vlimitto_vddmax_shift) |

@@ -422,7 +424,7 @@ static void __init vp_init(struct omap_vdd_info *vdd)
 		vdd->vp_reg.vlimitto_vddmin_shift) |
 		(vdd->vp_reg.vlimitto_timeout <<
 		vdd->vp_reg.vlimitto_timeout_shift));
-	prm_write_mod_reg(vp_val, mod, vdd->vp_offs.vlimitto);
+	vdd->write_reg(vp_val, mod, vdd->vp_offs.vlimitto);
 }
 
 static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)

@@ -503,23 +505,23 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
 		volt_data = NULL;
 
 	*target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
-	*current_vsel = prm_read_mod_reg(vp_mod, vdd->vp_offs.voltage);
+	*current_vsel = vdd->read_reg(vp_mod, vdd->vp_offs.voltage);
 
 	/* Setting the ON voltage to the new target voltage */
-	vc_cmdval = prm_read_mod_reg(vc_mod, vdd->vc_reg.cmdval_reg);
+	vc_cmdval = vdd->read_reg(vc_mod, vdd->vc_reg.cmdval_reg);
 	vc_cmdval &= ~vdd->vc_reg.cmd_on_mask;
 	vc_cmdval |= (*target_vsel << vdd->vc_reg.cmd_on_shift);
-	prm_write_mod_reg(vc_cmdval, vc_mod, vdd->vc_reg.cmdval_reg);
+	vdd->write_reg(vc_cmdval, vc_mod, vdd->vc_reg.cmdval_reg);
 
 	/* Setting vp errorgain based on the voltage */
 	if (volt_data) {
-		vp_errgain_val = prm_read_mod_reg(vp_mod,
+		vp_errgain_val = vdd->read_reg(vp_mod,
 				vdd->vp_offs.vpconfig);
 		vdd->vp_reg.vpconfig_errorgain = volt_data->vp_errgain;
 		vp_errgain_val &= ~vdd->vp_reg.vpconfig_errorgain_mask;
 		vp_errgain_val |= vdd->vp_reg.vpconfig_errorgain <<
 				vdd->vp_reg.vpconfig_errorgain_shift;
-		prm_write_mod_reg(vp_errgain_val, vp_mod,
+		vdd->write_reg(vp_errgain_val, vp_mod,
 				vdd->vp_offs.vpconfig);
 	}
 

@@ -564,10 +566,10 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
 			(vdd->pmic_info->i2c_slave_addr <<
 			vdd->vc_reg.slaveaddr_shift);
 
-	prm_write_mod_reg(vc_bypass_value, mod, vc_bypass_val_reg);
-	prm_write_mod_reg(vc_bypass_value | vc_valid, mod, vc_bypass_val_reg);
+	vdd->write_reg(vc_bypass_value, mod, vc_bypass_val_reg);
+	vdd->write_reg(vc_bypass_value | vc_valid, mod, vc_bypass_val_reg);
 
-	vc_bypass_value = prm_read_mod_reg(mod, vc_bypass_val_reg);
+	vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg);
 	/*
 	 * Loop till the bypass command is acknowledged from the SMPS.
 	 * NOTE: This is legacy code. The loop count and retry count needs

@@ -586,7 +588,7 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
 			loop_cnt = 0;
 			udelay(10);
 		}
-		vc_bypass_value = prm_read_mod_reg(mod, vc_bypass_val_reg);
+		vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg);
 	}
 
 	_post_volt_scale(vdd, target_volt, target_vsel, current_vsel);

@@ -615,9 +617,9 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
 	 * is <3us
 	 */
 	while (timeout++ < VP_TRANXDONE_TIMEOUT) {
-		prm_write_mod_reg(vdd->vp_reg.tranxdone_status,
+		vdd->write_reg(vdd->vp_reg.tranxdone_status,
 				ocp_mod, prm_irqst_reg);
-		if (!(prm_read_mod_reg(ocp_mod, prm_irqst_reg) &
+		if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) &
 				vdd->vp_reg.tranxdone_status))
 				break;
 		udelay(1);

@@ -629,28 +631,28 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
 	}
 
 	/* Configure for VP-Force Update */
-	vpconfig = prm_read_mod_reg(mod, vdd->vp_offs.vpconfig);
+	vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
 	vpconfig &= ~(vdd->vp_reg.vpconfig_initvdd |
 			vdd->vp_reg.vpconfig_forceupdate |
 			vdd->vp_reg.vpconfig_initvoltage_mask);
 	vpconfig |= ((target_vsel <<
 			vdd->vp_reg.vpconfig_initvoltage_shift));
-	prm_write_mod_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+	vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
 
 	/* Trigger initVDD value copy to voltage processor */
 	vpconfig |= vdd->vp_reg.vpconfig_initvdd;
-	prm_write_mod_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+	vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
 
 	/* Force update of voltage */
 	vpconfig |= vdd->vp_reg.vpconfig_forceupdate;
-	prm_write_mod_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+	vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
 
 	/*
 	 * Wait for TransactionDone. Typical latency is <200us.
 	 * Depends on SMPSWAITTIMEMIN/MAX and voltage change
 	 */
 	timeout = 0;
-	omap_test_timeout((prm_read_mod_reg(ocp_mod, prm_irqst_reg) &
+	omap_test_timeout((vdd->read_reg(ocp_mod, prm_irqst_reg) &
 			vdd->vp_reg.tranxdone_status),
 			VP_TRANXDONE_TIMEOUT, timeout);
 	if (timeout >= VP_TRANXDONE_TIMEOUT)

@@ -666,9 +668,9 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
 	 */
 	timeout = 0;
 	while (timeout++ < VP_TRANXDONE_TIMEOUT) {
-		prm_write_mod_reg(vdd->vp_reg.tranxdone_status,
+		vdd->write_reg(vdd->vp_reg.tranxdone_status,
 				ocp_mod, prm_irqst_reg);
-		if (!(prm_read_mod_reg(ocp_mod, prm_irqst_reg) &
+		if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) &
 				vdd->vp_reg.tranxdone_status))
 				break;
 		udelay(1);

@@ -679,13 +681,13 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
 			"to clear the TRANXDONE status\n",
 			__func__, vdd->voltdm.name);
 
-	vpconfig = prm_read_mod_reg(mod, vdd->vp_offs.vpconfig);
+	vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
 	/* Clear initVDD copy trigger bit */
 	vpconfig &= ~vdd->vp_reg.vpconfig_initvdd;;
-	prm_write_mod_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+	vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
 	/* Clear force bit */
 	vpconfig &= ~vdd->vp_reg.vpconfig_forceupdate;
-	prm_write_mod_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+	vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
 
 	return 0;
 }

@@ -713,23 +715,23 @@ static void __init omap3_vc_init(struct omap_vdd_info *vdd)
 	mod = vdd->vc_reg.prm_mod;
 
 	/* Set up the SMPS_SA(i2c slave address in VC */
-	vc_val = prm_read_mod_reg(mod, vdd->vc_reg.smps_sa_reg);
+	vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg);
 	vc_val &= ~vdd->vc_reg.smps_sa_mask;
 	vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift;
-	prm_write_mod_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg);
+	vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg);
 
 	/* Setup the VOLRA(pmic reg addr) in VC */
-	vc_val = prm_read_mod_reg(mod, vdd->vc_reg.smps_volra_reg);
+	vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg);
 	vc_val &= ~vdd->vc_reg.smps_volra_mask;
 	vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift;
-	prm_write_mod_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg);
+	vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg);
 
 	/*Configure the setup times */
-	vc_val = prm_read_mod_reg(mod, vdd->vc_reg.voltsetup_reg);
+	vc_val = vdd->read_reg(mod, vdd->vc_reg.voltsetup_reg);
 	vc_val &= ~vdd->vc_reg.voltsetup_mask;
 	vc_val |= vdd->pmic_info->volt_setup_time <<
 			vdd->vc_reg.voltsetup_shift;
-	prm_write_mod_reg(vc_val, mod, vdd->vc_reg.voltsetup_reg);
+	vdd->write_reg(vc_val, mod, vdd->vc_reg.voltsetup_reg);
 
 	/* Set up the on, inactive, retention and off voltage */
 	on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);

@@ -740,19 +742,19 @@ static void __init omap3_vc_init(struct omap_vdd_info *vdd)
 		(onlp_vsel << vdd->vc_reg.cmd_onlp_shift) |
 		(ret_vsel << vdd->vc_reg.cmd_ret_shift) |
 		(off_vsel << vdd->vc_reg.cmd_off_shift));
-	prm_write_mod_reg(vc_val, mod, vdd->vc_reg.cmdval_reg);
+	vdd->write_reg(vc_val, mod, vdd->vc_reg.cmdval_reg);
 
 	if (is_initialized)
 		return;
 
 	/* Generic VC parameters init */
-	prm_write_mod_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, mod,
+	vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, mod,
 			OMAP3_PRM_VC_CH_CONF_OFFSET);
-	prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, mod,
+	vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, mod,
 			OMAP3_PRM_VC_I2C_CFG_OFFSET);
-	prm_write_mod_reg(OMAP3_CLKSETUP, mod, OMAP3_PRM_CLKSETUP_OFFSET);
-	prm_write_mod_reg(OMAP3_VOLTOFFSET, mod, OMAP3_PRM_VOLTOFFSET_OFFSET);
-	prm_write_mod_reg(OMAP3_VOLTSETUP2, mod, OMAP3_PRM_VOLTSETUP2_OFFSET);
+	vdd->write_reg(OMAP3_CLKSETUP, mod, OMAP3_PRM_CLKSETUP_OFFSET);
+	vdd->write_reg(OMAP3_VOLTOFFSET, mod, OMAP3_PRM_VOLTOFFSET_OFFSET);
+	vdd->write_reg(OMAP3_VOLTSETUP2, mod, OMAP3_PRM_VOLTSETUP2_OFFSET);
 	is_initialized = true;
 }
 

@@ -896,16 +898,16 @@ static void __init omap4_vc_init(struct omap_vdd_info *vdd)
 	mod = vdd->vc_reg.prm_mod;
 
 	/* Set up the SMPS_SA(i2c slave address in VC */
-	vc_val = prm_read_mod_reg(mod, vdd->vc_reg.smps_sa_reg);
+	vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg);
 	vc_val &= ~vdd->vc_reg.smps_sa_mask;
 	vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift;
-	prm_write_mod_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg);
+	vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg);
 
 	/* Setup the VOLRA(pmic reg addr) in VC */
-	vc_val = prm_read_mod_reg(mod, vdd->vc_reg.smps_volra_reg);
+	vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg);
 	vc_val &= ~vdd->vc_reg.smps_volra_mask;
 	vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift;
-	prm_write_mod_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg);
+	vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg);
 
 	/* TODO: Configure setup times and CMD_VAL values*/
 

@@ -916,10 +918,10 @@ static void __init omap4_vc_init(struct omap_vdd_info *vdd)
 	vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
 		OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
 		OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
-	prm_write_mod_reg(vc_val, mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
+	vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
 
 	vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
-	prm_write_mod_reg(vc_val, mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
+	vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
 
 	is_initialized = true;
 }

@@ -994,12 +996,12 @@ static void __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
 
 	/* Generic voltage parameters */
 	vdd->curr_volt = 1200000;
-	vdd->ocp_mod = OMAP4430_PRM_OCP_SOCKET_MOD;
+	vdd->ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST;
 	vdd->volt_scale = vp_forceupdate_scale_voltage;
 	vdd->vp_enabled = false;
 
 	/* VC parameters */
-	vdd->vc_reg.prm_mod = OMAP4430_PRM_DEVICE_MOD;
+	vdd->vc_reg.prm_mod = OMAP4430_PRM_DEVICE_INST;
 	vdd->vc_reg.smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET;
 	vdd->vc_reg.smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET;
 	vdd->vc_reg.bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET;

@@ -1013,7 +1015,7 @@ static void __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
 	vdd->vc_reg.cmd_ret_shift = OMAP4430_RET_SHIFT;
 	vdd->vc_reg.cmd_off_shift = OMAP4430_OFF_SHIFT;
 
-	vdd->vp_reg.prm_mod = OMAP4430_PRM_DEVICE_MOD;
+	vdd->vp_reg.prm_mod = OMAP4430_PRM_DEVICE_INST;
 
 	/* VPCONFIG bit fields */
 	vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset <<

@@ -1091,7 +1093,7 @@ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
 
 	vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
 
-	curr_vsel = prm_read_mod_reg(vdd->vp_reg.prm_mod,
+	curr_vsel = vdd->read_reg(vdd->vp_reg.prm_mod,
 			vdd->vp_offs.voltage);
 
 	if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) {

@@ -1132,9 +1134,9 @@ void omap_vp_enable(struct voltagedomain *voltdm)
 	vp_latch_vsel(vdd);
 
 	/* Enable VP */
-	vpconfig = prm_read_mod_reg(mod, vdd->vp_offs.vpconfig);
+	vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
 	vpconfig |= vdd->vp_reg.vpconfig_vpenable;
-	prm_write_mod_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+	vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
 	vdd->vp_enabled = true;
 }
 

@@ -1169,14 +1171,14 @@ void omap_vp_disable(struct voltagedomain *voltdm)
 	}
 
 	/* Disable VP */
-	vpconfig = prm_read_mod_reg(mod, vdd->vp_offs.vpconfig);
+	vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
 	vpconfig &= ~vdd->vp_reg.vpconfig_vpenable;
-	prm_write_mod_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+	vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
 
 	/*
 	 * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
 	 */
-	omap_test_timeout((prm_read_mod_reg(mod, vdd->vp_offs.vstatus)),
+	omap_test_timeout((vdd->read_reg(mod, vdd->vp_offs.vstatus)),
 				VP_IDLE_TIMEOUT, timeout);
 
 	if (timeout >= VP_IDLE_TIMEOUT)