powerpc/85xx: Enable Errata command on MPC8572DS

PATCH New Kumar Gala 1 participant 10 messages Jan 26, 2011 – Feb 1, 2011 PowerPC

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Kumar Gala

author

2011-01-26 06:22 UTC #0 lore raw

PATCH 1/5 powerpc/85xx: Enable Errata command on MPC8572DS

From: York Sun <[email protected]>

Also removed duplicate CONFIG_CMD_IRQ define.

Signed-off-by York Sun <[email protected]>

Signed-off-by Kumar Gala <[email protected]>

---
 include/configs/MPC8572DS.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

include/configs/MPC8572DS.h +1 -1

index e6b60cf..8f333a6 100644
@@ -654,12 +654,12 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
 #define CONFIG_CMD_REGINFO

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-02-01 04:39 UTC #1 lore raw

PATCH 1/5 powerpc/85xx: Enable Errata command on MPC8572DS

Quoted 9 lines · Kumar Gala

From: York Sun <[email protected]>
Also removed duplicate CONFIG_CMD_IRQ define.
Signed-off-by York Sun <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
include/configs/MPC8572DS.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-26 06:22 UTC #2 lore raw

PATCH 2/5 powerpc/85xx: Remove unnecessary polling loop from DDR init

In reply to Kumar Gala

From: York Sun <[email protected]>

This polling loop is not required normally, unless specifically stated in workaround.

Signed-off-by York Sun <[email protected]>

Signed-off-by Kumar Gala <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/ddr-gen3.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

arch/powerpc/cpu/mpc85xx/ddr-gen3.c +0 -2

index fa7e09f..b9502f7 100644
@@ -199,8 +199,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 	asm volatile("sync;isync");
-	while (!(in_be32(&ddr->debug[1]) & 0x2))
-		;
 
 	/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 	while (in_be32(&ddr->sdram_cfg_2) & 0x10) {

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-02-01 04:39 UTC #3 lore raw

PATCH 2/5 powerpc/85xx: Remove unnecessary polling loop from DDR init

Quoted 10 lines · Kumar Gala

From: York Sun <[email protected]>
This polling loop is not required normally, unless specifically stated in workaround.
Signed-off-by York Sun <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-26 06:22 UTC #4 lore raw

PATCH 3/5 powerpc/85xx: Rename MPC8572 DDR erratum to DDR115

In reply to Kumar Gala

From: York Sun <[email protected]>

Use unique erratum number instead of platform number. Enable command that reports errata on MPC8572DS.

Signed-off-by York Sun <[email protected]>

Signed-off-by Kumar Gala <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    4 +++-
 arch/powerpc/cpu/mpc85xx/ddr-gen3.c       |    2 +-
 arch/powerpc/include/asm/config_mpc85xx.h |    1 +
 3 files changed, 5 insertions(+), 2 deletions(-)

arch/powerpc/cpu/mpc85xx/cmd_errata.c +3 -1

index 0cc8b1e..94a5876 100644
@@ -71,7 +71,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 	puts("Work-around for Erratum DDR-A003 enabled\n");
 #endif
-
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
+	puts("Work-around for Erratum DDR115 enabled\n");
+#endif
 	return 0;
 }

arch/powerpc/cpu/mpc85xx/ddr-gen3.c +1 -1

index b9502f7..35997f2 100644
@@ -178,7 +178,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	 * when operatiing in 32-bit bus mode with 4-beat bursts,
 	 * This erratum does not affect DDR3 mode, only for DDR2 mode.
 	 */
-#ifdef CONFIG_MPC8572
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 	if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 	    && in_be32(&ddr->sdram_cfg) & 0x80000) {
 		/* set DEBUG_1[31] */

arch/powerpc/include/asm/config_mpc85xx.h +1 -0

index 7a0af37..8ef9743 100644
@@ -77,6 +77,7 @@
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_FSL_ERRATUM_DDR_115
 
 #elif defined(CONFIG_P1010)
 #define CONFIG_MAX_CPUS			1

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-02-01 04:39 UTC #5 lore raw

PATCH 3/5 powerpc/85xx: Rename MPC8572 DDR erratum to DDR115

Quoted 5 lines · Kumar Gala

From: York Sun <[email protected]>
Use unique erratum number instead of platform number. Enable command that reports errata on MPC8572DS.

Quoted 7 lines

Signed-off-by York Sun <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    4 +++-
arch/powerpc/cpu/mpc85xx/ddr-gen3.c       |    2 +-
arch/powerpc/include/asm/config_mpc85xx.h |    1 +
3 files changed, 5 insertions(+), 2 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-26 06:22 UTC #6 lore raw

PATCH 4/5 powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134

In reply to Kumar Gala

From: York Sun <[email protected]>

Workaround for the following errata:
DDR111 - MCKE signal may not function correctly at assertion of HRESET DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can
calibrate to incorrect values

These two workarounds must be implemented together because they touch common registers.

Signed-off-by York Sun <[email protected]>

Signed-off-by Kumar Gala <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    4 +
 arch/powerpc/cpu/mpc85xx/ddr-gen3.c       |  107 ++++++++++++++++++++++++++++-
 arch/powerpc/include/asm/config_mpc85xx.h |    1 +
 arch/powerpc/include/asm/fsl_ddr_sdram.h  |    5 ++
 4 files changed, 116 insertions(+), 1 deletions(-)

arch/powerpc/cpu/mpc85xx/cmd_errata.c +4 -0

index 94a5876..feee36c 100644
@@ -74,6 +74,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 	puts("Work-around for Erratum DDR115 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+	puts("Work-around for Erratum DDR111 enabled\n");
+	puts("Work-around for Erratum DDR134 enabled\n");
+#endif
 	return 0;
 }

arch/powerpc/cpu/mpc85xx/ddr-gen3.c +106 -1

125 lines not on this page · raw message

arch/powerpc/include/asm/config_mpc85xx.h +1 -0

index 8ef9743..57d252c 100644
@@ -78,6 +78,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
+#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 
 #elif defined(CONFIG_P1010)
 #define CONFIG_MAX_CPUS			1

arch/powerpc/include/asm/fsl_ddr_sdram.h +5 -0

index 73bc023..b5b1efe 100644
@@ -89,6 +89,11 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define SDRAM_CFG_2T_EN			0x00008000
 #define SDRAM_CFG_BI			0x00000001
 
+#define SDRAM_CFG2_D_INIT		0x00000010
+#define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
+
+#define TIMING_CFG_2_CPO_MASK	0x0F800000
+
 #if defined(CONFIG_P4080)
 #define RD_TO_PRE_MASK		0xf
 #define RD_TO_PRE_SHIFT		13

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-02-01 04:39 UTC #7 lore raw

PATCH 4/5 powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134

Quoted 10 lines · Kumar Gala

From: York Sun <[email protected]>
Workaround for the following errata:
DDR111 - MCKE signal may not function correctly at assertion of HRESET DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can
calibrate to incorrect values
These two workarounds must be implemented together because they touch common registers.

Quoted 8 lines

Signed-off-by York Sun <[email protected]>

Signed-off-by Kumar Gala <[email protected]>

---

arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    4 +
arch/powerpc/cpu/mpc85xx/ddr-gen3.c       |  107 ++++++++++++++++++++++++++++-
arch/powerpc/include/asm/config_mpc85xx.h |    1 +
arch/powerpc/include/asm/fsl_ddr_sdram.h  |    5 ++
4 files changed, 116 insertions(+), 1 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-26 06:22 UTC #8 lore raw

PATCH 5/5 poewrpc/85xx: Enable ECC on MPC8572DS

In reply to Kumar Gala

From: York Sun <[email protected]>

Using hwconfig to turn on/off ECC, without re-compiling.

Signed-off-by York Sun <[email protected]>

Signed-off-by Kumar Gala <[email protected]>

---
 include/configs/MPC8572DS.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

include/configs/MPC8572DS.h +1 -0

index 8f333a6..bf2fdd6 100644
@@ -136,6 +136,7 @@
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 
+#define CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-02-01 04:39 UTC #9 lore raw

PATCH 5/5 poewrpc/85xx: Enable ECC on MPC8572DS

Quoted 9 lines · Kumar Gala

From: York Sun <[email protected]>
Using hwconfig to turn on/off ECC, without re-compiling.
Signed-off-by York Sun <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
include/configs/MPC8572DS.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)

applied to 85xx

- k