powerpc/85xx: Add support for Freescale P1023/P1017 Processors

PATCH New Kumar Gala 1 participant 4 messages Feb 4, 2011 – Feb 10, 2011 PowerPC

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Kumar Gala

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2011-02-04 20:41 UTC #0 lore raw

PATCH 1/2 powerpc/85xx: Add support for Freescale P1023/P1017 Processors

From: Roy Zang <[email protected]>

Add P1023 (dual core) & P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly).
* Added P1023/P1027 to config_mpc85xx.h
* Added new LAW type introduced on P1023/P1017
* Updated a few immap register/defines unique to P1023/P1017

Signed-off-by Roy Zang <[email protected]>

Signed-off-by Kumar Gala <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/Makefile         |    2 +
 arch/powerpc/cpu/mpc85xx/p1023_serdes.c   |   53 +++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc8xxx/cpu.c            |    6 +++-
 arch/powerpc/include/asm/config_mpc85xx.h |   20 +++++++++++
 arch/powerpc/include/asm/fsl_law.h        |    1 +
 arch/powerpc/include/asm/immap_85xx.h     |   14 ++++++++
 arch/powerpc/include/asm/processor.h      |    4 ++
 7 files changed, 99 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/p1023_serdes.c

arch/powerpc/cpu/mpc85xx/Makefile +2 -0

index 628e1cf..cc16db3 100644
@@ -92,9 +92,11 @@ COBJS-$(CONFIG_P1011)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1012)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1013)	+= p1022_serdes.o
 COBJS-$(CONFIG_P1014)	+= p1010_serdes.o
+COBJS-$(CONFIG_P1017)	+= p1023_serdes.o
 COBJS-$(CONFIG_P1020)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1021)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1022)	+= p1022_serdes.o
+COBJS-$(CONFIG_P1023)	+= p1023_serdes.o
 COBJS-$(CONFIG_P2010)	+= p2020_serdes.o
 COBJS-$(CONFIG_P2020)	+= p2020_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o

arch/powerpc/cpu/mpc85xx/p1023_serdes.c new file +53 -0

53 lines not on this page · raw message

arch/powerpc/cpu/mpc8xxx/cpu.c +5 -1

index 4335fb4..d2baaf0 100644
@@ -71,15 +71,19 @@ struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(P1012, P1012, 1),
 	CPU_TYPE_ENTRY(P1012, P1012_E, 1),
 	CPU_TYPE_ENTRY(P1013, P1013, 1),
+	CPU_TYPE_ENTRY(P1013, P1013_E, 1),
 	CPU_TYPE_ENTRY(P1014, P1014_E, 1),
 	CPU_TYPE_ENTRY(P1014, P1014, 1),
-	CPU_TYPE_ENTRY(P1013, P1013_E, 1),
+	CPU_TYPE_ENTRY(P1017, P1017, 1),
+	CPU_TYPE_ENTRY(P1017, P1017, 1),
 	CPU_TYPE_ENTRY(P1020, P1020, 2),
 	CPU_TYPE_ENTRY(P1020, P1020_E, 2),
 	CPU_TYPE_ENTRY(P1021, P1021, 2),
 	CPU_TYPE_ENTRY(P1021, P1021_E, 2),
 	CPU_TYPE_ENTRY(P1022, P1022, 2),
 	CPU_TYPE_ENTRY(P1022, P1022_E, 2),
+	CPU_TYPE_ENTRY(P1023, P1023, 2),
+	CPU_TYPE_ENTRY(P1023, P1023_E, 2),
 	CPU_TYPE_ENTRY(P2010, P2010, 1),
 	CPU_TYPE_ENTRY(P2010, P2010_E, 1),
 	CPU_TYPE_ENTRY(P2020, P2020, 2),

arch/powerpc/include/asm/config_mpc85xx.h +20 -0

index 57d252c..9c7ae8c 100644
@@ -110,6 +110,16 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 
+#elif defined(CONFIG_P1017)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	2
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_QMAN_NUM_PORTALS	3
+#define CONFIG_SYS_BMAN_NUM_PORTALS	3
+
 #elif defined(CONFIG_P1020)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12

@@ -128,6 +138,16 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 
+#elif defined(CONFIG_P1023)
+#define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	2
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_QMAN_NUM_PORTALS	3
+#define CONFIG_SYS_BMAN_NUM_PORTALS	3
+
 #elif defined(CONFIG_P2010)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12

arch/powerpc/include/asm/fsl_law.h +1 -0

index ae45f9b..13caffd 100644
@@ -83,6 +83,7 @@ enum law_trgt_if {
 	LAW_TRGT_IF_DDR_INTRLV = 0x0b,
 	LAW_TRGT_IF_RIO = 0x0c,
 	LAW_TRGT_IF_RIO_2 = 0x0d,
+	LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
 	LAW_TRGT_IF_DDR = 0x0f,
 	LAW_TRGT_IF_DDR_2 = 0x16,	/* 2nd controller */
 };

arch/powerpc/include/asm/immap_85xx.h +14 -0

index f239e59..ce27fec 100644
@@ -1865,8 +1865,13 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORBMSR_HA_SHIFT	16
 	u32	porimpscr;	/* POR I/O impedance status & control */
 	u32	pordevsr;	/* POR I/O device status regsiter */
+#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#define MPC85xx_PORDEVSR_SGMII1_DIS	0x10000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS	0x08000000
+#else
 #define MPC85xx_PORDEVSR_SGMII1_DIS	0x20000000
 #define MPC85xx_PORDEVSR_SGMII2_DIS	0x10000000
+#endif
 #define MPC85xx_PORDEVSR_SGMII3_DIS	0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL	0x38000000

@@ -1874,6 +1879,9 @@ typedef struct ccsr_gur {
 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
 #define MPC85xx_PORDEVSR_IO_SEL		0x007c0000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	18
+#elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#define MPC85xx_PORDEVSR_IO_SEL		0x00600000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
 #else
 #if defined(CONFIG_P1010)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00600000

@@ -2247,6 +2255,12 @@ typedef struct ccsr_pme {
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
 #define CONFIG_SYS_MPC85xx_CPM_OFFSET		0x80000
+#define CONFIG_SYS_FSL_QMAN_OFFSET		0x88000
+#define CONFIG_SYS_FSL_BMAN_OFFSET		0x8a000
+#define CONFIG_SYS_FSL_FM1_OFFSET		0x100000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x188000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x189000
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x1e0000
 #endif
 
 #define CONFIG_SYS_MPC85xx_PIC_OFFSET		0x40000

arch/powerpc/include/asm/processor.h +4 -0

index fcee1a2..d8b8f34 100644
@@ -1048,12 +1048,16 @@
 #define SVR_P1013_E	0x80EF00
 #define SVR_P1014	0x80F101
 #define SVR_P1014_E	0x80F901
+#define SVR_P1017	0x80F700
+#define SVR_P1017_E	0x80FF00
 #define SVR_P1020	0x80E400
 #define SVR_P1020_E	0x80EC00
 #define SVR_P1021	0x80E401
 #define SVR_P1021_E	0x80EC01
 #define SVR_P1022	0x80E600
 #define SVR_P1022_E	0x80EE00
+#define SVR_P1023	0x80F600
+#define SVR_P1023_E	0x80FE00
 #define SVR_P2010	0x80E300
 #define SVR_P2010_E	0x80EB00
 #define SVR_P2020	0x80E200

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-02-10 05:24 UTC #1 lore raw

PATCH 1/2 powerpc/85xx: Add support for Freescale P1023/P1017 Processors

Quoted 21 lines · Kumar Gala

From: Roy Zang <[email protected]>
Add P1023 (dual core) & P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly).
* Added P1023/P1027 to config_mpc85xx.h
* Added new LAW type introduced on P1023/P1017
* Updated a few immap register/defines unique to P1023/P1017
Signed-off-by Roy Zang <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
arch/powerpc/cpu/mpc85xx/Makefile         |    2 +
arch/powerpc/cpu/mpc85xx/p1023_serdes.c   |   53 +++++++++++++++++++++++++++++
arch/powerpc/cpu/mpc8xxx/cpu.c            |    6 +++-
arch/powerpc/include/asm/config_mpc85xx.h |   20 +++++++++++
arch/powerpc/include/asm/fsl_law.h        |    1 +
arch/powerpc/include/asm/immap_85xx.h     |   14 ++++++++
arch/powerpc/include/asm/processor.h      |    4 ++
7 files changed, 99 insertions(+), 1 deletions(-)

Quoted 1 line

create mode 100644 arch/powerpc/cpu/mpc85xx/p1023_serdes.c

applied to 85xx next

- k

Kumar Gala

author

2011-02-04 20:41 UTC #2 lore raw

PATCH 2/2 powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs

In reply to Kumar Gala

From: Haiying Wang <[email protected]>

There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps.

* Rename various immap defines to remove _CORENET_ if they are shared
* Added P1023/P1017 specific memory offsets
* Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017)

Signed-off-by Haiying Wang <[email protected]>

Signed-off-by Kumar Gala <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/Makefile     |    2 +-
 arch/powerpc/cpu/mpc85xx/portals.c    |   32 +++++++++++++++++++++++---------
 arch/powerpc/cpu/mpc85xx/speed.c      |    7 +++++++
 arch/powerpc/include/asm/fsl_liodn.h  |   10 +++++-----
 arch/powerpc/include/asm/immap_85xx.h |   12 ++++++------
 include/configs/corenet_ds.h          |    1 +
 6 files changed, 43 insertions(+), 21 deletions(-)

arch/powerpc/cpu/mpc85xx/Makefile +1 -1

index cc16db3..5791be0 100644
@@ -69,7 +69,7 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS-$(CONFIG_FSL_CORENET) += liodn.o
 COBJS-$(CONFIG_MP)	+= mp.o
 COBJS-$(CONFIG_PCI)	+= pci.o
-COBJS-$(CONFIG_FSL_CORENET) += portals.o
+COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
 
 # various SoC specific assignments
 COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o

arch/powerpc/cpu/mpc85xx/portals.c +23 -9

index 01aec6e..e8d53bb 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -30,18 +30,13 @@
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
 
-static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR;
+static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
 
 void setup_portals(void)
 {
+#ifdef CONFIG_FSL_CORENET
 	int i;
 
-	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
-#ifdef CONFIG_PHYS_64BIT
-	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
-#endif
-	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
-
 	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
 		u8 sdest = qp_info[i].sdest;
 		u16 fliodn = qp_info[i].fliodn;

@@ -53,6 +48,13 @@ void setup_portals(void)
 		/* set frame liodn */
 		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
 	}
+#endif
+
+	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
+#ifdef CONFIG_PHYS_64BIT
+	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+#endif
+	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
 }
 
 /* Update portal containter to match LAW setup of portal in phy map */

@@ -118,9 +120,12 @@ void fdt_portal(void *blob, const char *compat, const char *container,
 static int fdt_qportal(void *blob, int off, int id, char *name,
 		       enum fsl_dpaa_dev dev, int create)
 {
-	int childoff, dev_off, num, ret = 0;
+	int childoff, dev_off, ret = 0;
 	uint32_t dev_handle;
+#ifdef CONFIG_FSL_CORENET
+	int num;
 	u32 liodns[2];
+#endif
 
 	childoff = fdt_subnode_offset(blob, off, name);
 	if (create) {

@@ -154,9 +159,11 @@ static int fdt_qportal(void *blob, int off, int id, char *name,
 			if (ret < 0)
 				return ret;
 
+#ifdef CONFIG_FSL_CORENET
 			num = get_dpaa_liodn(dev, &liodns[0], id);
 			ret = fdt_setprop(blob, childoff, "fsl,liodn",
 					  &liodns[0], sizeof(u32) * num);
+#endif
 		} else {
 			return childoff;
 		}

@@ -184,7 +191,9 @@ void fdt_fixup_qportals(void *blob)
 
 	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
 	while (off != -FDT_ERR_NOTFOUND) {
+#ifdef CONFIG_FSL_CORENET
 		u32 liodns[2];
+#endif
 		const int *ci = fdt_getprop(blob, off, "cell-index", NULL);
 		int j, i = *ci;

@@ -192,6 +201,7 @@ void fdt_fixup_qportals(void *blob)
 		if (err < 0)
 			goto err;
 
+#ifdef CONFIG_FSL_CORENET
 		liodns[0] = qp_info[i].dliodn;
 		liodns[1] = qp_info[i].fliodn;

@@ -199,6 +209,7 @@ void fdt_fixup_qportals(void *blob)
 				  &liodns, sizeof(u32) * 2);
 		if (err < 0)
 			goto err;
+#endif
 
 		i++;

@@ -207,6 +218,7 @@ void fdt_fixup_qportals(void *blob)
 		if (err < 0)
 			goto err;
 
+#ifdef CONFIG_FSL_CORENET
 #ifdef CONFIG_SYS_DPAA_PME
 		err = fdt_qportal(blob, off, i, "pme at 0", FSL_HW_PORTAL_PME, 1);
 		if (err < 0)

@@ -214,6 +226,8 @@ void fdt_fixup_qportals(void *blob)
 #else
 		fdt_qportal(blob, off, i, "pme at 0", FSL_HW_PORTAL_PME, 0);
 #endif
+#endif
+
 #ifdef CONFIG_SYS_DPAA_FMAN
 		for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
 			char name[] = "fman@0";

arch/powerpc/cpu/mpc85xx/speed.c +7 -0

index f2aa8d0..d440b6a 100644
@@ -170,6 +170,13 @@ void get_sys_info (sys_info_t * sysInfo)
 	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
 #endif
 
+#ifdef CONFIG_SYS_DPAA_FMAN
+		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+#if (CONFIG_SYS_NUM_FMAN) == 2
+		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+#endif
+#endif
+
 #if defined(CONFIG_FSL_LBC)
 #if defined(CONFIG_SYS_LBC_LCRR)
 	/* We will program LCRR to this value later */

arch/powerpc/include/asm/fsl_liodn.h +5 -5

index 4c17fe2..f76676c 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -85,13 +85,13 @@ extern void fdt_fixup_liodn(void *blob);
 
 #define SET_QMAN_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
-		CONFIG_SYS_FSL_CORENET_QMAN_OFFSET, \
-		CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
+		CONFIG_SYS_FSL_QMAN_OFFSET, \
+		CONFIG_SYS_FSL_QMAN_OFFSET)
 
 #define SET_BMAN_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \
-		CONFIG_SYS_FSL_CORENET_BMAN_OFFSET, \
-		CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
+		CONFIG_SYS_FSL_BMAN_OFFSET, \
+		CONFIG_SYS_FSL_BMAN_OFFSET)
 
 #define SET_PME_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \

arch/powerpc/include/asm/immap_85xx.h +6 -6

index ce27fec..d26d648 100644
@@ -2204,8 +2204,8 @@ typedef struct ccsr_pme {
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x300000
 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET	0x316000
-#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET	0x318000
-#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET	0x31a000
+#define CONFIG_SYS_FSL_QMAN_OFFSET		0x318000
+#define CONFIG_SYS_FSL_BMAN_OFFSET		0x31a000
 #define CONFIG_SYS_FSL_FM1_OFFSET		0x400000
 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x488000
 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x489000

@@ -2268,10 +2268,10 @@ typedef struct ccsr_pme {
 
 #define CONFIG_SYS_FSL_CPC_ADDR	\
 	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
+#define CONFIG_SYS_FSL_QMAN_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
+#define CONFIG_SYS_FSL_BMAN_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \

include/configs/corenet_ds.h +1 -0

index bff212e..7bafa05 100644
@@ -357,6 +357,7 @@
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 
 /* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-02-10 05:26 UTC #3 lore raw

PATCH 2/2 powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs

Quoted 13 lines · Kumar Gala

From: Haiying Wang <[email protected]>
There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps.
* Rename various immap defines to remove _CORENET_ if they are shared
* Added P1023/P1017 specific memory offsets
* Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017)
Signed-off-by Haiying Wang <[email protected]>
Signed-off-by Kumar Gala <[email protected]>

Quoted 8 lines

---

arch/powerpc/cpu/mpc85xx/Makefile     |    2 +-
arch/powerpc/cpu/mpc85xx/portals.c    |   32 +++++++++++++++++++++++---------
arch/powerpc/cpu/mpc85xx/speed.c      |    7 +++++++
arch/powerpc/include/asm/fsl_liodn.h  |   10 +++++-----
arch/powerpc/include/asm/immap_85xx.h |   12 ++++++------
include/configs/corenet_ds.h          |    1 +
6 files changed, 43 insertions(+), 21 deletions(-)

applied to 85xx next

- k