pruss mfd drivers

This patch adds the pruss MFD driver and associated include files.

drivers/mfd/da8xx_pru.c new file +14 -0

+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as  published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/module.h>

drivers/mfd/da8xx_pru.c new file +2 -0

+s16 pruss_writeb(struct device *dev, u32 u32offset,
+		u8 *pu8datatowrite, u16 u16bytestowrite)

Hi Subhasish,

Quoted 1 line · Subhasish Ghosh

This patch adds the pruss MFD driver and associated include files.

A more detailed changelog would be better. What is this device, why is it an MFD and what are its potential subdevices ?

Quoted 8 lines

drivers/mfd/Kconfig +0 -0

index fd01836..6c437df 100644
@@ -81,6 +81,16 @@ config MFD_DM355EVM_MSP
   boards.  MSP430 firmware manages resets and power sequencing,
   inputs from buttons and the IR remote, LEDs, an RTC, and more.
 

drivers/mfd/Kconfig config MFD_DM355EVM_MSP · line 86

Quoted 3 lines

drivers/mfd/Kconfig +3 -0

+config MFD_DA8XX_PRUSS
+ tristate "Texas Instruments DA8XX PRUSS support"
+ depends on ARCH_DAVINCI && ARCH_DAVINCI_DA850

Why are we depending on those ?

drivers/mfd/Kconfig config MFD_DM355EVM_MSP · line 92

Quoted 8 lines

drivers/mfd/Kconfig +6 -0

+ select MFD_CORE
+ help
+     This driver provides support api's for the programmable
+ realtime unit (PRU) present on TI's da8xx processors. It
+ provides basic read, write, config, enable, disable
+ routines to facilitate devices emulated on it.

Please fix your identation here.

drivers/mfd/da8xx_pru.c line 2

Quoted 6 lines

drivers/mfd/da8xx_pru.c new file +2 -0

@@ -0,0 +1,446 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated

s/2010/2011/ ?

Quoted 19 lines

drivers/mfd/da8xx_pru.c new file +1 -0

+ * This program is free software; you can redistribute it and/or modify 

it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */

drivers/mfd/da8xx_pru.c new file +8 -0

+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>

drivers/mfd/da8xx_pru.c line 27

Quoted 7 lines

drivers/mfd/da8xx_pru.c new file +7 -0

+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/mfd/pruss/da8xx_prucore.h>
+#include <linux/mfd/pruss/da8xx_pru.h>
+#include <linux/mfd/core.h>
+#include <linux/io.h>
+#include <mach/da8xx.h>

Is that include needed ?

Quoted 3 lines

+struct da8xx_pruss {

What is the "ss" suffix for ?

drivers/mfd/da8xx_pru.c line 54

Quoted 12 lines

drivers/mfd/da8xx_pru.c new file +10 -0

+u32 pruss_disable(struct device *dev, u8 pruss_num)
+{
+ struct da8xx_pruss *pruss = dev_get_drvdata(dev->parent);
+ da8xx_prusscore_regs h_pruss;
+ u32 temp_reg;
+
+ if (pruss_num == DA8XX_PRUCORE_0) {
+ /* Disable PRU0  */
+ h_pruss = (da8xx_prusscore_regs)
+ ((u32) pruss->ioaddr + 0x7000);

So it seems you're doing this in several places, and I have a few comments:

- You don't need the da8xx_prusscore_regs at all.
- Define the register map through a set of #define in your header file.
- Use a static routine that takes the core number and returns the register map
offset.

Then routines like this one will look a lot more readable.

Quoted 3 lines

+s16 pruss_writeb(struct device *dev, u32 u32offset,
+ u8 *pu8datatowrite, u16 u16bytestowrite)

From CodingStyle: "Encoding the type of a function into the name (so-called Hungarian notation) is brain damaged"

Also, all your exported routines severely lack any sort of locking. An IO mutex or spinlock is mandatory here.

Quoted 19 lines

drivers/mfd/da8xx_pru.c new file +18 -0

+static int pruss_mfd_add_devices(struct platform_device *pdev)
+{
+ struct da8xx_pruss_devices *dev_data = pdev->dev.platform_data;
+ struct device *dev = &pdev->dev;
+ struct mfd_cell cell;
+ u32 err, count;
+
+ for (count = 0; (dev_data + count)->dev_name != NULL; count++) {
+ memset(&cell, 0, sizeof(struct mfd_cell));
+ cell.id = count;
+ cell.name = (dev_data + count)->dev_name;
+ cell.platform_data = (dev_data + count)->pdata;
+ cell.data_size = (dev_data + count)->pdata_size;
+
+ err = mfd_add_devices(dev, 0, &cell, 1, NULL, 0);
+ if (err) {
+ dev_err(dev, "cannot add mfd cells\n");
+ return err;

Quoted 4 lines

+ }
+ }
+ return err;
+}

So, what are the potential subdevices for this driver ? If it's a really dynamic setup, I'm fine with passing those as platform data but then do it so that you pass a NULL terminated da8xx_pruss_devices array. That will avoid most of the ugly casts you're doing here.

Quoted 25 lines

include/linux/mfd/pruss/da8xx_pru.h new file +5 -0

new file mode 100644
index 0000000..68d8421
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Author: Jitendra Kumar <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify 

it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */

include/linux/mfd/pruss/da8xx_pru.h new file +3 -0

+
+#ifndef _PRUSS_H_
+#define _PRUSS_H_

include/linux/mfd/pruss/da8xx_pru.h line 23

Quoted 7 lines

include/linux/mfd/pruss/da8xx_pru.h new file +7 -0

+
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include "da8xx_prucore.h"
+
+#define PRUSS_NUM0 DA8XX_PRUCORE_0
+#define PRUSS_NUM1 DA8XX_PRUCORE_1

Those are unused.

include/linux/mfd/pruss/da8xx_prucore.h

Quoted 6 lines

include/linux/mfd/pruss/da8xx_prucore.h new file +0 -0

new file mode 100644
index 0000000..81f2ff9

Please rename your mfd include directory to include/linux/mfd/da8xx/, so that one can match it with the drivers/mfd/da8xx driver code.

Quoted 7 lines

include/linux/mfd/pruss/da8xx_prucore.h new file +5 -0

+typedef struct {
+ u32 CONTROL;
+ u32 STATUS;
+ u32 WAKEUP;
+ u32 CYCLECNT;

include/linux/mfd/pruss/da8xx_prucore.h line 72

Quoted 10 lines

include/linux/mfd/pruss/da8xx_prucore.h new file +10 -0

+ u32 STALLCNT;
+ u8  RSVD0[12];
+ u32 CONTABBLKIDX0;
+ u32 CONTABBLKIDX1;
+ u32 CONTABPROPTR0;
+ u32 CONTABPROPTR1;
+ u8  RSVD1[976];
+ u32 INTGPR[32];
+ u32 INTCTER[32];
+} *da8xx_prusscore_regs;

Again, we don't need that structure.

Cheers,
Samuel.

Signature · 2 lines

Intel Open Source Technology Centre
http://oss.intel.com/ 

Thank you for your comments.

Quoted 8 lines

Quoted 8 lines

drivers/mfd/Kconfig +0 -0

index fd01836..6c437df 100644
@@ -81,6 +81,16 @@ config MFD_DM355EVM_MSP
  boards.  MSP430 firmware manages resets and power sequencing,
  inputs from buttons and the IR remote, LEDs, an RTC, and more.
 

Quoted 4 lines

drivers/mfd/Kconfig config MFD_DM355EVM_MSP · line 86

Quoted 3 lines

drivers/mfd/Kconfig +3 -0

+config MFD_DA8XX_PRUSS
+ tristate "Texas Instruments DA8XX PRUSS support"
+ depends on ARCH_DAVINCI && ARCH_DAVINCI_DA850

Why are we depending on those ?

SG -- The PRUSS core in only available within DA850 and DA830,
DA830 support is not yet implemented.

Quoted 19 lines

drivers/mfd/Kconfig config MFD_DM355EVM_MSP · line 96

Quoted 10 lines

drivers/mfd/Kconfig +10 -0

+u32 pruss_disable(struct device *dev, u8 pruss_num)
+{
+ struct da8xx_pruss *pruss = dev_get_drvdata(dev->parent);
+ da8xx_prusscore_regs h_pruss;
+ u32 temp_reg;
+
+ if (pruss_num == DA8XX_PRUCORE_0) {
+ /* Disable PRU0  */
+ h_pruss = (da8xx_prusscore_regs)
+ ((u32) pruss->ioaddr + 0x7000);

So it seems you're doing this in several places, and I have a few comments:

- You don't need the da8xx_prusscore_regs at all.
- Define the register map through a set of #define in your header file.
- Use a static routine that takes the core number and returns the register map
offset.

Quoted 1 line

Then routines like this one will look a lot more readable.

SG -- There are a huge number of PRUSS registers. A lot of them are reserved and are expected to change as development on the
controller is still ongoing.

If we use #defines to plot
all the registers, then first, there are too many array type registers which will need to be duplicated.

Quoted 2 lines

Also, all your exported routines severely lack any sort of locking. An IO mutex or spinlock is mandatory here.

SG - As per our current implementation, we do not have two devices running simultaneously on the PRU,
so we do not have any way to test it. We have kept this as an
enhancement if request comes in for
multiple devices.

Quoted 19 lines

Quoted 19 lines

drivers/mfd/Kconfig +19 -0

+static int pruss_mfd_add_devices(struct platform_device *pdev)
+{
+ struct da8xx_pruss_devices *dev_data = pdev->dev.platform_data;
+ struct device *dev = &pdev->dev;
+ struct mfd_cell cell;
+ u32 err, count;
+
+ for (count = 0; (dev_data + count)->dev_name != NULL; count++) {
+ memset(&cell, 0, sizeof(struct mfd_cell));
+ cell.id = count;
+ cell.name = (dev_data + count)->dev_name;
+ cell.platform_data = (dev_data + count)->pdata;
+ cell.data_size = (dev_data + count)->pdata_size;
+
+ err = mfd_add_devices(dev, 0, &cell, 1, NULL, 0);
+ if (err) {
+ dev_err(dev, "cannot add mfd cells\n");
+ return err;
+ }

Quoted 8 lines

Quoted 3 lines

+ }
+ return err;
+}

So, what are the potential subdevices for this driver ? If it's a really dynamic setup, I'm fine with passing those as platform data but then do it so
that you pass a NULL terminated da8xx_pruss_devices array. That will avoid most of the ugly casts you're doing here.

SG -- I did not follow your recommendations here, could you please elaborate.
I am already checking the dev_name for a NULL. This device is basically a microcontroller within DA850,
so basically any device or protocol can be
emulated on it. Currently, we have emulated 8 UARTS using
the two PRUs and also a CAN device.

Hi Subhasish,

Quoted 1 line · Subhasish Ghosh

Thank you for your comments.

No problem.

Quoted 8 lines

Quoted 8 lines

Quoted 8 lines

drivers/mfd/Kconfig +0 -0

index fd01836..6c437df 100644
@@ -81,6 +81,16 @@ config MFD_DM355EVM_MSP
  boards.  MSP430 firmware manages resets and power sequencing,
  inputs from buttons and the IR remote, LEDs, an RTC, and more.
 

Quoted 7 lines

Quoted 4 lines

drivers/mfd/Kconfig config MFD_DM355EVM_MSP · line 86

Quoted 3 lines

drivers/mfd/Kconfig +3 -0

+config MFD_DA8XX_PRUSS
+ tristate "Texas Instruments DA8XX PRUSS support"
+ depends on ARCH_DAVINCI && ARCH_DAVINCI_DA850

Why are we depending on those ?

SG -- The PRUSS core in only available within DA850 and DA830,
DA830 support is not yet implemented.

Sure, but if there are no actual code dependencies, I'd like to get rid of those depends.

Quoted 19 lines

Quoted 19 lines

drivers/mfd/Kconfig config MFD_DM355EVM_MSP · line 96

Quoted 10 lines

drivers/mfd/Kconfig +10 -0

+u32 pruss_disable(struct device *dev, u8 pruss_num)
+{
+ struct da8xx_pruss *pruss = dev_get_drvdata(dev->parent);
+ da8xx_prusscore_regs h_pruss;
+ u32 temp_reg;
+
+ if (pruss_num == DA8XX_PRUCORE_0) {
+ /* Disable PRU0  */
+ h_pruss = (da8xx_prusscore_regs)
+ ((u32) pruss->ioaddr + 0x7000);

So it seems you're doing this in several places, and I have a few comments:

- You don't need the da8xx_prusscore_regs at all.
- Define the register map through a set of #define in your header file.
- Use a static routine that takes the core number and returns the register map
offset.

Quoted 5 lines

Quoted 1 line

Then routines like this one will look a lot more readable.

SG -- There are a huge number of PRUSS registers. A lot of them are reserved and are expected to change as development on the
controller is still ongoing.

First of all, from what I read in your patch you're only using the CONTROL offset.

Quoted 3 lines

If we use #defines to plot
all the registers, then first, there are too many array type registers which will need to be duplicated.

What I'm expecting is a small set of defines for the register offsets. You have 13 fields in your da8xx_prusscore_regs, you only need to define 13 register offsets.

So, if you have a:

static u32 reg_offset(struct device *dev, u8 pru_num)

{
	struct da8xx_pruss *pru = dev_get_drvdata(dev->parent);

	switch (pru_num) {
	case DA8XX_PRUCORE_0:
		return (u32) pru->ioaddr + 0x7000;
	case DA8XX_PRUCORE_1:
		return (u32) pru->ioaddr + 0x7800;
	default:
		return 0;
}

then routines like pruss_enable (which should return an int, btw) would look like:

int pruss_enable(struct device *dev, u8 pruss_num)

{
	u32 offset = reg_offset(dev, pruss_num);

	if (offset == 0)
		return -EINVAL;

	__raw_writel(DA8XX_PRUCORE_CONTROL_RESETVAL,
			offset + PRU_CORE_CONTROL);

	return 0;
}

Quoted 78 lines · Samuel Ortiz

Hi Subhasish,

Quoted 1 line · Subhasish Ghosh

Thank you for your comments.

No problem.

Quoted 8 lines

Quoted 8 lines

Quoted 8 lines

drivers/mfd/Kconfig +0 -0

index fd01836..6c437df 100644
@@ -81,6 +81,16 @@ config MFD_DM355EVM_MSP
  boards.  MSP430 firmware manages resets and power sequencing,
  inputs from buttons and the IR remote, LEDs, an RTC, and more.
 

Quoted 7 lines

Quoted 4 lines

drivers/mfd/Kconfig config MFD_DM355EVM_MSP · line 86

Quoted 3 lines

drivers/mfd/Kconfig +3 -0

+config MFD_DA8XX_PRUSS
+ tristate "Texas Instruments DA8XX PRUSS support"
+ depends on ARCH_DAVINCI && ARCH_DAVINCI_DA850

Why are we depending on those ?

SG -- The PRUSS core in only available within DA850 and DA830,
DA830 support is not yet implemented.

Sure, but if there are no actual code dependencies, I'd like to get rid of those depends.

Quoted 19 lines

Quoted 19 lines

drivers/mfd/Kconfig config MFD_DM355EVM_MSP · line 96

Quoted 10 lines

drivers/mfd/Kconfig +10 -0

+u32 pruss_disable(struct device *dev, u8 pruss_num)
+{
+ struct da8xx_pruss *pruss = dev_get_drvdata(dev->parent);
+ da8xx_prusscore_regs h_pruss;
+ u32 temp_reg;
+
+ if (pruss_num == DA8XX_PRUCORE_0) {
+ /* Disable PRU0  */
+ h_pruss = (da8xx_prusscore_regs)
+ ((u32) pruss->ioaddr + 0x7000);

So it seems you're doing this in several places, and I have a few comments:

- You don't need the da8xx_prusscore_regs at all.
- Define the register map through a set of #define in your header file.
- Use a static routine that takes the core number and returns the register map
offset.

Quoted 5 lines

Quoted 1 line

Then routines like this one will look a lot more readable.

SG -- There are a huge number of PRUSS registers. A lot of them are reserved and are expected to change as development on the
controller is still ongoing.

First of all, from what I read in your patch you're only using the CONTROL offset.

Quoted 3 lines

If we use #defines to plot
all the registers, then first, there are too many array type registers which will need to be duplicated.

What I'm expecting is a small set of defines for the register offsets. You have 13 fields in your da8xx_prusscore_regs, you only need to define 13 register offsets.

So, if you have a:

static u32 reg_offset(struct device *dev, u8 pru_num)

{
	struct da8xx_pruss *pru = dev_get_drvdata(dev->parent);

	switch (pru_num) {
	case DA8XX_PRUCORE_0:
		return (u32) pru->ioaddr + 0x7000;
	case DA8XX_PRUCORE_1:
		return (u32) pru->ioaddr + 0x7800;
	default:
		return 0;
}

then routines like pruss_enable (which should return an int, btw) would look like:

int pruss_enable(struct device *dev, u8 pruss_num)

Quoted 11 lines

{
	u32 offset = reg_offset(dev, pruss_num);

	if (offset == 0)
		return -EINVAL;

	__raw_writel(DA8XX_PRUCORE_CONTROL_RESETVAL,
			offset + PRU_CORE_CONTROL);

	return 0;
}

All registers are memory mapped and could nicely be described by structures (and sub-structures). Therefore we asked to considerer structs, at least for the Pruss SocketCAN drivers.

That would result in
much much clearer and better readable code. The code above would shrink to:

	__raw_writel(DA8XX_PRUCORE_CONTROL_RESETVAL,
		     &prucore[pruss_num].control);

Quoted 96 lines · Samuel Ortiz

Quoted 82 lines

Hi Subhasish,

Quoted 1 line · Subhasish Ghosh

Thank you for your comments.

No problem.

Quoted 8 lines

Quoted 8 lines

Quoted 8 lines

drivers/mfd/Kconfig +0 -0

index fd01836..6c437df 100644
@@ -81,6 +81,16 @@ config MFD_DM355EVM_MSP
  boards.  MSP430 firmware manages resets and power sequencing,
  inputs from buttons and the IR remote, LEDs, an RTC, and more.
 

Quoted 7 lines

Quoted 4 lines

drivers/mfd/Kconfig config MFD_DM355EVM_MSP · line 86

Quoted 3 lines

drivers/mfd/Kconfig +3 -0

+config MFD_DA8XX_PRUSS
+ tristate "Texas Instruments DA8XX PRUSS support"
+ depends on ARCH_DAVINCI && ARCH_DAVINCI_DA850

Why are we depending on those ?

SG -- The PRUSS core in only available within DA850 and DA830,
DA830 support is not yet implemented.

Sure, but if there are no actual code dependencies, I'd like to get rid of those depends.

Quoted 20 lines

Quoted 20 lines

drivers/mfd/Kconfig config MFD_DM355EVM_MSP · line 96

Quoted 10 lines

drivers/mfd/Kconfig +10 -0

+u32 pruss_disable(struct device *dev, u8 pruss_num)
+{
+ struct da8xx_pruss *pruss = dev_get_drvdata(dev->parent);
+ da8xx_prusscore_regs h_pruss;
+ u32 temp_reg;
+
+ if (pruss_num == DA8XX_PRUCORE_0) {
+ /* Disable PRU0  */
+ h_pruss = (da8xx_prusscore_regs)
+ ((u32) pruss->ioaddr + 0x7000);

So it seems you're doing this in several places, and I have a few comments:

- You don't need the da8xx_prusscore_regs at all.
- Define the register map through a set of #define in your header file.
- Use a static routine that takes the core number and returns the register map
offset.

Quoted 5 lines

Quoted 1 line

Then routines like this one will look a lot more readable.

SG -- There are a huge number of PRUSS registers. A lot of them are reserved and are expected to change as development on the
controller is still ongoing.

First of all, from what I read in your patch you're only using the CONTROL offset.

Quoted 3 lines

If we use #defines to plot
all the registers, then first, there are too many array type registers which will need to be duplicated.

What I'm expecting is a small set of defines for the register offsets. You have 13 fields in your da8xx_prusscore_regs, you only need to define 13 register offsets.

So, if you have a:

static u32 reg_offset(struct device *dev, u8 pru_num) {
struct da8xx_pruss *pru = dev_get_drvdata(dev->parent);

switch (pru_num) {
case DA8XX_PRUCORE_0:
return (u32) pru->ioaddr + 0x7000;
case DA8XX_PRUCORE_1:
return (u32) pru->ioaddr + 0x7800;
default:
return 0;
}

then routines like pruss_enable (which should return an int, btw) would look like:

int pruss_enable(struct device *dev, u8 pruss_num) {
u32 offset = reg_offset(dev, pruss_num);

Quoted 8 lines

if (offset == 0)
return -EINVAL;

__raw_writel(DA8XX_PRUCORE_CONTROL_RESETVAL,
offset + PRU_CORE_CONTROL);

return 0;
}

All registers are memory mapped and could nicely be described by structures (and sub-structures). Therefore we asked to considerer structs, at least for the Pruss SocketCAN drivers.

Quoted 5 lines

That would result in
much much clearer and better readable code. The code above would shrink to:

__raw_writel(DA8XX_PRUCORE_CONTROL_RESETVAL,

     &prucore[pruss_num].control);

This driver seems to exclusively use the control offset, which is why I don't see an absolute need for doing this mapping.
But if both maps are contiguous then doing the mapping would prevent us from calling reg_offset() and would bring some advantage. I'd then be fine with it. For now, da8xx_prusscore_regs seems to be larger than the 0x800 interval between the 2 maps, so I have no idea if both maps are indeed contiguous.

Cheers,
Samuel.

Signature · 2 lines

Intel Open Source Technology Centre
http://oss.intel.com/ 

I am not sure if I understood you correctly, but the current sizeof the structure da8xx_prusscore_regs is 0x500.

Here is a link to the PRUSS memory map:
http://processors.wiki.ti.com/index.php/PRUSS_Memory_Map

The offset 0x00007000 is the PRU0 reg offset and 0x00007800 is the PRU1 reg offset.
We cannot have a register file larger than this, but lot of space is left out, possibly for future development.

Hi Subhasish,

Quoted 1 line · Subhasish Ghosh

Thank you for your comments.

No problem.

Quoted 13 lines

Quoted 12 lines

drivers/mfd/Kconfig config MFD_DM355EVM_MSP · line 86

Quoted 11 lines

drivers/mfd/Kconfig +3 -0

index fd01836..6c437df 100644
@@ -81,6 +81,16 @@ config MFD_DM355EVM_MSP
  boards.  MSP430 firmware manages resets and power sequencing,
  inputs from buttons and the IR remote, LEDs, an RTC, and more.
 
+config MFD_DA8XX_PRUSS
+ tristate "Texas Instruments DA8XX PRUSS support"
+ depends on ARCH_DAVINCI && ARCH_DAVINCI_DA850

Why are we depending on those ?

Quoted 2 lines

SG -- The PRUSS core in only available within DA850 and DA830,
DA830 support is not yet implemented.

Sure, but if there are no actual code dependencies, I'd like to get rid of those depends.

Quoted 20 lines

Quoted 20 lines

drivers/mfd/Kconfig config MFD_DM355EVM_MSP · line 96

Quoted 11 lines

drivers/mfd/Kconfig +10 -0

+u32 pruss_disable(struct device *dev, u8 pruss_num)
+{
+ struct da8xx_pruss *pruss = dev_get_drvdata(dev->parent);
+ da8xx_prusscore_regs h_pruss;
+ u32 temp_reg;
+
+ if (pruss_num == DA8XX_PRUCORE_0) {
+ /* Disable PRU0  */
+ h_pruss = (da8xx_prusscore_regs)
+ ((u32) pruss->ioaddr + 0x7000);

So it seems you're doing this in several places, and I have a few comments:

- You don't need the da8xx_prusscore_regs at all.
- Define the register map through a set of #define in your header file.
- Use a static routine that takes the core number and returns the register map
offset.

Quoted 5 lines

Quoted 1 line

Then routines like this one will look a lot more readable.

SG -- There are a huge number of PRUSS registers. A lot of them are reserved and are expected to change as development on the
controller is still ongoing.

First of all, from what I read in your patch you're only using the CONTROL offset.

Quoted 3 lines

If we use #defines to plot
all the registers, then first, there are too many array type registers which will need to be duplicated.

What I'm expecting is a small set of defines for the register offsets. You have 13 fields in your da8xx_prusscore_regs, you only need to define 13 register offsets.

So, if you have a:

static u32 reg_offset(struct device *dev, u8 pru_num) {
struct da8xx_pruss *pru = dev_get_drvdata(dev->parent);

switch (pru_num) {
case DA8XX_PRUCORE_0:
return (u32) pru->ioaddr + 0x7000;
case DA8XX_PRUCORE_1:
return (u32) pru->ioaddr + 0x7800;
default:
return 0;
}

then routines like pruss_enable (which should return an int, btw) would look like:

int pruss_enable(struct device *dev, u8 pruss_num) {
u32 offset = reg_offset(dev, pruss_num);

if (offset == 0)
return -EINVAL;

__raw_writel(DA8XX_PRUCORE_CONTROL_RESETVAL,
offset + PRU_CORE_CONTROL);

return 0;
}

Quoted 8 lines

Quoted 2 lines

Also, all your exported routines severely lack any sort of locking. An IO mutex or spinlock is mandatory here.

SG - As per our current implementation, we do not have two devices running simultaneously on the PRU,
so we do not have any way to test it. We have kept this as an
enhancement if request comes in for
multiple devices.

It's not about having multiple devices at the same time, it's about having multiple callers writing and reading to the same registers. Since you're exporting all your I/O routines you have no way to prevent 2 drivers from writing to the same register at the "same" time. You need locking here, regardless of the number of devices that you can have on a system.

Quoted 29 lines

Quoted 20 lines

Quoted 20 lines

drivers/mfd/Kconfig +19 -0

+static int pruss_mfd_add_devices(struct platform_device *pdev)
+{
+ struct da8xx_pruss_devices *dev_data = pdev->dev.platform_data;
+ struct device *dev = &pdev->dev;
+ struct mfd_cell cell;
+ u32 err, count;
+
+ for (count = 0; (dev_data + count)->dev_name != NULL; count++) {
+ memset(&cell, 0, sizeof(struct mfd_cell));
+ cell.id = count;
+ cell.name = (dev_data + count)->dev_name;
+ cell.platform_data = (dev_data + count)->pdata;
+ cell.data_size = (dev_data + count)->pdata_size;
+
+ err = mfd_add_devices(dev, 0, &cell, 1, NULL, 0);
+ if (err) {
+ dev_err(dev, "cannot add mfd cells\n");
+ return err;
+ }

Quoted 8 lines

Quoted 3 lines

+ }
+ return err;
+}

So, what are the potential subdevices for this driver ? If it's a really dynamic setup, I'm fine with passing those as platform data but then do it so
that you pass a NULL terminated da8xx_pruss_devices array. That will avoid most of the ugly casts you're doing here.

Quoted 7 lines

SG -- I did not follow your recommendations here, could you please elaborate.
I am already checking the dev_name for a NULL. This device is basically a microcontroller within DA850,
so basically any device or protocol can be
emulated on it. Currently, we have emulated 8 UARTS using
the two PRUs and also a CAN device.

Ok, I wasnt sure you can emulate anything on that thing. So I'm fine with you passing all your devices through platform_data. But I'd prefer this routine to look like:

[...]
for (count = 0; dev_data[count] != NULL; count++) { memset(&cell, 0, sizeof(struct mfd_cell)); cell.id = count;
cell.name = dev_data[count]->dev_name; cell.platform_data = dev_data[count]->pdata; cell.data_size = dev_data[count]->pdata_size;

Looks nicer to me.

Cheers,
Samuel.

Signature · 2 lines

Intel Open Source Technology Centre
http://oss.intel.com/ 

So, if you have a:

static u32 reg_offset(struct device *dev, u8 pru_num)

{
	struct da8xx_pruss *pru = dev_get_drvdata(dev->parent);

	switch (pru_num) {
	case DA8XX_PRUCORE_0:
		return (u32) pru->ioaddr + 0x7000;
	case DA8XX_PRUCORE_1:
		return (u32) pru->ioaddr + 0x7800;
	default:
		return 0;
}

This patch adds the platform device and assignes the platform resources for the PRUSS mfd driver.

Signed-off-by Subhasish Ghosh <[email protected]>

Hello.

Quoted 2 lines · Subhasish Ghosh

This patch adds the platform device and assignes the platform resources for the PRUSS mfd driver.

You also add the PRUSS clock (and I would have done that as a separate
patch).

Quoted 1 line

Signed-off-by Subhasish Ghosh <[email protected]>

You should have noted the patch dependency here -- this patch depends
on the one nenaming DA8XX_LPSC0_DMAX.

WBR, Sergei

-----Original Message-----
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Subhasish Ghosh
Sent: Friday, February 11, 2011 8:21 PM
To: davinci-linux-open-source at linux.davincidsp.com
Cc: sachi at mistralsolutions.com; Russell King; Kevin Hilman; Subhasish Ghosh; open list; Watkins, Melissa; linux-arm-kernel at lists.infradead.org
Subject: [PATCH v2 02/13] da850: pruss platform specific additions.

This patch adds the platform device and assignes the platform resources for the PRUSS mfd driver.

Signed-off-by Subhasish Ghosh <[email protected]>

---
+struct platform_device da8xx_pruss_dev = {

Hi,

Quoted 10 lines

-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of Subhasish Ghosh
Sent: Friday, February 11, 2011 8:21 PM
To: [email protected]
Cc: [email protected]; Russell King; Kevin Hilman; Subhasish Ghosh; open list; Watkins, Melissa; [email protected]
Subject: [PATCH v2 02/13] da850: pruss platform specific additions.

Quoted 6 lines

This patch adds the platform device and assignes the platform resources for the PRUSS mfd driver.

Signed-off-by Subhasish Ghosh <[email protected]>

---
+struct platform_device da8xx_pruss_dev = {

Can you please rename this to da8xx_pruss_mfddev?

Quoted 1 line

+ .name = "da8xx_pruss",

Can you please rename name string as pruss_mfd? This will help to base my UIO patches on top of yours.

Quoted 7 lines

+ .id = -1,
+ .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
+ .resource = da8xx_pruss_resources,

arch/arm/mach-davinci/da850.c +3 -0

+};
+
+int __init da8xx_register_pruss(struct da8xx_pruss_devices 

*pruss_device)

Please rename this to da8xx_register_pruss_mfd

Thanks,
Pratheesh

-----Original Message-----
From: Subhasish Ghosh [mailto:subhasish at mistralsolutions.com]
Sent: Tuesday, March 01, 2011 12:29 PM
Hello,

Can we not have the PRU UIO also as a part of the MFD framework. I know that the UIO is not really a device, but I feel its incorrect to register the same device twice.
Instead we can have a single entry as the MFD framework and the UIO, as a child device, based upon the MFD driver APIs.

All that we need to do is add an entry into the da8xx_pruss_devices structure
and the MFD driver will do the rest to get the UIO probe called.

This patch adds board specific initializations and setup routines.

Signed-off-by Subhasish Ghosh <[email protected]>

Quoted 3 lines · Subhasish Ghosh

This patch adds board specific initializations and setup routines.

Signed-off-by Subhasish Ghosh <[email protected]>

[...]

arch/arm/mach-davinci/board-da850-evm.c static __init int da850_evm_init_cpufreq(void) · line 1056

Quoted 9 lines

arch/arm/mach-davinci/board-da850-evm.c +1 -0

index 11f986b..242d1ed 100644
@@ -1053,6 +1053,26 @@ static __init int da850_evm_init_cpufreq(void)
 static __init int da850_evm_init_cpufreq(void) { return 0; }
 #endif
 +static struct da8xx_pruss_devices pruss_devices[] = {
+ {.dev_name = NULL,},

No need to explicitly initialize to NULL.

WBR, Sergei

This patch adds the pruss CAN pin mux and registers the device with the pruss mfd driver.

Signed-off-by Subhasish Ghosh <[email protected]>

arch/arm/mach-davinci/board-da850-evm.c +0 -0

index 242d1ed..2ce5536 100644
@@ -1053,8 +1053,43 @@ static __init int da850_evm_init_cpufreq(void)

Quoted 4 lines · Subhasish Ghosh

This patch adds the pruss CAN pin mux and registers the device with the pruss mfd driver.

Signed-off-by Subhasish Ghosh <[email protected]>

[...]

Quoted 6 lines

arch/arm/mach-davinci/board-da850-evm.c +0 -0

index 242d1ed..2ce5536 100644
@@ -1053,8 +1053,43 @@ static __init int da850_evm_init_cpufreq(void)

[...]

Quoted 11 lines

static struct da8xx_pruss_devices pruss_devices[] = {
- {.dev_name = NULL,},
+ {
+ .dev_name = "da8xx_pruss_can",
+ .pdata = &can_data,
+ .pdata_size = sizeof(can_data),
+ .setup = da850_evm_setup_pruss_can,
+ },
+ {
+ .dev_name = NULL,
+ },

No need to explicitly initialize to NULL.

WBR, Sergei

Quoted 4 lines · Subhasish Ghosh

This patch adds the pruss CAN pin mux and registers the device with the pruss mfd driver.

Signed-off-by Subhasish Ghosh <[email protected]>

[...]

Quoted 6 lines

arch/arm/mach-davinci/board-da850-evm.c +0 -0

index 242d1ed..2ce5536 100644
@@ -1053,8 +1053,43 @@ static __init int da850_evm_init_cpufreq(void)

[...]

Quoted 11 lines

static struct da8xx_pruss_devices pruss_devices[] = {
- {.dev_name = NULL,},
+ {
+ .dev_name = "da8xx_pruss_can",
+ .pdata = &can_data,
+ .pdata_size = sizeof(can_data),
+ .setup = da850_evm_setup_pruss_can,
+ },
+ {
+ .dev_name = NULL,
+ },

No need to explicitly initialize to NULL.

WBR, Sergei

This patch adds the GPIOs for the pruss CAN device.

Signed-off-by Subhasish Ghosh <[email protected]>

Hello.

Quoted 3 lines · Subhasish Ghosh

This patch adds the GPIOs for the pruss CAN device.

Signed-off-by Subhasish Ghosh <[email protected]>

I still think this patch should be merged with patch 5, and patch 8
with patch 6...

WBR, Sergei

drivers/net/can/da8xx_pruss/Kconfig new file +53 -0

+config DA8XX_PRU_CANID_MBX0
+	hex "CANID for mailbox 0"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	---help---
+	Enter the CANID for mailbox 0
+	Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX1
+	hex "CANID for mailbox 1"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	 ---help---
+	Enter the CANID for mailbox 1
+	Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX2
+	hex "CANID for mailbox 2"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	---help---
+	Enter the CANID for mailbox 2
+	Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX3
+	hex "CANID for mailbox 3"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	---help---
+	Enter the CANID for mailbox 3
+	Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX4
+	hex "CANID for mailbox 4"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	---help---
+	Enter the CANID for mailbox 4
+	Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX5
+	hex "CANID for mailbox 5"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	---help---
+	Enter the CANID for mailbox 5
+	Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX6
+	hex "CANID for mailbox 6"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	---help---

Quoted 53 lines

drivers/net/can/da8xx_pruss/Kconfig new file +53 -0

+config DA8XX_PRU_CANID_MBX0
+ hex "CANID for mailbox 0"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 0
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX1
+ hex "CANID for mailbox 1"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 1
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX2
+ hex "CANID for mailbox 2"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 2
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX3
+ hex "CANID for mailbox 3"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 3
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX4
+ hex "CANID for mailbox 4"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 4
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX5
+ hex "CANID for mailbox 5"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 5
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX6
+ hex "CANID for mailbox 6"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---

drivers/net/can/da8xx_pruss/Kconfig line 73

Quoted 10 lines

drivers/net/can/da8xx_pruss/Kconfig new file +10 -0

+ Enter the CANID for mailbox 6
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX7
+ hex "CANID for mailbox 7"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 7
+ Default value is set to 0x123, change this as required.

Why is filling the mailboxes the job of kernel config?

Regards,
Kurt

Hello,

I had a discussion regarding this with Wolfgang:

http://www.mail-archive.com/[email protected]/msg00324.html

The problem here is that we must configure the mailbox ID's and this support is not available in the socketCan sub-system.

Quoted 8 lines · Subhasish Ghosh

Hello,

I had a discussion regarding this with Wolfgang:

http://www.mail-archive.com/socketcan-users at lists.berlios.de/msg00324.html

The problem here is that we must configure the mailbox ID's and this support is not available in the socketCan sub-system.

Using SysFS files would already be much better.

Quoted 8 lines

Hello,

I had a discussion regarding this with Wolfgang:

http://www.mail-archive.com/[email protected]/msg00324.html

The problem here is that we must configure the mailbox ID's and this support is not available in the socketCan sub-system.

To understand you correctly. A mailbox (or message object) can *only* receive messages with the pre-programmed CAN id? Isn't there a chance to receive all or a range of CAN ids? That's a very unusual piece of hardware. Anyway, using kernel configuration parameters to define the CAN id's would be the less flexible method. The user will not have a chance to change them at run-time. Using SysFS files would already be much better.

Wolfgang.

That is correct, we receive only pre-programmed CAN ids and "all" or "range" implementation is not there in the PRU firmware.

That is correct, we receive only pre-programmed CAN ids and "all" or "range" implementation is not there in the PRU firmware.

That is correct, we receive only pre-programmed CAN ids and "all" or "range" implementation is not there in the PRU firmware.

Hello,

The problem with the "all" implementation is that it hogs the ARM/DSP heavily and that's the reason why we specifically avoided this in our firmware design.
Hence, implementing this condition spoils the whole purpose of the PRU!!

Hello,

The problem with the "all" implementation is that it hogs the ARM/DSP heavily and that's the reason why we specifically avoided this in our firmware design.
Hence, implementing this condition spoils the whole purpose of the PRU!!

--------------------------------------------------
From: "Marc Kleine-Budde" <[email protected]>
Sent: Monday, February 14, 2011 3:05 PM
To: "Subhasish Ghosh" <subhasish-EvXpCiN+lbve9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Cc: "Wolfgang Grandegger" <[email protected]>; "Kurt Van Dijck" <kurt.van.dijck-/[email protected]>; <davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org>; <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>; <[email protected]>; <[email protected]>; <sachi-EvXpCiN+lbve9wHmmfpqLFaTQe2KTcn/@public.gmane.org>; "open list:CAN NETWORK DRIVERS" <[email protected]>; "open list:CAN NETWORK
DRIVERS" <[email protected]>; "open list" <[email protected]>
Subject: Re: [PATCH v2 09/13] can: pruss CAN driver.

Hello,

Quoted 2 lines · Subhasish Ghosh

That is correct, we receive only pre-programmed CAN ids and "all" or "range" implementation is not there in the PRU firmware.

I'd really like to see that you add a "all" implementation to the firmware. Or even better use the standard id/mask approach.

cheers, Marc

drivers/net/can/da8xx_pruss/pruss_can.c new file +8 -0

+	}
+	if (pru_can_calc_timing(priv->dev, priv->can.clock.freq,
+				bt->bitrate) != 0)
+		return -EINVAL;
+	bit_error =
+	    (((priv->timer_freq / (priv->timer_freq / bt->bitrate)) -
+	      bt->bitrate) * 1000) / bt->bitrate;
+	if (bit_error) {

drivers/net/can/da8xx_pruss/pruss_can.c new file +21 -0

+	if (cf->can_id & CAN_EFF_FLAG)	/* Extended frame format */
+		*((u32 *) &priv->can_tx_hndl.strcanmailbox) =
+		    (cf->can_id & CAN_EFF_MASK) | PRU_CANMID_IDE;
+	else			/* Standard frame format */
+		*((u32 *) &priv->can_tx_hndl.strcanmailbox) =
+		    (cf->can_id & CAN_SFF_MASK) << 18;
+
+	if (cf->can_id & CAN_RTR_FLAG)	/* Remote transmission request */
+		*((u32 *) &priv->can_tx_hndl.strcanmailbox) |= CAN_RTR_FLAG;
+
+	ptr8data = &priv->can_tx_hndl.strcanmailbox.u8data7 + (dlc - 1);
+	for (count = 0; count < (u8) dlc; count++) {
+		*ptr8data-- = *data++;
+	}
+	*((u32 *) &priv->can_tx_hndl.strcanmailbox.u16datalength) = (u32) dlc;
+/*
+ * search for the next available mbx
+ * if the next mbx is busy, then try the next + 1
+ * do this until the head is reached.
+ * if still unable to tx, stop accepting any packets
+ * if able to tx and the head is reached, then reset next to tail, i.e mbx0

drivers/net/can/da8xx_pruss/pruss_can.c new file +53 -0

+					netif_stop_queue(ndev);	/* IF stalled */
+				dev_err(priv->dev,
+					"%s: no tx mbx available", __func__);
+				return NETDEV_TX_BUSY;
+			} else
+				continue;
+		} else {
+			/* set transmit request */
+			pru_can_tx(priv->dev, priv->tx_next, CAN_TX_PRU_1);
+			pru_can_tx_mode_set(priv->dev, false, ecanreceive);
+			pru_can_tx_mode_set(priv->dev, true, ecantransmit);
+			pru_can_start_abort_tx(priv->dev, PRU_CAN_START);
+			priv->tx_next++;
+			can_put_echo_skb(skb, ndev, 0);
+			break;
+		}
+	}
+	if (priv->tx_next > priv->tx_head) {
+		priv->tx_next = priv->tx_tail;
+	}
+	return NETDEV_TX_OK;
+}
+
+
 
+irqreturn_t omapl_tx_can_intr(int irq, void *dev_id)
+{
+	struct net_device *ndev = dev_id;
+	struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 bit_set, mbxno;
+
+	pru_can_get_intr_status(priv->dev, &priv->can_tx_hndl);
+	if ((PRU_CAN_ISR_BIT_CCI & priv->can_tx_hndl.u32interruptstatus)
+	    || (PRU_CAN_ISR_BIT_SRDI & priv->can_tx_hndl.u32interruptstatus)) {
+		__can_debug("tx_int_status = 0x%X\n",
+			    priv->can_tx_hndl.u32interruptstatus);
+		can_free_echo_skb(ndev, 0);
+	} else {
+		for (bit_set = 0; ((priv->can_tx_hndl.u32interruptstatus & 0xFF)
+						>> bit_set != 0); bit_set++)
+		;
+		if (0 == bit_set) {
+			__can_err("%s: invalid mailbox number\n", __func__);
+			can_free_echo_skb(ndev, 0);
+		} else {
+			mbxno = bit_set - 1;	/* mail box numbering starts from 0 */
+			if (PRU_CAN_ISR_BIT_ESI & priv->can_tx_hndl.
+			    u32interruptstatus) {
+				/* read gsr and ack pru */
+				pru_can_get_global_status(priv->dev, &priv->can_tx_hndl);
+				omapl_pru_can_err(ndev,
+						  priv->can_tx_hndl.
+						  u32interruptstatus,

drivers/net/can/da8xx_pruss/pruss_can.c new file +5 -0

+		netif_wake_queue(ndev);
+
+	can_get_echo_skb(ndev, 0);
+	pru_can_tx_mode_set(priv->dev, true, ecanreceive);
+	return IRQ_HANDLED;

Hi,

I looked a bit at the TX path:

On Fri, Feb 11, 2011 at 08:21:28PM +0530, Subhasish Ghosh wrote:

drivers/net/can/da8xx_pruss/pruss_can.c line 124

Quoted 9 lines

drivers/net/can/da8xx_pruss/pruss_can.c new file +9 -0

+static int omapl_pru_can_set_bittiming(struct net_device *ndev)
+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ struct can_bittiming *bt = &priv->can.bittiming;
+ long bit_error = 0;
+
+ if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
+ dev_warn(priv->dev, "WARN: Triple"
+ "sampling not set due to h/w limitations");

You should not have enabled CAN_CTRLMODE_3_SAMPLES in the first place?

Quoted 11 lines

+ }
+ if (pru_can_calc_timing(priv->dev, priv->can.clock.freq,
+ bt->bitrate) != 0)
+ return -EINVAL;
+ bit_error =

drivers/net/can/da8xx_pruss/pruss_can.c new file +6 -0

+     (((priv->timer_freq / (priv->timer_freq / bt->bitrate)) -
+       bt->bitrate) * 1000) / bt->bitrate;
+ if (bit_error) {
+ bit_error =
+     (((priv->timer_freq / (priv->timer_freq / bt->bitrate)) -
+       bt->bitrate) * 1000000) / bt->bitrate;

drivers/net/can/da8xx_pruss/pruss_can.c line 114

Quoted 7 lines

+ printk(KERN_INFO "\nBitrate error %ld.%ld%%\n",
+ bit_error / 10000, bit_error % 1000);
+ } else
+ printk(KERN_INFO "\nBitrate error 0.0%%\n");

drivers/net/can/da8xx_pruss/pruss_can.c new file +3 -0

+
+ return 0;
+}

I wonder how much of this code is duplicated from drivers/net/can/dev.c ?

drivers/net/can/da8xx_pruss/pruss_can.c line 210

Quoted 11 lines

drivers/net/can/da8xx_pruss/pruss_can.c new file +10 -0

+static netdev_tx_t omapl_pru_can_start_xmit(struct sk_buff *skb,
+     struct net_device *ndev)
+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ struct can_frame *cf = (struct can_frame *)skb->data;
+ int count;
+ u8 *data = cf->data;
+ u8 dlc = cf->can_dlc;
+ u8 *ptr8data = NULL;
+

most drivers start with:
if (can_dropped_invalid_skb(dev, skb))
return NETDEV_TX_OK;

Quoted 2 lines

+ netif_stop_queue(ndev);

why would you stop when you just resumed the queue?

Quoted 25 lines

+ if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
+ *((u32 *) &priv->can_tx_hndl.strcanmailbox) =

drivers/net/can/da8xx_pruss/pruss_can.c new file +19 -0

+     (cf->can_id & CAN_EFF_MASK) | PRU_CANMID_IDE;
+ else /* Standard frame format */
+ *((u32 *) &priv->can_tx_hndl.strcanmailbox) =
+     (cf->can_id & CAN_SFF_MASK) << 18;
+
+ if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
+ *((u32 *) &priv->can_tx_hndl.strcanmailbox) |= CAN_RTR_FLAG;
+
+ ptr8data = &priv->can_tx_hndl.strcanmailbox.u8data7 + (dlc - 1);
+ for (count = 0; count < (u8) dlc; count++) {
+ *ptr8data-- = *data++;
+ }
+ *((u32 *) &priv->can_tx_hndl.strcanmailbox.u16datalength) = (u32) dlc;
+/*
+ * search for the next available mbx
+ * if the next mbx is busy, then try the next + 1
+ * do this until the head is reached.
+ * if still unable to tx, stop accepting any packets
+ * if able to tx and the head is reached, then reset next to tail, i.e 

mbx0
+ * if head is not reached, then just point to the next mbx
+ */
+ for (; priv->tx_next <= priv->tx_head; priv->tx_next++) {

Quoted 7 lines

+ priv->can_tx_hndl.ecanmailboxnumber =
+ (can_mailbox_number) priv->tx_next;
+ if (-1 == pru_can_write_data_to_mailbox(priv->dev,
+ &priv->can_tx_hndl)) {
+ if (priv->tx_next == priv->tx_head) {
+ priv->tx_next = priv->tx_tail;
+ if (!netif_queue_stopped(ndev))

If you get here, the queue is not stopped. This test is therefore useless.

Quoted 58 lines

+ netif_stop_queue(ndev); /* IF stalled */
+ dev_err(priv->dev,
+ "%s: no tx mbx available", __func__);
+ return NETDEV_TX_BUSY;
+ } else
+ continue;
+ } else {
+ /* set transmit request */
+ pru_can_tx(priv->dev, priv->tx_next, CAN_TX_PRU_1);
+ pru_can_tx_mode_set(priv->dev, false, ecanreceive);
+ pru_can_tx_mode_set(priv->dev, true, ecantransmit);
+ pru_can_start_abort_tx(priv->dev, PRU_CAN_START);
+ priv->tx_next++;
+ can_put_echo_skb(skb, ndev, 0);
+ break;
+ }
+ }
+ if (priv->tx_next > priv->tx_head) {
+ priv->tx_next = priv->tx_tail;
+ }
+ return NETDEV_TX_OK;

drivers/net/can/da8xx_pruss/pruss_can.c new file +36 -0

+}
+
+
 
+irqreturn_t omapl_tx_can_intr(int irq, void *dev_id)
+{
+ struct net_device *ndev = dev_id;
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ struct net_device_stats *stats = &ndev->stats;
+ u32 bit_set, mbxno;
+
+ pru_can_get_intr_status(priv->dev, &priv->can_tx_hndl);
+ if ((PRU_CAN_ISR_BIT_CCI & priv->can_tx_hndl.u32interruptstatus)
+     || (PRU_CAN_ISR_BIT_SRDI & priv->can_tx_hndl.u32interruptstatus)) {
+ __can_debug("tx_int_status = 0x%X\n",
+     priv->can_tx_hndl.u32interruptstatus);
+ can_free_echo_skb(ndev, 0);
+ } else {
+ for (bit_set = 0; ((priv->can_tx_hndl.u32interruptstatus & 0xFF)
+ >> bit_set != 0); bit_set++)
+ ;
+ if (0 == bit_set) {
+ __can_err("%s: invalid mailbox number\n", __func__);
+ can_free_echo_skb(ndev, 0);
+ } else {
+ mbxno = bit_set - 1; /* mail box numbering starts from 0 */
+ if (PRU_CAN_ISR_BIT_ESI & priv->can_tx_hndl.
+     u32interruptstatus) {
+ /* read gsr and ack pru */
+ pru_can_get_global_status(priv->dev, &priv->can_tx_hndl);
+ omapl_pru_can_err(ndev,
+   priv->can_tx_hndl.
+   u32interruptstatus,
+   priv->can_tx_hndl.
+   u32globalstatus);
+ } else {
+ stats->tx_packets++;

Quoted 6 lines

+ /* stats->tx_bytes += dlc; */
+ /*can_get_echo_skb(ndev, 0);*/
+ }
+ }
+ }
+ if (netif_queue_stopped(ndev))

you can call netif_wake_queue(ndev) multiple times, so there is no need for netif_queue_stopped()

Quoted 8 lines

+ netif_wake_queue(ndev);

drivers/net/can/da8xx_pruss/pruss_can.c new file +7 -0

+
+ can_get_echo_skb(ndev, 0);
+ pru_can_tx_mode_set(priv->dev, true, ecanreceive);
+ return IRQ_HANDLED;
+}
+
+static int omapl_pru_can_open(struct net_device *ndev)

drivers/net/can/da8xx_pruss/pruss_can.c line 494

Quoted 7 lines

drivers/net/can/da8xx_pruss/pruss_can.c new file +7 -0

+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ int err;
+
+ /* register interrupt handler */
+ err = request_irq(priv->trx_irq, &omapl_rx_can_intr, IRQF_SHARED,
+   "pru_can_irq", ndev);

you're doing a lot of work _in_ the irq handler. Maybe threaded irq?

drivers/net/can/da8xx_pruss/pruss_can.c line 533

Quoted 5 lines

drivers/net/can/da8xx_pruss/pruss_can.c new file +5 -0

+static int omapl_pru_can_close(struct net_device *ndev)
+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+
+ if (!netif_queue_stopped(ndev))

check is not needed.

drivers/net/can/da8xx_pruss/pruss_can.c line 541

Quoted 8 lines

+ netif_stop_queue(ndev);

drivers/net/can/da8xx_pruss/pruss_can.c new file +7 -0

+
+ close_candev(ndev);
+
+ free_irq(priv->trx_irq, ndev);
+ return 0;
+}
+

Regards,
Kurt

--------------------------------------------------
From: "Kurt Van Dijck" <kurt.van.dijck-/[email protected]>

Quoted 5 lines

Quoted 3 lines

+ /* register interrupt handler */
+ err = request_irq(priv->trx_irq, &omapl_rx_can_intr, IRQF_SHARED,
+ "pru_can_irq", ndev);

you're doing a lot of work _in_ the irq handler. Maybe threaded irq?

SG -Ok, will do

Quoted 2 lines

--------------------------------------------------
From: "Kurt Van Dijck" <[email protected]>

...

Quoted 6 lines

Quoted 5 lines

Quoted 3 lines

+ /* register interrupt handler */
+ err = request_irq(priv->trx_irq, &omapl_rx_can_intr, IRQF_SHARED,
+ "pru_can_irq", ndev);

you're doing a lot of work _in_ the irq handler. Maybe threaded irq?

SG -Ok, will do

No, please use NAPI instead.

Quoted 10 lines · Subhasish Ghosh

Quoted 2 lines

--------------------------------------------------
From: "Kurt Van Dijck" <[email protected]>

...

Quoted 5 lines

Quoted 5 lines

Quoted 3 lines

+ /* register interrupt handler */
+ err = request_irq(priv->trx_irq, &omapl_rx_can_intr, IRQF_SHARED,
+ "pru_can_irq", ndev);

you're doing a lot of work _in_ the irq handler. Maybe threaded irq?

Quoted 3 lines

Quoted 1 line

SG -Ok, will do

No, please use NAPI instead.

We are using h/w filters, so the number of interrupts coming into the processor are not hogging it.
I feel that we may not require an interrupt mitigation.

Quoted 10 lines · Subhasish Ghosh

Quoted 2 lines

--------------------------------------------------
From: "Kurt Van Dijck" <[email protected]>

...

Quoted 5 lines

Quoted 5 lines

Quoted 3 lines

+ /* register interrupt handler */
+ err = request_irq(priv->trx_irq, &omapl_rx_can_intr, IRQF_SHARED,
+ "pru_can_irq", ndev);

you're doing a lot of work _in_ the irq handler. Maybe threaded irq?

Quoted 3 lines

Quoted 1 line

SG -Ok, will do

No, please use NAPI instead.

We are using h/w filters, so the number of interrupts coming into the processor are not hogging it.
I feel that we may not require an interrupt mitigation.

This patch adds support for the CAN device emulated on PRUSS.

Signed-off-by Subhasish Ghosh <subhasish-EvXpCiN+lbve9wHmmfpqLFaTQe2KTcn/@public.gmane.org>

---
 drivers/net/can/Kconfig                     |    1 +
 drivers/net/can/Makefile                    |    1 +
 drivers/net/can/da8xx_pruss/Kconfig         |   73 ++
 drivers/net/can/da8xx_pruss/Makefile        |    7 +
 drivers/net/can/da8xx_pruss/pruss_can.c     |  758 +++++++++++++++++
 drivers/net/can/da8xx_pruss/pruss_can_api.c | 1227 +++++++++++++++++++++++++++
 drivers/net/can/da8xx_pruss/pruss_can_api.h |  290 +++++++
 7 files changed, 2357 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/can/da8xx_pruss/Kconfig
 create mode 100644 drivers/net/can/da8xx_pruss/Makefile
 create mode 100644 drivers/net/can/da8xx_pruss/pruss_can.c
 create mode 100644 drivers/net/can/da8xx_pruss/pruss_can_api.c
 create mode 100644 drivers/net/can/da8xx_pruss/pruss_can_api.h

drivers/net/can/Kconfig +1 -0

index d5a9db6..ae8f0f9 100644
@@ -112,6 +112,7 @@ config PCH_CAN
 	  This driver can access CAN bus.
 
 source "drivers/net/can/mscan/Kconfig"
+source "drivers/net/can/da8xx_pruss/Kconfig"
 
 source "drivers/net/can/sja1000/Kconfig"
 

drivers/net/can/Makefile +0 -0

index 07ca159..849cdbf 100644

drivers/net/can/Makefile +0 -0

 obj-$(CONFIG_CAN_MCP251X)	+= mcp251x.o
 obj-$(CONFIG_CAN_BFIN)		+= bfin_can.o
 obj-$(CONFIG_CAN_JANZ_ICAN3)	+= janz-ican3.o

drivers/net/can/da8xx_pruss/Kconfig new file +63 -0

new file mode 100644
index 0000000..8b68f68
@@ -0,0 +1,73 @@
+#
+# CAN Lite Kernel Configuration
+#
+config CAN_TI_DA8XX_PRU
+	depends on CAN_DEV && ARCH_DAVINCI && ARCH_DAVINCI_DA850
+	tristate "PRU based CAN emulation for DA8XX"
+	---help---
+	Enable this to emulate a CAN controller on the PRU of DA8XX.
+	If not sure, mark N
+
+config DA8XX_PRU_CANID_MBX0
+	hex "CANID for mailbox 0"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	---help---
+	Enter the CANID for mailbox 0
+	Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX1
+	hex "CANID for mailbox 1"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	 ---help---
+	Enter the CANID for mailbox 1
+	Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX2
+	hex "CANID for mailbox 2"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	---help---
+	Enter the CANID for mailbox 2
+	Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX3
+	hex "CANID for mailbox 3"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	---help---
+	Enter the CANID for mailbox 3
+	Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX4
+	hex "CANID for mailbox 4"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	---help---
+	Enter the CANID for mailbox 4
+	Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX5
+	hex "CANID for mailbox 5"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	---help---
+	Enter the CANID for mailbox 5
+	Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX6
+	hex "CANID for mailbox 6"
+	depends on CAN_TI_DA8XX_PRU
+	default "0x123"
+	---help---

drivers/net/can/da8xx_pruss/pruss_can.c new file +73 -0

new file mode 100644
index 0000000..1b3afde
@@ -0,0 +1,758 @@
+/*
+ *  TI DA8XX PRU CAN Emulation device driver
+ *  Author: subhasish-EvXpCiN+lbve9wHmmfpqLFaTQe2KTcn/@public.gmane.org
+ *
+ *  This driver supports TI's PRU CAN Emulation and the
+ *  specs for the same is available at <http://www.ti.com>
+ *
+ *  Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License as
+ *  published by the Free Software Foundation version 2.
+ *
+ *  This program is distributed as is WITHOUT ANY WARRANTY of any
+ *  kind, whether express or implied; without even the implied warranty
+ *  of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/skbuff.h>
+#include <linux/platform_device.h>
+#include <linux/firmware.h>
+#include <linux/clk.h>
+#include <linux/types.h>
+
+#include <linux/can.h>
+#include <linux/can/dev.h>
+#include <linux/can/error.h>
+#include <mach/da8xx.h>
+#include "pruss_can_api.h"
+
+#define DRV_NAME "da8xx_pruss_can"
+#define DRV_DESC "TI PRU CAN Controller Driver v0.1"
+#define PRU_CAN_START		1
+#define PRU_CAN_STOP		0
+#define MB_MIN			0
+#define MB_MAX			7
+
+#define PRU_CANMID_IDE			BIT(29)	/* Extended frame format */
+
+#define PRU_CAN_ISR_BIT_CCI		BIT(15)
+#define PRU_CAN_ISR_BIT_ESI		BIT(14)
+#define PRU_CAN_ISR_BIT_SRDI		BIT(13)
+#define PRU_CAN_ISR_BIT_RRI		BIT(8)
+
+#define PRU_CAN_MBXSR_BIT_STATE		BIT(7)
+#define PRU_CAN_MBXSR_BIT_TC		BIT(6)
+#define PRU_CAN_MBXSR_BIT_ERR		BIT(5)
+#define PRU_CAN_MBXSR_BIT_OF		BIT(0)
+
+#define PRU_CAN_GSR_BIT_TXM		BIT(7)
+#define PRU_CAN_GSR_BIT_RXM		BIT(6)
+#define PRU_CAN_GSR_BIT_CM		BIT(5)
+#define PRU_CAN_GSR_BIT_EPM		BIT(4)
+#define PRU_CAN_GSR_BIT_BFM		BIT(3)
+#define RTR_MBX_NO			8
+#define MAX_INIT_RETRIES		20
+#define L138_PRU_ARM_FREQ		312000
+#define DFLT_PRU_FREQ			156000000
+#define DFLT_PRU_BITRATE		125000
+
+#define CONFIG_DA8XX_PRU_CANID_MBX0	0x123
+#define CONFIG_DA8XX_PRU_CANID_MBX1	0x123
+#define CONFIG_DA8XX_PRU_CANID_MBX2	0x123
+#define CONFIG_DA8XX_PRU_CANID_MBX3	0x123
+#define CONFIG_DA8XX_PRU_CANID_MBX4	0x123

drivers/net/can/da8xx_pruss/pruss_can.c new file +20 -0

+/*
+ * omapl_pru can private data
+ */
+struct omapl_pru_can_priv {
+	struct can_priv can;
+	struct workqueue_struct *pru_can_wQ;
+	struct work_struct rx_work;
+	struct net_device *ndev;
+	struct device *dev; /* pdev->dev */
+	struct clk *clk_timer;
+	u32 timer_freq;
+	can_emu_app_hndl can_tx_hndl;
+	can_emu_app_hndl can_rx_hndl;
+	const struct firmware *fw_rx;
+	const struct firmware *fw_tx;
+	spinlock_t mbox_lock;
+	u32 trx_irq;
+	u32 tx_head;
+	u32 tx_tail;
+	u32 tx_next;

drivers/net/can/da8xx_pruss/pruss_can.c new file +6 -0

+	if (pru_can_calc_timing(priv->dev, priv->can.clock.freq,
+				bt->bitrate) != 0)
+		return -EINVAL;
+	bit_error =
+	    (((priv->timer_freq / (priv->timer_freq / bt->bitrate)) -
+	      bt->bitrate) * 1000) / bt->bitrate;

drivers/net/can/da8xx_pruss/pruss_can.c new file +20 -0

+}
+
+static void omapl_pru_can_stop(struct net_device *ndev)
+{
+	struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+	u16 int_mask = 0;
+
+	pru_can_mask_ints(priv->dev, int_mask);	/* mask all ints */
+	pru_can_start_abort_tx(priv->dev, PRU_CAN_STOP);
+	priv->can.state = CAN_STATE_STOPPED;
+}
+
+/*
+ * This is to just set the can state to ERROR_ACTIVE
+ *	ip link set canX up type can bitrate 125000
+ */
+static void omapl_pru_can_start(struct net_device *ndev)
+{
+	struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+	u16 int_mask = 0xFFFF;

drivers/net/can/da8xx_pruss/pruss_can.c new file +12 -0

+		priv->can.state = CAN_STATE_ERROR_PASSIVE;
+	else if (PRU_CAN_GSR_BIT_BFM & priv->can_tx_hndl.u32globalstatus)
+		priv->can.state = CAN_STATE_BUS_OFF;
+	else
+		priv->can.state = CAN_STATE_ERROR_ACTIVE;
+}
+
+static int omapl_pru_can_set_mode(struct net_device *ndev, enum can_mode mode)
+{
+	int ret = 0;
+
+	switch (mode) {

drivers/net/can/da8xx_pruss/pruss_can.c new file +17 -0

+	default:
+		ret = -EOPNOTSUPP;
+		break;
+	}
+	return ret;
+}
+
+static netdev_tx_t omapl_pru_can_start_xmit(struct sk_buff *skb,
+					    struct net_device *ndev)
+{
+	struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+	struct can_frame *cf = (struct can_frame *)skb->data;
+	int count;
+	u8 *data = cf->data;
+	u8 dlc = cf->can_dlc;
+	u8 *ptr8data = NULL;
+

drivers/net/can/da8xx_pruss/pruss_can.c new file +8 -0

+	if (cf->can_id & CAN_RTR_FLAG)	/* Remote transmission request */
+		*((u32 *) &priv->can_tx_hndl.strcanmailbox) |= CAN_RTR_FLAG;
+
+	ptr8data = &priv->can_tx_hndl.strcanmailbox.u8data7 + (dlc - 1);
+	for (count = 0; count < (u8) dlc; count++) {
+		*ptr8data-- = *data++;
+	}
+	*((u32 *) &priv->can_tx_hndl.strcanmailbox.u16datalength) = (u32) dlc;

drivers/net/can/da8xx_pruss/pruss_can.c new file +168 -0

+	}
+
+	return IRQ_HANDLED;
+}
+
+static int omapl_pru_can_open(struct net_device *ndev)
+{
+	struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+	int err;
+
+	/* register interrupt handler */
+	err = request_irq(priv->trx_irq, &omapl_rx_can_intr, IRQF_SHARED,
+			  "pru_can_irq", ndev);
+	if (err) {
+		dev_err(priv->dev, "error requesting rx interrupt\n");
+		goto exit_trx_irq;
+	}
+	/* common open */
+	err = open_candev(ndev);
+	if (err) {
+		dev_err(priv->dev, "open_candev() failed %d\n", err);
+		goto exit_open;
+	}
+
+	pru_can_emu_init(priv->dev, priv->can.clock.freq);
+	priv->tx_tail = MB_MIN;
+	priv->tx_head = MB_MAX;
+
+	pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX0, 0);
+	pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX1, 1);
+	pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX2, 2);
+	pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX3, 3);
+	pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX4, 4);
+	pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX5, 5);
+	pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX6, 6);
+	pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX7, 7);
+
+	omapl_pru_can_start(ndev);
+	netif_start_queue(ndev);
+	return 0;
+
+exit_open:
+	free_irq(priv->trx_irq, ndev);
+exit_trx_irq:
+	return err;
+}
+
+static int omapl_pru_can_close(struct net_device *ndev)
+{
+	struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+
+	if (!netif_queue_stopped(ndev))
+		netif_stop_queue(ndev);
+
+	close_candev(ndev);
+
+	free_irq(priv->trx_irq, ndev);
+	return 0;
+}
+
+static const struct net_device_ops omapl_pru_can_netdev_ops = {
+	.ndo_open		= omapl_pru_can_open,
+	.ndo_stop		= omapl_pru_can_close,
+	.ndo_start_xmit		= omapl_pru_can_start_xmit,
+};
+
+static int __devinit omapl_pru_can_probe(struct platform_device *pdev)
+{
+	struct net_device *ndev = NULL;
+	const struct da8xx_pru_can_data *pdata;
+	struct omapl_pru_can_priv *priv = NULL;
+	struct device *dev = &pdev->dev;
+	u32 err;
+
+	pdata = dev->platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "platform data not found\n");
+		return -EINVAL;
+	}
+
+	ndev = alloc_candev(sizeof(struct omapl_pru_can_priv), MB_MAX + 1);
+	if (!ndev) {
+		dev_err(&pdev->dev, "alloc_candev failed\n");
+		err = -ENOMEM;
+		goto probe_exit;
+	}
+	priv = netdev_priv(ndev);
+
+	priv->trx_irq = platform_get_irq(to_platform_device(dev->parent), 0);
+	if (!priv->trx_irq) {
+		dev_err(&pdev->dev, "unable to get pru interrupt resources!\n");
+		err = -ENODEV;
+		goto probe_exit;
+	}
+
+	priv->ndev = ndev;
+	priv->dev = dev; /* priv->dev = pdev->dev */
+
+	priv->can.bittiming_const = NULL;
+	priv->can.do_set_bittiming = omapl_pru_can_set_bittiming;
+	priv->can.do_set_mode = omapl_pru_can_set_mode;
+	priv->can.do_get_state = omapl_pru_can_get_state;
+	priv->can_tx_hndl.u8prunumber = CAN_TX_PRU_1;
+	priv->can_rx_hndl.u8prunumber = CAN_RX_PRU_0;
+
+	/* we support local echo, no arp */
+	ndev->flags |= (IFF_ECHO | IFF_NOARP);
+
+	/* pdev->dev->device_private->driver_data = ndev */
+	platform_set_drvdata(pdev, ndev);
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+	ndev->netdev_ops = &omapl_pru_can_netdev_ops;
+
+	priv->can.clock.freq = pruss_get_clk_freq(priv->dev);
+
+	priv->clk_timer = clk_get(&pdev->dev, "pll1_sysclk2");
+	if (IS_ERR(priv->clk_timer)) {
+		dev_err(&pdev->dev, "no timer clock available\n");
+		err = PTR_ERR(priv->clk_timer);
+		priv->clk_timer = NULL;
+		goto probe_exit_candev;
+	}
+	priv->timer_freq = clk_get_rate(priv->clk_timer);
+
+	err = register_candev(ndev);
+	if (err) {
+		dev_err(&pdev->dev, "register_candev() failed\n");
+		err = -ENODEV;
+		goto probe_exit_clk;
+	}
+
+	err = request_firmware(&priv->fw_tx, "PRU_CAN_Emulation_Tx.bin",
+			&pdev->dev);
+	if (err) {
+		dev_err(&pdev->dev, "can't load firmware\n");
+		err = -ENODEV;
+		goto probe_exit_clk;
+	}
+
+	dev_info(&pdev->dev, "fw_tx size %d. downloading...\n",
+		 priv->fw_tx->size);
+
+	err = request_firmware(&priv->fw_rx, "PRU_CAN_Emulation_Rx.bin",
+			&pdev->dev);
+	if (err) {
+		dev_err(&pdev->dev, "can't load firmware\n");
+		err = -ENODEV;
+		goto probe_release_fw;
+	}
+	dev_info(&pdev->dev, "fw_rx size %d. downloading...\n",
+		 priv->fw_rx->size);
+
+	/* init the pru */
+	pru_can_emu_init(priv->dev, priv->can.clock.freq);
+	udelay(200);
+
+	pruss_enable(priv->dev, CAN_RX_PRU_0);
+	pruss_enable(priv->dev, CAN_TX_PRU_1);
+
+	/* download firmware into pru */
+	err = pruss_load(priv->dev, CAN_RX_PRU_0,
+		(u32 *)priv->fw_rx->data, (priv->fw_rx->size / 4));
+	if (err) {
+		dev_err(&pdev->dev, "firmware download error\n");
+		err = -ENODEV;
+		goto probe_release_fw_1;
+	}
+	err = pruss_load(priv->dev, CAN_TX_PRU_1,

drivers/net/can/da8xx_pruss/pruss_can.c new file +99 -0

+
+	pruss_run(priv->dev, CAN_RX_PRU_0);
+	pruss_run(priv->dev, CAN_TX_PRU_1);
+
+	/*Create The Work Queue */
+	priv->pru_can_wQ = create_freezeable_workqueue("omapl_pru_wQ");
+	if (priv->pru_can_wQ == NULL) {
+		dev_err(&pdev->dev, "failed to create work queue\n");
+		err = -ENODEV;
+		goto probe_release_fw_1;
+	}
+
+	INIT_WORK(&priv->rx_work, omapl_pru_can_rx_wQ);
+	dev_info(&pdev->dev,
+		 "%s device registered (trx_irq = %d,  clk = %d)\n",
+		 DRV_NAME, priv->trx_irq, priv->can.clock.freq);
+
+	return 0;
+
+probe_release_fw_1:
+	release_firmware(priv->fw_rx);
+probe_release_fw:
+	release_firmware(priv->fw_tx);
+probe_exit_clk:
+	clk_put(priv->clk_timer);
+probe_exit_candev:
+	if (NULL != ndev)
+		free_candev(ndev);
+probe_exit:
+	return err;
+}
+
+static int __devexit omapl_pru_can_remove(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+
+	omapl_pru_can_stop(ndev);
+
+	pru_can_emu_exit(priv->dev);
+	release_firmware(priv->fw_tx);
+	release_firmware(priv->fw_rx);
+	clk_put(priv->clk_timer);
+	flush_workqueue(priv->pru_can_wQ);
+	destroy_workqueue(priv->pru_can_wQ);
+	unregister_candev(ndev);
+	free_candev(ndev);
+	platform_set_drvdata(pdev, NULL);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int omapl_pru_can_suspend(struct platform_device *pdev,
+			pm_message_t mesg)
+{
+	dev_info(&pdev->dev, "%s not yet implemented\n", __func__);
+	return 0;
+}
+
+static int omapl_pru_can_resume(struct platform_device *pdev)
+{
+	dev_info(&pdev->dev, "%s not yet implemented\n", __func__);
+	return 0;
+}
+#else
+#define omapl_pru_can_suspend NULL
+#define omapl_pru_can_resume NULL
+#endif /* CONFIG_PM */
+
+static struct platform_driver omapl_pru_can_driver = {
+	.probe		= omapl_pru_can_probe,
+	.remove		= __devexit_p(omapl_pru_can_remove),
+	.suspend	= omapl_pru_can_suspend,
+	.resume		= omapl_pru_can_resume,
+	.driver		= {
+		.name	= DRV_NAME,
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init omapl_pru_can_init(void)
+{
+	__can_debug(KERN_INFO DRV_DESC "\n");
+	return platform_driver_register(&omapl_pru_can_driver);
+}
+
+module_init(omapl_pru_can_init);
+
+static void __exit omapl_pru_can_exit(void)
+{
+	__can_debug(KERN_INFO DRV_DESC " unloaded\n");
+	platform_driver_unregister(&omapl_pru_can_driver);
+}
+
+module_exit(omapl_pru_can_exit);
+
+MODULE_AUTHOR("Subhasish Ghosh <subhasish-EvXpCiN+lbve9wHmmfpqLFaTQe2KTcn/@public.gmane.org>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("omapl pru CAN netdevice driver");

drivers/net/can/da8xx_pruss/pruss_can_api.c new file +118 -0

new file mode 100644
index 0000000..2f7438a
@@ -0,0 +1,1227 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Author: Wilfred Felix
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as  published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include "pruss_can_api.h"
+
+static can_emu_drv_inst gstr_can_inst[ecanmaxinst];
+
+/*
+ * pru_can_set_brp()	Updates the  BRP register of PRU0
+ * and PRU1 of OMAP L138. This API will be called by the
+ * Application to updtae the BRP register of PRU0 and PRU1
+ *
+ * param	u16bitrateprescaler		The can bus bitrate
+ * prescaler value be set
+ *
+ * return   SUCCESS or FAILURE
+ */
+s16 pru_can_set_brp(struct device *dev, u16 u16bitrateprescaler)
+{
+
+	u32 u32offset;
+
+	if (u16bitrateprescaler > 255) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_CLOCK_BRP_REGISTER);
+	pruss_writel(dev, u32offset, (u32 *) &u16bitrateprescaler, 1);
+
+	u32offset = (PRU_CAN_TX_CLOCK_BRP_REGISTER);
+	pruss_writel(dev, u32offset, (u32 *) &u16bitrateprescaler, 1);
+
+	return 0;
+
+}
+
+/*
+ * pru_can_set_bit_timing()		Updates the timing register
+ * of PRU0 and PRU1 of OMAP L138. This API will be called by
+ * the Application to updtae the timing register of PRU0 and PRU1
+ *
+ * param	pstrbittiming		Pointer to structure holding
+ * the bit timing values for can bus.
+ *
+ * return   SUCCESS or FAILURE
+ */
+s16 pru_can_set_bit_timing(struct device *dev,
+		can_bit_timing_consts *pstrbittiming)
+{
+
+	u32 u32offset;
+	u32 u32serregister;
+
+	u32serregister = 0;
+
+	if (pstrbittiming == NULL) {
+		return -1;
+	}
+
+	if ((pstrbittiming->u8syncjumpwidth > PRU_CAN_MAX_SJW) ||
+	    (pstrbittiming->u8phseg1 > PRU_CAN_MAX_PHSEG1) ||
+	    (pstrbittiming->u8phseg2 > PRU_CAN_MAX_PHSEG2)) {
+		return -1;
+	}
+
+	u32serregister = u32serregister |
+			((pstrbittiming->u8syncjumpwidth << 7) |
+			(pstrbittiming->u8phseg1 << 3) |
+			(pstrbittiming->u8phseg2));
+
+	u32offset = (PRU_CAN_TX_TIMING_REGISTER);
+	pruss_writel(dev, u32offset, (u32 *) &u32serregister, 1);
+
+	u32offset = (PRU_CAN_RX_TIMING_REGISTER);
+	pruss_writel(dev, u32offset, (u32 *) &u32serregister, 1);
+
+	return 0;
+}
+
+
+/*
+ * pru_can_calc_timing()
+ * Updates the  timing values of PRU0 and PRU1 of OMAP L138.
+ * This API will be called by the
+ * Application to updtae the timing values of PRU0 and PRU1
+ *
+ * return   SUCCESS or FAILURE
+ */
+
+s16 pru_can_calc_timing(struct device *dev, u32 pru_freq, u32 bit_rate)
+{
+	u16 u16phaseseg1;
+	u16 u16phaseseg2;
+	u32 u32offset;
+	u32 u32timing_value;
+	u32 u32setup_value;
+	u32timing_value = TIMER_CLK_FREQ / bit_rate;
+	u32offset = (PRU_CAN_TIMING_VAL_TX);
+	pruss_writel(dev, u32offset, (u32 *) &u32timing_value, 4);
+	pruss_readl(dev, u32offset, (u32 *) &u32timing_value, 4);
+	u32setup_value =
+	    (GPIO_SETUP_DELAY * (pru_freq / 1000000) / 1000) /
+	    DELAY_LOOP_LENGTH;
+	u32offset = (PRU_CAN_TIMING_VAL_TX_SJW);
+	pruss_writel(dev, u32offset, (u32 *) &u32setup_value, 4);
+	u16phaseseg1 = (u16) (u32timing_value / 2);
+	u16phaseseg2 = u32timing_value - u16phaseseg1;

drivers/net/can/da8xx_pruss/pruss_can_api.c new file +40 -0

+/*
+ * pru_can_write_data_to_mailbox()
+ * Updates the transmit mailboxes of PRU1 of OMAP L138.
+ * This API will be called by the Application to update
+ * the transmit mailboxes of PRU1
+ *
+ * param  pu16canframedata	Can mailbox data buffer
+ *
+ * param  u8mailboxnum		Mailbox to be updated
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_write_data_to_mailbox(struct device *dev,
+			can_emu_app_hndl *pstremuapphndl)
+{
+	s16 s16subrtnretval;
+	u32 u32offset;
+
+	if (pstremuapphndl == NULL) {
+		return -1;
+	}
+
+	switch ((u8) pstremuapphndl->ecanmailboxnumber) {
+	case 0:
+		u32offset = (PRU_CAN_TX_MAILBOX0);
+		break;
+	case 1:
+		u32offset = (PRU_CAN_TX_MAILBOX1);
+		break;
+	case 2:
+		u32offset = (PRU_CAN_TX_MAILBOX2);
+		break;
+	case 3:
+		u32offset = (PRU_CAN_TX_MAILBOX3);
+		break;
+	case 4:
+		u32offset = (PRU_CAN_TX_MAILBOX4);
+		break;
+	case 5:
+		u32offset = (PRU_CAN_TX_MAILBOX5);

drivers/net/can/da8xx_pruss/pruss_can_api.c new file +51 -0

+	s16subrtnretval = pruss_writel(dev, u32offset,
+		(u32 *) &(pstremuapphndl->strcanmailbox), 4);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+	return 0;
+}
+
+/*
+ * pru_can_get_data_from_mailbox()
+ * Receive data from the receive mailboxes of PRU0  of OMAP L138.
+ * This API will be called by the Application to get data from
+ * the receive mailboxes of PRU0
+ *
+ * param  pu16canframedata	Can mailbox data buffer
+ *
+ * param  u8mailboxnum		Mailbox to be updated
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_get_data_from_mailbox(struct device *dev,
+		can_emu_app_hndl *pstremuapphndl)
+{
+	s16 s16subrtnretval;
+	u32 u32offset;
+
+	if (pstremuapphndl == NULL) {
+		return -1;
+	}
+
+	switch ((u8) pstremuapphndl->ecanmailboxnumber) {
+	case 0:
+		u32offset = (PRU_CAN_RX_MAILBOX0);
+		break;
+	case 1:
+		u32offset = (PRU_CAN_RX_MAILBOX1);
+		break;
+	case 2:
+		u32offset = (PRU_CAN_RX_MAILBOX2);
+		break;
+	case 3:
+		u32offset = (PRU_CAN_RX_MAILBOX3);
+		break;
+	case 4:
+		u32offset = (PRU_CAN_RX_MAILBOX4);
+		break;
+	case 5:
+		u32offset = (PRU_CAN_RX_MAILBOX5);
+		break;
+	case 6:
+		u32offset = (PRU_CAN_RX_MAILBOX6);

drivers/net/can/da8xx_pruss/pruss_can_api.c new file +645 -0

+	s16subrtnretval =
+	    pruss_readl(dev, u32offset,
+		  (u32 *) &(pstremuapphndl->strcanmailbox),
+				  4);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+	return 0;
+}
+
+/*
+ * pru_can_receive_id_map()
+ * Receive mailboxes ID Mapping of PRU0  of OMAP L138.
+ * This API will be called by the Application
+ * to map the IDs  to receive mailboxes of PRU0
+ *
+ * param  u32nodeid		Can node ID
+ *
+ * param  ecanmailboxno		Mailbox to be mapped
+ *
+ * return   SUCCESS or FAILURE
+ */
+s16 pru_can_rx_id_map(struct device *dev, u32 u32nodeid,
+		can_mailbox_number ecanmailboxno)
+{
+
+	pruss_writel(dev, (PRU_CAN_ID_MAP +
+		(((u8) ecanmailboxno) * 4)), (u32 *) &u32nodeid, 1);
+
+	return 0;
+}
+
+/*
+ * pru_can_get_intr_status()
+ * Gets the interrupts status register value.
+ * This API will be called by the Application
+ * to get the interrupts status register value
+ *
+ * param  u8prunumber	PRU number for which IntStatusReg
+ * has to be read
+ *
+ * return   SUCCESS or FAILURE
+ */
+s16 pru_can_get_intr_status(struct device *dev,
+		can_emu_app_hndl *pstremuapphndl)
+{
+	u32 u32offset;
+	s16 s16subrtnretval = -1;
+
+	if (pstremuapphndl == NULL) {
+		return -1;
+	}
+
+	if (pstremuapphndl->u8prunumber == DA8XX_PRUCORE_1) {
+		u32offset = (PRU_CAN_TX_INTERRUPT_STATUS_REGISTER);
+	} else if (pstremuapphndl->u8prunumber == DA8XX_PRUCORE_0) {
+		u32offset = (PRU_CAN_RX_INTERRUPT_STATUS_REGISTER);
+	} else {
+		return -1;
+	}
+
+	s16subrtnretval = pruss_readl(dev, u32offset,
+		(u32 *) &pstremuapphndl->u32interruptstatus, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * pru_can_get_global_status()	Gets the globalstatus
+ * register value. This API will be called by the Application
+ * to  get the global status register value
+ *
+ * return   SUCCESS or FAILURE
+ */
+s16 pru_can_get_global_status(struct device *dev,
+		can_emu_app_hndl *pstremuapphndl)
+{
+	u32 u32offset;
+	int s16subrtnretval = -1;
+
+	if (pstremuapphndl == NULL) {
+		return -1;
+	}
+
+	if (pstremuapphndl->u8prunumber == DA8XX_PRUCORE_1) {
+		u32offset = (PRU_CAN_TX_GLOBAL_STATUS_REGISTER);
+	} else if (pstremuapphndl->u8prunumber == DA8XX_PRUCORE_0) {
+		u32offset = (PRU_CAN_RX_GLOBAL_STATUS_REGISTER);
+	} else {
+		return -1;
+	}
+
+	s16subrtnretval = pruss_readl(dev, u32offset,
+		(u32 *) &pstremuapphndl->u32globalstatus, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * pru_can_get_mailbox_status()		Gets the mailbox status
+ * register value. This API will be called by the Application
+ * to get the mailbox status register value
+ *
+ * return   SUCCESS or FAILURE
+ */
+s16 pru_can_get_mailbox_status(struct device *dev,
+		can_emu_app_hndl *pstremuapphndl)
+{
+	u32 u32offset;
+	s16 s16subrtnretval = -1;
+
+	if (pstremuapphndl == NULL) {
+		return -1;
+	}
+
+	if (pstremuapphndl->u8prunumber == DA8XX_PRUCORE_1) {
+		switch (pstremuapphndl->ecanmailboxnumber) {
+		case 0:
+			u32offset = (PRU_CAN_TX_MAILBOX0_STATUS_REGISTER);
+			break;
+		case 1:
+			u32offset = (PRU_CAN_TX_MAILBOX1_STATUS_REGISTER);
+			break;
+		case 2:
+			u32offset = (PRU_CAN_TX_MAILBOX2_STATUS_REGISTER);
+			break;
+		case 3:
+			u32offset = (PRU_CAN_TX_MAILBOX3_STATUS_REGISTER);
+			break;
+		case 4:
+			u32offset = (PRU_CAN_TX_MAILBOX4_STATUS_REGISTER);
+			break;
+		case 5:
+			u32offset = (PRU_CAN_TX_MAILBOX5_STATUS_REGISTER);
+			break;
+		case 6:
+			u32offset = (PRU_CAN_TX_MAILBOX6_STATUS_REGISTER);
+			break;
+		case 7:
+			u32offset = (PRU_CAN_TX_MAILBOX7_STATUS_REGISTER);
+			break;
+		default:
+			return -1;
+		}
+	}
+
+	else if (pstremuapphndl->u8prunumber == DA8XX_PRUCORE_0) {
+		switch (pstremuapphndl->ecanmailboxnumber) {
+		case 0:
+			u32offset = (PRU_CAN_RX_MAILBOX0_STATUS_REGISTER);
+			break;
+		case 1:
+			u32offset = (PRU_CAN_RX_MAILBOX1_STATUS_REGISTER);
+			break;
+		case 2:
+			u32offset = (PRU_CAN_RX_MAILBOX2_STATUS_REGISTER);
+			break;
+		case 3:
+			u32offset = (PRU_CAN_RX_MAILBOX3_STATUS_REGISTER);
+			break;
+		case 4:
+			u32offset = (PRU_CAN_RX_MAILBOX4_STATUS_REGISTER);
+			break;
+		case 5:
+			u32offset = (PRU_CAN_RX_MAILBOX5_STATUS_REGISTER);
+			break;
+		case 6:
+			u32offset = (PRU_CAN_RX_MAILBOX6_STATUS_REGISTER);
+			break;
+		case 7:
+			u32offset = (PRU_CAN_RX_MAILBOX7_STATUS_REGISTER);
+			break;
+		case 8:
+			u32offset = (PRU_CAN_RX_MAILBOX8_STATUS_REGISTER);
+			break;
+		default:
+			return -1;
+		}
+	}
+
+	else {
+		return -1;
+	}
+
+	s16subrtnretval = pruss_readl(dev, u32offset,
+		(u32 *) &pstremuapphndl->u32mailboxstatus, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	return 0;
+}
+
+s16 pru_can_tx_mode_set(struct device *dev, bool btransfer_flag,
+				can_transfer_direction ecan_trx)
+{
+	u32 u32offset;
+	u32 u32value;
+
+	if (ecan_trx == ecantransmit) {
+		u32offset = (PRU_CAN_RX_GLOBAL_STATUS_REGISTER);
+		pruss_readl(dev, u32offset, &u32value, 1);
+		if (btransfer_flag == true) {
+			u32value &= 0x1F;
+			u32value |= 0x80;
+		} else {
+			u32value &= 0x7F;
+		}
+		pruss_writel(dev, u32offset, &u32value, 1);
+		u32offset = (PRU_CAN_TX_GLOBAL_STATUS_REGISTER);
+		pruss_writel(dev, u32offset, &u32value, 1);
+	} else if (ecan_trx == ecanreceive) {
+		u32offset = (PRU_CAN_RX_GLOBAL_STATUS_REGISTER);
+		pruss_readl(dev, u32offset, &u32value, 1);
+		if (btransfer_flag == true) {
+			u32value &= 0x1F;
+			u32value |= 0x40;
+		} else {
+			u32value &= 0xBF;
+		}
+		pruss_writel(dev, u32offset, &u32value, 1);
+		u32offset = (PRU_CAN_TX_GLOBAL_STATUS_REGISTER);
+		pruss_writel(dev, u32offset, &u32value, 1);
+	} else
+		return -1;
+
+	return 0;
+}
+
+/*
+ * pru_can_config_mode_set()		Sets the timing value
+ * for data transfer. This API will be called by the Application
+ * to set timing valus for data transfer
+ *
+ * return   SUCCESS or FAILURE
+ */
+s16 pru_can_config_mode_set(struct device *dev, bool bconfigmodeflag)
+{
+
+	u32 u32bitrateprescaler;
+	u32 u32canbittiming;
+
+	pruss_readl(dev, (PRU_CAN_TX_CLOCK_BRP_REGISTER),
+			(u32 *) &u32bitrateprescaler, 1);
+	pruss_readl(dev, (PRU_CAN_TX_TIMING_REGISTER),
+			(u32 *) &u32canbittiming, 1);
+
+	if (bconfigmodeflag == 1) {
+		pru_can_calc_timing(dev, u32canbittiming, u32bitrateprescaler);
+	}
+
+	else {
+		pru_can_calc_timing(dev, 0, 0);
+	}
+
+	return 0;
+}
+
+/*
+ * pru_can_emu_init()		Initializes the Can
+ * Emulation Parameters. This API will be called by the Application
+ * to Initialize the Can Emulation Parameters
+ *
+ * param    u32pruclock         PRU Clock value
+ *
+ * return   SUCCESS or FAILURE
+ */
+s16 pru_can_emu_init(struct device *dev, u32 u32pruclock)
+{
+	u32 u32offset;
+	u32 u32value;
+	s16 s16subrtnretval = -1;
+	u8 u8loop;
+
+	for (u8loop = 0; u8loop < (u8) ecanmaxinst; u8loop++) {
+		gstr_can_inst[u8loop].bcaninststate = (bool) 0;
+		gstr_can_inst[u8loop].ecantransferdirection =
+		    (can_transfer_direction) 0;
+		gstr_can_inst[u8loop].u32apphandlerptr = 0;
+	}
+
+	u32offset = (PRU_CAN_TX_GLOBAL_CONTROL_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_GLOBAL_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000040;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+	u32offset = (PRU_CAN_RX_GLOBAL_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000040;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_INTERRUPT_MASK_REGISTER & 0xFFFF);
+	u32value = 0x00004000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_INTERRUPT_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_MAILBOX0_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000001;
+	s16subrtnretval =
+	    pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_MAILBOX1_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000001;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_MAILBOX2_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000001;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_MAILBOX3_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000001;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_MAILBOX4_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000001;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_MAILBOX5_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000001;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_MAILBOX6_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000001;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_MAILBOX7_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000001;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_ERROR_COUNTER_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_TIMING_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_CLOCK_BRP_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_TX_ERROR_COUNTER_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_POLARITY0 & 0xFFFF);
+	u32value = 0xFFFFFFFF;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+	u32offset = (PRUSS_INTC_POLARITY1 & 0xFFFF);
+	u32value = 0xFFFFFFFF;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+	u32offset = (PRUSS_INTC_TYPE0 & 0xFFFF);
+	u32value = 0x1C000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+	u32offset = (PRUSS_INTC_TYPE1 & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_HSTINTENIDXCLR & 0xFFFF);
+	u32value = 0x0;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_GLBLEN & 0xFFFF);
+	u32value = 0x1;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+	/* tx intr map arm->pru */
+	u32offset = (PRUSS_INTC_HSTINTENIDXSET & 0xFFFF);
+	u32value = 0x0;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_HOSTMAP0 & 0xFFFF);
+	u32value = 0x03020100;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_HOSTMAP1 & 0xFFFF);
+	u32value = 0x07060504;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_HOSTMAP2 & 0xFFFF);
+	u32value = 0x0000908;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_CHANMAP0 & 0xFFFF);
+	u32value = 0;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_CHANMAP8 & 0xFFFF);
+	u32value = 0x00020200;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_STATIDXCLR & 0xFFFF);
+	u32value = 32;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_STATIDXCLR & 0xFFFF);
+	u32value = 19;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_ENIDXSET & 0xFFFF);
+	u32value = 19;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+	u32offset = (PRUSS_INTC_STATIDXCLR & 0xFFFF);
+	u32value = 18;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_ENIDXSET & 0xFFFF);
+	u32value = 18;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_STATIDXCLR & 0xFFFF);
+	u32value = 34;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_ENIDXSET & 0xFFFF);
+	u32value = 34;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_ENIDXSET & 0xFFFF);
+	u32value = 32;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRUSS_INTC_HOSTINTEN & 0xFFFF);
+	u32value = 0x5;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+/* PRU0 - Rx Internal Registers Initializations */
+
+	u32offset = (PRU_CAN_RX_GLOBAL_CONTROL_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_GLOBAL_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000040;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_INTERRUPT_MASK_REGISTER & 0xFFFF);
+	u32value = 0x00004000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_INTERRUPT_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_MAILBOX0_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_MAILBOX1_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x0000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_MAILBOX2_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_MAILBOX3_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_MAILBOX4_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_MAILBOX5_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_MAILBOX6_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_MAILBOX7_STATUS_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_ERROR_COUNTER_REGISTER & 0xFFFF);
+	u32value = 0x00000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+	if (s16subrtnretval == -1) {
+		return -1;
+	}
+
+	u32offset = (PRU_CAN_RX_TIMING_REGISTER & 0xFFFF);
+	u32value = 0x0000000;
+	s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);