oprofile: Allow setting EDGE/INV/CMASK for Intel counter events
PATCH 1/1 oprofile: Allow setting EDGE/INV/CMASK for Intel counter events
From: Andi Kleen <[email protected]>
For some performance events it's useful to set the EDGE and INV bits and the CMASK mask in the counter control register. The list of predefined events Intel releases for each CPU has some events which require these settings to get more "natural" to use higher level events.
oprofile currently doesn't allow this.
This patch adds new extra configuration fields for them, so that they can be specified in oprofilefs.
An updated oprofile daemon can then make use of this to set them.
--- arch/x86/oprofile/nmi_int.c | 4 ++++ arch/x86/oprofile/op_counter.h | 1 + 2 files changed, 5 insertions(+), 0 deletions(-)
arch/x86/oprofile/nmi_int.c +4 -0
@@ -49,6 +49,9 @@ u64 op_x86_get_ctrl(struct op_x86_model_spec const *model, val |= counter_config->user ?ARCH_PERFMON_EVENTSEL_USR :0 ; val |= counter_config->kernel ?ARCH_PERFMON_EVENTSEL_OS :0 ; val |= (counter_config->unit_mask &0xFF ) <<8 ; + val |= counter_config->extra & (ARCH_PERFMON_EVENTSEL_INV | +ARCH_PERFMON_EVENTSEL_EDGE | +ARCH_PERFMON_EVENTSEL_CMASK ); event &= model->event_mask ? model->event_mask :0xFF ; val |= event &0xFF ; val |= (event &0x0F00 ) <<24 ;
@@ -440,6 +443,7 @@ static int nmi_create_files(struct super_block *sb, struct dentry *root)oprofilefs_create_ulong (sb, dir,"unit_mask" , &counter_config[i].unit_mask);oprofilefs_create_ulong (sb, dir,"kernel" , &counter_config[i].kernel);oprofilefs_create_ulong (sb, dir,"user" , &counter_config[i].user); +oprofilefs_create_ulong (sb, dir,"extra" , &counter_config[i].extra); }return 0 ;
arch/x86/oprofile/op_counter.h +1 -0
@@ -22,6 +22,7 @@ struct op_counter_config {unsigned long kernel;unsigned long user;unsigned long unit_mask; +unsigned long extra; };extern struct op_counter_config counter_config[];
Signature · 1 line
1.7.4
Quoted 25 lines · Andi Kleen
From: Andi Kleen <[email protected]>
For some performance events it's useful to set the EDGE and INV bits and the CMASK mask in the counter control register. The list of predefined events Intel releases for each CPU has some events which require these settings to get more "natural" to use higher level events.
oprofile currently doesn't allow this.
This patch adds new extra configuration fields for them, so that they can be specified in oprofilefs.
An updated oprofile daemon can then make use of this to set them.
Signed-off-by Andi Kleen <[email protected]>--- arch/x86/oprofile/nmi_int.c | 4 ++++ arch/x86/oprofile/op_counter.h | 1 + 2 files changed, 5 insertions(+), 0 deletions(-)arch/x86/oprofile/nmi_int.c +0
-0
arch/x86/oprofile/nmi_int.c u64 op_x86_get_ctrl(struct op_x86_model_spec const *model, · line 54
Quoted 6 lines
arch/x86/oprofile/nmi_int.c +3
-0@@ -49,6 +49,9 @@ u64 op_x86_get_ctrl(struct op_x86_model_spec const *model, val |= counter_config->user ?ARCH_PERFMON_EVENTSEL_USR :0 ; val |= counter_config->kernel ?ARCH_PERFMON_EVENTSEL_OS :0 ; val |= (counter_config->unit_mask &0xFF ) <<8 ; + val |= counter_config->extra & (ARCH_PERFMON_EVENTSEL_INV | +ARCH_PERFMON_EVENTSEL_EDGE | +ARCH_PERFMON_EVENTSEL_CMASK );
I would like to write the actual value back so that userland may read it:
counter_config->extra &= (ARCH_PERFMON_EVENTSEL_INV|
ARCH_PERFMON_EVENTSEL_EDGE|
ARCH_PERFMON_EVENTSEL_CMASK);
val |= counter_config->extra;The value will not be updated emmediately but at least after profiling was started.
As an alternative, maybe we better put this extra bits in the unit_mask, e.g. in bits [31:16] of the unit mask for bits [31:16] of PerfEvtSel? Then, we simply could use the current userland to set it up.
-Robert
Signature · 2 lines
Advanced Micro Devices, Inc. Operating System Research Center
Quoted 10 lines
I would like to write the actual value back so that userland may read it:
counter_config->extra &= (ARCH_PERFMON_EVENTSEL_INV| ARCH_PERFMON_EVENTSEL_EDGE| ARCH_PERFMON_EVENTSEL_CMASK); val |= counter_config->extra;The value will not be updated emmediately but at least after profiling was started.
Okay.
Quoted 5 lines
As an alternative, maybe we better put this extra bits in the
unit_mask, e.g. in bits [31:16] of the unit mask for bits [31:16] of PerfEvtSel? Then, we simply could use the current userland to set it up.
We can't anyways, it doesn't support it.
-Andi
Signature · 1 line
[email protected] -- Speaking for myself only
Quoted 14 lines · Andi Kleen
Quoted 10 lines
I would like to write the actual value back so that userland may read it:
counter_config->extra &= (ARCH_PERFMON_EVENTSEL_INV| ARCH_PERFMON_EVENTSEL_EDGE| ARCH_PERFMON_EVENTSEL_CMASK); val |= counter_config->extra;The value will not be updated emmediately but at least after profiling was started.
Okay.
Quoted 1 line
Quoted 6 lines
Quoted 4 lines
As an alternative, maybe we better put this extra bits in the
unit_mask, e.g. in bits [31:16] of the unit mask for bits [31:16] of PerfEvtSel? Then, we simply could use the current userland to set it up.We can't anyways, it doesn't support it.
Shouldn't something like the follwing work (assuming the umask table is modified)?
opcontrol --event SOME_EVENT:100000:0x00800000 ...
(setting the INV flag)
-Robert
Signature · 2 lines
Advanced Micro Devices, Inc. Operating System Research Center
Quoted 4 lines
Shouldn't something like the follwing work (assuming the umask table is modified)?
opcontrol --event SOME_EVENT:100000:0x00800000 ...
I think there was some problem with this when I tried it.
Besides I'm more interested in using named events for this; the raw numbers are quite evil. So this needs new user space in any case.
-Andi
Quoted 10 lines · Andi Kleen
Quoted 4 lines
Shouldn't something like the follwing work (assuming the umask table is modified)?
opcontrol --event SOME_EVENT:100000:0x00800000 ...
I think there was some problem with this when I tried it.
Besides I'm more interested in using named events for this; the raw numbers are quite evil. So this needs new user space in any case.
Ok, in this case we can use also /extra. So I am fine with this too.
Thanks,
-Robert
Signature · 2 lines
Advanced Micro Devices, Inc. Operating System Research Center