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powerpc/mpc512x: Add initial support for TWR-MPC5125

PATCH In review Vladimir Ermakov 2 participants 6 messages Mar 16, 2011 – Mar 22, 2011

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Device tree bindings PowerPC Linux for PowerPC embedded MPC5XXX
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Vladimir Ermakov

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PATCH 1/4 powerpc/mpc512x: Add initial support for TWR-MPC5125

Adds Freescale TWR-MPC5125 device tree and platform code.

Currently following is supported:
- NAND
- FEC1 and FEC2
- RTC
- PSC UART

Signed-off-by Vladimir Ermakov <[email protected]>

---

arch/powerpc/boot/dts/mpc5125twr.dts new file +394 -0
new file mode 100644
index 0000000..54f568f
@@ -0,0 +1,394 @@
+/*
+ * STx/Freescale ADS5125 MPC5125 silicon
+ *
+ * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "mpc5125ads";
+	compatible = "fsl,mpc5125ads";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,5125@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <0x20>;	// 32 bytes
+			i-cache-line-size = <0x20>;	// 32 bytes
+			d-cache-size = <0x8000>;	// L1, 32K
+			i-cache-size = <0x8000>;	// L1, 32K
+			timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
+			bus-frequency = <198000000>;	// 198 MHz csb bus
+			clock-frequency = <396000000>;	// 396 MHz ppc core
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;	// 256MB at 0
+	};
+
+	sram@30000000 {
+		compatible = "fsl,mpc5121-sram";
+		reg = <0x30000000 0x08000>;		// 32K at 0x30000000
+	};
+
+	nfc@40000000 {
+		compatible = "fsl,mpc5125-nfc";
+		reg = <0x40000000 0x100000>;	// 1M at 0x40000000
+		interrupts = <6 0x8>;
+		interrupt-parent = < &ipic >;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <1>;
+		write-size = <4096>;
+		spare-size = <128>;
+		chips = <1>;
+		// NOTE: partition map different than in BSP
+		nand-spl@0 {
+			label = "loader";
+			reg = <0x00000000 0x00100000>;
+			read-only;
+		};
+		uboot@100000 {
+			label = "uboot";
+			reg = <0x00100000 0x00100000>;
+			read-only;
+		};
+		uboot-env@200000 {
+			label = "uboot-env";
+			reg = <0x00200000 0x00100000>;
+			read-only;
+		};
+		kernel300000 {
+			label = "kernel";
+			reg = <0x00300000 0x00800000>;
+		};
+		device-tree00000 {
+			label = "device-tree";
+			reg = <0x00b00000 0x00100000>;
+		};
+		ramboot-rootfs@c00000 {
+			label = "ramboot-rootfs";
+			reg = <0x00c00000 0x00800000>;
+		};
+		rootfs@1400000 {
+			label = "rootfs";
+			reg = <0x01400000 0x01400000>;
+		};
+		user@2800000 {
+			label = "user";
+			reg = <0x02800000 0x01400000>;
+		};
+		SRAM@4200000 {
+			label = "SRAM"; // NVRAM emul
+			reg = <0x04200000 0x01400000>;
+		};
+		prom@5600000 {
+			label = "prom";
+			reg = <0x05600000 0x01400000>;
+		};
+		//data@2800000 {
+		//	label = "data";
+		//	reg = <0x28000000 0xeac00000>;
+		//};
+	};
+
+	soc@80000000 {
+		compatible = "fsl,mpc5121-immr";
+		device_type = "soc";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		#interrupt-cells = <2>;
+		ranges = <0x0 0x80000000 0x400000>;
+		reg = <0x80000000 0x400000>;
+		bus-frequency = <66000000>;	// 66 MHz ips bus
+
+
+		// IPIC
+		// interrupts cell = <intr #, sense>
+		// sense values match linux IORESOURCE_IRQ_* defines:
+		// sense == 8: Level, low assertion
+		// sense == 2: Edge, high-to-low change
+		//
+		ipic: interrupt-controller@c00 {
+			compatible = "fsl,mpc5121-ipic", "fsl,ipic";
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			reg = <0xc00 0x100>;
+		};
+
+		rtc@a00 {	// Real time clock
+			compatible = "fsl,mpc5121-rtc";
+			reg = <0xa00 0x100>;
+			interrupts = <79 0x8 80 0x8>;
+			interrupt-parent = < &ipic >;
+		};
+
+		reset@e00 {	// Reset module
+			compatible = "fsl,mpc5121-reset";
+			reg = <0xe00 0x100>;
+		};
+
+		clock@f00 {	// Clock control
+			compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
+			reg = <0xf00 0x100>;
+		};
+
+		pmc@1000{  // Power Management Controller
+			compatible = "fsl,mpc5121-pmc";
+			reg = <0x1000 0x100>;
+			interrupts = <83 0x2>;
+			interrupt-parent = < &ipic >;
+		};
+
+		gpio@1100 {
+			compatible = "fsl,mpc5125-gpio";
+			cell-index = <0>;
+			reg = <0x1100 0x080>;
+			interrupts = <78 0x8>;
+			interrupt-parent = < &ipic >;
+		};
+
+		gpio@1180 {
+			compatible = "fsl,mpc5125-gpio1";
+			cell-index = <1>;
+			reg = <0x1180 0x080>;
+			interrupts = <78 0x8>;
+			interrupt-parent = < &ipic >;
+		};
+
+		can@1300 { // CAN rev.2
+			compatible = "fsl,mpc5121-mscan";
+			cell-index = <0>;
+			interrupts = <12 0x8>;
+			interrupt-parent = < &ipic >;
+			reg = <0x1300 0x80>;
+		};
+
+		can@1380 {
+			compatible = "fsl,mpc5121-mscan";
+			cell-index = <1>;
+			interrupts = <13 0x8>;
+			interrupt-parent = < &ipic >;
+			reg = <0x1380 0x80>;
+		};
+
+		sdhc@1500 {
+			compatible = "fsl,mpc5125-sdhc";
+			interrupts = <8 0x8>;
+			interrupt-parent = < &ipic >;
+			reg = <0x1500 0x100>;
+		};
+
+		i2c@1700 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl-i2c";
+			cell-index = <0>;
+			reg = <0x1700 0x20>;
+			interrupts = <0x9 0x8>;
+			interrupt-parent = < &ipic >;
+			fsl5200-clocking;
+		};
+
+		i2c@1720 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl-i2c";
+			cell-index = <1>;
+			reg = <0x1720 0x20>;
+			interrupts = <0xa 0x8>;
+			interrupt-parent = < &ipic >;
+			fsl5200-clocking;
+		};
+
+		i2c@1740 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl-i2c";
+			cell-index = <2>;
+			reg = <0x1740 0x20>;
+			interrupts = <0xb 0x8>;
+			interrupt-parent = < &ipic >;
+			fsl5200-clocking;
+		};
+
+		i2ccontrol@1760 {
+			compatible = "fsl,mpc5121-i2c-ctrl";
+			reg = <0x1760 0x8>;
+		};
+
+		//diu@2100 {
+		//	device_type = "display";
+		//	compatible = "fsl-diu";
+		//	reg = <0x2100 0x100>;
+		//	interrupts = <64 0x8>;
+		//	interrupt-parent = < &ipic >;
+		//};
+
+		// MPC5125e has two more CAN ports
+		// but they are not used on ADS5125
+		//can@2300 {
+		//	compatible = "fsl,mpc5121-mscan";
+		//	cell-index = <2>;
+		//	interrupts = <90 0x8>;
+		//	interrupt-parent = < &ipic >;
+		//	reg = <0x2300 0x80>;
+		//};
+
+		//can@2380 {
+		//	compatible = "fsl,mpc5121-mscan";
+		//	cell-index = <3>;
+		//	interrupts = <91 0x8>;
+		//	interrupt-parent = < &ipic >;
+		//	reg = <0x2380 0x80>;
+		//};
+
+		mdio@2800 {
+			device_type = "mdio";
+			compatible = "fsl,mpc5121-fec-mdio";
+			reg = <0x2800 0x800>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			phy0: ethernet-phy@0 {
+				reg = <1>;
+				device_type = "ethernet-phy";
+			};
+		};
+
+		ethernet@2800 {
+			device_type = "network";
+			compatible = "fsl,mpc5121-fec";
+			reg = <0x2800 0x800>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <4 0x8>;
+			interrupt-parent = < &ipic >;
+			phy-handle = < &phy0 >;
+		};
+
+		// USB ULPI1
+		//usb@3000 {
+		//	device_type = "usb";
+		//	compatible = "fsl-usb2-dr";
+		//	reg = <0x3000 0x400>;
+		//	#address-cells = <1>;
+		//	#size-cells = <0>;
+		//	interrupt-parent = < &ipic >;
+		//	interrupts = <43 0x8>;
+		//	dr_mode = "host";
+		//	phy_type = "ulpi";
+		//	big-endian-regs;
+		//};
+
+		// USB ULPI2
+		//usb@4000 {
+		//	device_type = "usb";
+		//	compatible = "fsl-usb2-dr";
+		//	reg = <0x4000 0x400>;
+		//	#address-cells = <1>;
+		//	#size-cells = <0>;
+		//	interrupt-parent = < &ipic >;
+		//	interrupts = <44 0x8>;
+		//	dr_mode = "otg";
+		//	phy_type = "ulpi";
+		//	big-endian-regs;
+		//};
+
+		mdio@4800 {
+			device_type = "mdio";
+			compatible = "fsl,mpc5121-fec-mdio";
+			reg = <0x4800 0x800>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			phy1: ethernet-phy@0 {
+				reg = <1>;
+				device_type = "ethernet-phy";
+			};
+		};
+
+		ethernet@4800 {
+			device_type = "network";
+			compatible = "fsl,mpc5121-fec";
+			reg = <0x4800 0x800>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <5 0x8>;
+			interrupt-parent = < &ipic >;
+			phy-handle = < &phy1 >;
+		};
+
+		// IO control
+		ioctl@a000 {
+			compatible = "fsl,mpc5125-ioctl";
+			reg = <0xA000 0x1000>;
+		};
+
+		// PSC0 in ac97 mode
+		//ac97@11000 {
+		//	device_type = "sound";
+		//	compatible = "fsl,mpc5125-psc-ac97", "fsl,mpc5125-psc";
+		//	cell-index = <0>;
+		//	reg = <0x11000 0x100>;
+		//	interrupts = <40 0x8>;
+		//	interrupt-parent = < &ipic >;
+		//	fsl,mode = "ac97-slave";
+		//	rx-fifo-size = <384>;
+		//	tx-fifo-size = <384>;
+		//};
+
+		// 5125 PSCs are not 52xx or 5121 PSC compatible
+		// PSC1 uart0 aka ttyPSC0
+		serial@11100 {
+			device_type = "serial";
+			compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
+			port-number = <0>;
+			cell-index = <1>;
+			reg = <0x11100 0x100>;
+			interrupts = <40 0x8 71 0x8>;
+			interrupt-parent = < &ipic >;
+			fsl,rx-fifo-size = <16>;
+			fsl,tx-fifo-size = <16>;
+			nodcd;
+		};
+
+		// PSC9 uart1 aka ttyPSC1
+		serial@11900 {
+			device_type = "serial";
+			compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
+			port-number = <1>;
+			cell-index = <9>;
+			reg = <0x11900 0x100>;
+			interrupts = <40 0x8 32 0x8>;
+			interrupt-parent = < &ipic >;
+			fsl,rx-fifo-size = <16>;
+			fsl,tx-fifo-size = <16>;
+			nodcd;
+		};
+
+		pscfifo@11f00 {
+			compatible = "fsl,mpc5121-psc-fifo";
+			reg = <0x11f00 0x100>;
+			interrupts = <40 0x8>;
+			interrupt-parent = < &ipic >;
+		};
+
+		dma@14000 {
+			compatible = "fsl,mpc5121-dma"; // old name: "mpc512x-dma2"
+			reg = <0x14000 0x1800>;
+			interrupts = <65 0x8>;
+			interrupt-parent = < &ipic >;
+		};
+	};
+};
arch/powerpc/platforms/512x/Kconfig +14 -0
index 27b0651..0dde4b0 100644
@@ -26,6 +26,20 @@ config MPC5121_GENERIC
 	  Compatible boards include:  Protonic LVT base boards (ZANMCU
 	  and VICVT2).
 
+config PPC_MPC5125
+	bool "Generic support for MPC5125 based boards"
+	depends on PPC_MPC512x
+	select DEFAULT_UIMAGE
+	select PPC_INDIRECT_PCI
+	default n
+
+config MPC5125_TWR
+	bool "Freescale MPC5125 Tower system"
+	depends on PPC_MPC512x
+	select PPC_MPC5125
+	help
+	  This option enables support for the MPC5125 TWR board.
+
 config PDM360NG
 	bool "ifm PDM360NG board"
 	depends on PPC_MPC512x
arch/powerpc/platforms/512x/Makefile +1 -0
index 4efc1c4..5c17561 100644
@@ -5,3 +5,4 @@ obj-y				+= clock.o mpc512x_shared.o
 obj-$(CONFIG_MPC5121_ADS)	+= mpc5121_ads.o mpc5121_ads_cpld.o
 obj-$(CONFIG_MPC5121_GENERIC)	+= mpc5121_generic.o
 obj-$(CONFIG_PDM360NG)		+= pdm360ng.o
+obj-$(CONFIG_MPC5125_TWR)	+= mpc5125_twr.o
arch/powerpc/platforms/512x/clock.c +8 -1
index 3dc2a8d..962c0ba 100644
@@ -669,6 +669,13 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
 	clk->rate = mclk_src / mclk_div;
 }
 
+
+#ifdef CONFIG_PPC_MPC5125
+#define PSC_PREFIX "mpc5125"
+#else
+#define PSC_PREFIX "mpc5121"
+#endif
+
 /*
  * Find all psc nodes in device tree and assign a clock
  * with name "psc%d_mclk" and dev pointing at the device

@@ -680,7 +687,7 @@ static void psc_clks_init(void)
 	const u32 *cell_index;
 	struct platform_device *ofdev;
 
-	for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+	for_each_compatible_node(np, NULL, "fsl," PSC_PREFIX "-psc") {
 		cell_index = of_get_property(np, "cell-index", NULL);
 		if (cell_index) {
 			int pscnum = *cell_index;
arch/powerpc/platforms/512x/mpc5125_twr.c new file +162 -0

162 lines not on this page · raw message

arch/powerpc/platforms/512x/mpc512x.h +3 -1
index 1ab6d11..70c66c6 100644
@@ -13,8 +13,10 @@
 #define __MPC512X_H__
 extern void __init mpc512x_init_IRQ(void);
 extern void __init mpc512x_init(void);
+extern void __init mpc512x_restart_init(void);
 extern int __init mpc5121_clk_init(void);
-void __init mpc512x_declare_of_platform_devices(void);
+extern void __init mpc512x_declare_of_platform_devices(void);
+extern void __init mpc512x_psc_fifo_init(char *psc_name);
 extern void mpc512x_restart(char *cmd);
 extern void mpc512x_init_diu(void);
 extern void mpc512x_setup_diu(void);
arch/powerpc/platforms/512x/mpc512x_shared.c +8 -4
index e41ebbd..411fc9d 100644
@@ -32,7 +32,7 @@
 
 static struct mpc512x_reset_module __iomem *reset_module_base;
 
-static void __init mpc512x_restart_init(void)
+void __init mpc512x_restart_init(void)
 {
 	struct device_node *np;
 

@@ -401,15 +401,19 @@ static unsigned int __init get_fifo_size(struct device_node *np,
 		    ((u32)(_base) + sizeof(struct mpc52xx_psc)))
 
 /* Init PSC FIFO space for TX and RX slices */
-void __init mpc512x_psc_fifo_init(void)
+void __init mpc512x_psc_fifo_init(char *psc_name)
 {
 	struct device_node *np;
 	void __iomem *psc;
 	unsigned int tx_fifo_size;
 	unsigned int rx_fifo_size;
+	char *default_psc = "fsl,mpc5121-psc";
 	int fifobase = 0; /* current fifo address in 32 bit words */
 
-	for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+	if (!psc_name)
+		psc_name = default_psc;
+
+	for_each_compatible_node(np, NULL, psc_name) {
 		tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size");
 		rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size");
 

@@ -461,5 +465,5 @@ void __init mpc512x_init(void)
 	mpc512x_declare_of_platform_devices();
 	mpc5121_clk_init();
 	mpc512x_restart_init();
-	mpc512x_psc_fifo_init();
+	mpc512x_psc_fifo_init(NULL);
 }
#1 lore raw

Hi Vladimir,

(if possible, please provide a diffstat with the patches)

Quoted 19 lines
arch/powerpc/platforms/512x/clock.c +7 -0
index 3dc2a8d..962c0ba 100644
@@ -669,6 +669,13 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
 	clk->rate = mclk_src / mclk_div;
 }
 
+
+#ifdef CONFIG_PPC_MPC5125
+#define PSC_PREFIX "mpc5125"
+#else
+#define PSC_PREFIX "mpc5121"
+#endif
+
 /*
  * Find all psc nodes in device tree and assign a clock
  * with name "psc%d_mclk" and dev pointing at the device

arch/powerpc/platforms/512x/clock.c static void psc_clks_init(void) · line 690

Quoted 5 lines
arch/powerpc/platforms/512x/clock.c +1 -1
@@ -680,7 +687,7 @@ static void psc_clks_init(void)
 	const u32 *cell_index;
 	struct platform_device *ofdev;
 
-	for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+	for_each_compatible_node(np, NULL, "fsl," PSC_PREFIX "-psc") {

Uh, that makes it impossible to have one kernel for mpc5121/5.

Quoted 5 lines
arch/powerpc/platforms/512x/clock.c +1 -1
-void __init mpc512x_psc_fifo_init(void)
+void __init mpc512x_psc_fifo_init(char *psc_name)
 {
 	struct device_node *np;
arch/powerpc/platforms/512x/clock.c +0 -0
 	void __iomem *psc;

arch/powerpc/platforms/512x/clock.c

Quoted 10 lines
arch/powerpc/platforms/512x/clock.c +5 -1
 	unsigned int tx_fifo_size;
 	unsigned int rx_fifo_size;
+	char *default_psc = "fsl,mpc5121-psc";
 	int fifobase = 0; /* current fifo address in 32 bit words */
 
-	for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+	if (!psc_name)
+		psc_name = default_psc;
+
+	for_each_compatible_node(np, NULL, psc_name) {

I think this goes more to the right direction, although you passed the non-default string for mpc5125 in the board-config, which is the wrong place, because it is a platform thing.

What about something like:

	if of_find_compatible_node(startpoint, NULL, "fsl,mpc5121-psc")
		psc_compat = "fsl,mpc5121-psc";
	else if of_find_compatible_node(startpoint, NULL, "fsl,mpc5125-psc")
		psc_compat = "fsl,mpc5125-psc";
	else if
		/* Problem handling */

Dunno, might be worth to put it into a function as it could be used here and in the block above.

Also, I noticed quite a number of magic values (e.g. 0x76). I guess those are register and bit names, which should be used instead.

Thanks,

Wolfram

Signature · 2 lines
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
author
#2 lore raw

Hi Wolfram.
I create function for select compat string and give name for registers.

commit fe8895542d537567f43f99af8234e7326451197e

Author: Ermakov Vladimir <[email protected]>
Date:   Thu Mar 17 11:10:49 2011 +0300

Adds Freescale TWR-MPC5125 device tree and platform code.

Currently following is supported:
- NAND
- FEC1 and FEC2
- RTC
- PSC UART

Signed-off-by Vladimir Ermakov <[email protected]>

---
v2:
- add PSC compat string selection
- add ioctl defines

(quoted diff) +0 -0

b/arch/powerpc/boot/dts/mpc5125twr.dts
new file mode 100644
index 0000000..54f568f

arch/powerpc/boot/dts/mpc5125twr.dts new file +6 -0
@@ -0,0 +1,394 @@
+/*
+ * STx/Freescale ADS5125 MPC5125 silicon
+ *
+ * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute  it and/or modify i=

t
+ * under the terms of the GNU General Public License as published by th= e
+ * Free Software Foundation; either version 2 of the License, or (at you= r
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model =3D "mpc5125ads";
+ compatible =3D "fsl,mpc5125ads";
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+
+ cpus {
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+
+ PowerPC,5125@0 {
+ device_type =3D "cpu";
+ reg =3D <0>;
+ d-cache-line-size =3D <0x20>; // 32 bytes
+ i-cache-line-size =3D <0x20>; // 32 bytes
+ d-cache-size =3D <0x8000>; // L1, 32K
+ i-cache-size =3D <0x8000>; // L1, 32K
+ timebase-frequency =3D <49500000>;// 49.5 MHz (csb/4)
+ bus-frequency =3D <198000000>; // 198 MHz csb bus
+ clock-frequency =3D <396000000>; // 396 MHz ppc core
+ };
+ };
+
+ memory {
+ device_type =3D "memory";
+ reg =3D <0x00000000 0x10000000>; // 256MB at 0
+ };
+
+ sram@30000000 {
+ compatible =3D "fsl,mpc5121-sram";
+ reg =3D <0x30000000 0x08000>; // 32K at 0x30000000
+ };
+
+ nfc@40000000 {
+ compatible =3D "fsl,mpc5125-nfc";
+ reg =3D <0x40000000 0x100000>; // 1M at 0x40000000
+ interrupts =3D <6 0x8>;
+ interrupt-parent =3D < &ipic >;
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+ bank-width =3D <1>;
+ write-size =3D <4096>;
+ spare-size =3D <128>;
+ chips =3D <1>;
+ // NOTE: partition map different than in BSP
+ nand-spl@0 {
+ label =3D "loader";
+ reg =3D <0x00000000 0x00100000>;
+ read-only;
+ };
+ uboot@100000 {
+ label =3D "uboot";
+ reg =3D <0x00100000 0x00100000>;
+ read-only;
+ };
+ uboot-env@200000 {
+ label =3D "uboot-env";
+ reg =3D <0x00200000 0x00100000>;
+ read-only;
+ };
+ kernel300000 {
+ label =3D "kernel";
+ reg =3D <0x00300000 0x00800000>;
+ };
+ device-tree00000 {
+ label =3D "device-tree";
+ reg =3D <0x00b00000 0x00100000>;
+ };
+ ramboot-rootfs@c00000 {
+ label =3D "ramboot-rootfs";
+ reg =3D <0x00c00000 0x00800000>;
+ };
+ rootfs@1400000 {
+ label =3D "rootfs";
+ reg =3D <0x01400000 0x01400000>;
+ };
+ user@2800000 {
+ label =3D "user";
+ reg =3D <0x02800000 0x01400000>;
+ };
+ SRAM@4200000 {
+ label =3D "SRAM"; // NVRAM emul
+ reg =3D <0x04200000 0x01400000>;
+ };
+ prom@5600000 {
+ label =3D "prom";
+ reg =3D <0x05600000 0x01400000>;
+ };
+ //data@2800000 {
+ // label =3D "data";
+ // reg =3D <0x28000000 0xeac00000>;
+ //};
+ };
+
+ soc@80000000 {
+ compatible =3D "fsl,mpc5121-immr";
+ device_type =3D "soc";
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+ #interrupt-cells =3D <2>;
+ ranges =3D <0x0 0x80000000 0x400000>;
+ reg =3D <0x80000000 0x400000>;
+ bus-frequency =3D <66000000>; // 66 MHz ips bus
+
+
+ // IPIC
+ // interrupts cell =3D <intr #, sense>
+ // sense values match linux IORESOURCE_IRQ_* defines:
+ // sense =3D=3D 8: Level, low assertion
+ // sense =3D=3D 2: Edge, high-to-low change
+ //
+ ipic: interrupt-controller@c00 {
+ compatible =3D "fsl,mpc5121-ipic", "fsl,ipic";
+ interrupt-controller;
+ #address-cells =3D <0>;
+ #interrupt-cells =3D <2>;
+ reg =3D <0xc00 0x100>;
+ };
+
+ rtc@a00 { // Real time clock
+ compatible =3D "fsl,mpc5121-rtc";
+ reg =3D <0xa00 0x100>;
+ interrupts =3D <79 0x8 80 0x8>;
+ interrupt-parent =3D < &ipic >;
+ };
+
+ reset@e00 { // Reset module
+ compatible =3D "fsl,mpc5121-reset";
+ reg =3D <0xe00 0x100>;
+ };
+
+ clock@f00 { // Clock control
+ compatible =3D "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
+ reg =3D <0xf00 0x100>;
+ };
+
+ pmc@1000{ // Power Management Controller
+ compatible =3D "fsl,mpc5121-pmc";
+ reg =3D <0x1000 0x100>;
+ interrupts =3D <83 0x2>;
+ interrupt-parent =3D < &ipic >;
+ };
+
+ gpio@1100 {
+ compatible =3D "fsl,mpc5125-gpio";
+ cell-index =3D <0>;
+ reg =3D <0x1100 0x080>;
+ interrupts =3D <78 0x8>;
+ interrupt-parent =3D < &ipic >;
+ };
+
+ gpio@1180 {
+ compatible =3D "fsl,mpc5125-gpio1";
+ cell-index =3D <1>;
+ reg =3D <0x1180 0x080>;
+ interrupts =3D <78 0x8>;
+ interrupt-parent =3D < &ipic >;
+ };
+
+ can@1300 { // CAN rev.2
+ compatible =3D "fsl,mpc5121-mscan";
+ cell-index =3D <0>;
+ interrupts =3D <12 0x8>;
+ interrupt-parent =3D < &ipic >;
+ reg =3D <0x1300 0x80>;
+ };
+
+ can@1380 {
+ compatible =3D "fsl,mpc5121-mscan";
+ cell-index =3D <1>;
+ interrupts =3D <13 0x8>;
+ interrupt-parent =3D < &ipic >;
+ reg =3D <0x1380 0x80>;
+ };
+
+ sdhc@1500 {
+ compatible =3D "fsl,mpc5125-sdhc";
+ interrupts =3D <8 0x8>;
+ interrupt-parent =3D < &ipic >;
+ reg =3D <0x1500 0x100>;
+ };
+
+ i2c@1700 {
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ compatible =3D "fsl-i2c";
+ cell-index =3D <0>;
+ reg =3D <0x1700 0x20>;
+ interrupts =3D <0x9 0x8>;
+ interrupt-parent =3D < &ipic >;
+ fsl5200-clocking;
+ };
+
+ i2c@1720 {
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ compatible =3D "fsl-i2c";
+ cell-index =3D <1>;
+ reg =3D <0x1720 0x20>;
+ interrupts =3D <0xa 0x8>;
+ interrupt-parent =3D < &ipic >;
+ fsl5200-clocking;
+ };
+
+ i2c@1740 {
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ compatible =3D "fsl-i2c";
+ cell-index =3D <2>;
+ reg =3D <0x1740 0x20>;
+ interrupts =3D <0xb 0x8>;
+ interrupt-parent =3D < &ipic >;
+ fsl5200-clocking;
+ };
+
+ i2ccontrol@1760 {
+ compatible =3D "fsl,mpc5121-i2c-ctrl";
+ reg =3D <0x1760 0x8>;
+ };
+
+ //diu@2100 {
+ // device_type =3D "display";
+ // compatible =3D "fsl-diu";
+ // reg =3D <0x2100 0x100>;
+ // interrupts =3D <64 0x8>;
+ // interrupt-parent =3D < &ipic >;
+ //};
+
+ // MPC5125e has two more CAN ports
+ // but they are not used on ADS5125
+ //can@2300 {
+ // compatible =3D "fsl,mpc5121-mscan";
+ // cell-index =3D <2>;
+ // interrupts =3D <90 0x8>;
+ // interrupt-parent =3D < &ipic >;
+ // reg =3D <0x2300 0x80>;
+ //};
+
+ //can@2380 {
+ // compatible =3D "fsl,mpc5121-mscan";
+ // cell-index =3D <3>;
+ // interrupts =3D <91 0x8>;
+ // interrupt-parent =3D < &ipic >;
+ // reg =3D <0x2380 0x80>;
+ //};
+
+ mdio@2800 {
+ device_type =3D "mdio";
+ compatible =3D "fsl,mpc5121-fec-mdio";
+ reg =3D <0x2800 0x800>;
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ phy0: ethernet-phy@0 {
+ reg =3D <1>;
+ device_type =3D "ethernet-phy";
+ };
+ };
+
+ ethernet@2800 {
+ device_type =3D "network";
+ compatible =3D "fsl,mpc5121-fec";
+ reg =3D <0x2800 0x800>;
+ local-mac-address =3D [ 00 00 00 00 00 00 ];
+ interrupts =3D <4 0x8>;
+ interrupt-parent =3D < &ipic >;
+ phy-handle =3D < &phy0 >;
+ };
+
+ // USB ULPI1
+ //usb@3000 {
+ // device_type =3D "usb";
+ // compatible =3D "fsl-usb2-dr";
+ // reg =3D <0x3000 0x400>;
+ // #address-cells =3D <1>;
+ // #size-cells =3D <0>;
+ // interrupt-parent =3D < &ipic >;
+ // interrupts =3D <43 0x8>;
+ // dr_mode =3D "host";
+ // phy_type =3D "ulpi";
+ // big-endian-regs;
+ //};
+
+ // USB ULPI2
+ //usb@4000 {
+ // device_type =3D "usb";
+ // compatible =3D "fsl-usb2-dr";
+ // reg =3D <0x4000 0x400>;
+ // #address-cells =3D <1>;
+ // #size-cells =3D <0>;
+ // interrupt-parent =3D < &ipic >;
+ // interrupts =3D <44 0x8>;
+ // dr_mode =3D "otg";
+ // phy_type =3D "ulpi";
+ // big-endian-regs;
+ //};
+
+ mdio@4800 {
+ device_type =3D "mdio";
+ compatible =3D "fsl,mpc5121-fec-mdio";
+ reg =3D <0x4800 0x800>;
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ phy1: ethernet-phy@0 {
+ reg =3D <1>;
+ device_type =3D "ethernet-phy";
+ };
+ };
+
+ ethernet@4800 {
+ device_type =3D "network";
+ compatible =3D "fsl,mpc5121-fec";
+ reg =3D <0x4800 0x800>;
+ local-mac-address =3D [ 00 00 00 00 00 00 ];
+ interrupts =3D <5 0x8>;
+ interrupt-parent =3D < &ipic >;
+ phy-handle =3D < &phy1 >;
+ };
+
+ // IO control
+ ioctl@a000 {
+ compatible =3D "fsl,mpc5125-ioctl";
+ reg =3D <0xA000 0x1000>;
+ };
+
+ // PSC0 in ac97 mode
+ //ac97@11000 {
+ // device_type =3D "sound";
+ // compatible =3D "fsl,mpc5125-psc-ac97", "fsl,mpc5125-psc";
+ // cell-index =3D <0>;
+ // reg =3D <0x11000 0x100>;
+ // interrupts =3D <40 0x8>;
+ // interrupt-parent =3D < &ipic >;
+ // fsl,mode =3D "ac97-slave";
+ // rx-fifo-size =3D <384>;
+ // tx-fifo-size =3D <384>;
+ //};
+
+ // 5125 PSCs are not 52xx or 5121 PSC compatible
+ // PSC1 uart0 aka ttyPSC0
+ serial@11100 {
+ device_type =3D "serial";
+ compatible =3D "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
+ port-number =3D <0>;
+ cell-index =3D <1>;
+ reg =3D <0x11100 0x100>;
+ interrupts =3D <40 0x8 71 0x8>;
+ interrupt-parent =3D < &ipic >;
+ fsl,rx-fifo-size =3D <16>;
+ fsl,tx-fifo-size =3D <16>;
+ nodcd;
+ };
+
+ // PSC9 uart1 aka ttyPSC1
+ serial@11900 {
+ device_type =3D "serial";
+ compatible =3D "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
+ port-number =3D <1>;
+ cell-index =3D <9>;
+ reg =3D <0x11900 0x100>;
+ interrupts =3D <40 0x8 32 0x8>;
+ interrupt-parent =3D < &ipic >;
+ fsl,rx-fifo-size =3D <16>;
+ fsl,tx-fifo-size =3D <16>;
+ nodcd;
+ };
+
+ pscfifo@11f00 {
+ compatible =3D "fsl,mpc5121-psc-fifo";
+ reg =3D <0x11f00 0x100>;
+ interrupts =3D <40 0x8>;
+ interrupt-parent =3D < &ipic >;
+ };
+
+ dma@14000 {
+ compatible =3D "fsl,mpc5121-dma"; // old name: "mpc512x-dma2"
+ reg =3D <0x14000 0x1800>;
+ interrupts =3D <65 0x8>;
+ interrupt-parent =3D < &ipic >;
+ };
+ };
+};

(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/Kconfig
index 27b0651..0dde4b0 100644

arch/powerpc/platforms/512x/Kconfig +14 -0
@@ -26,6 +26,20 @@ config MPC5121_GENERIC
 	  Compatible boards include:  Protonic LVT base boards (ZANMCU
 	  and VICVT2).
 
+config PPC_MPC5125
+	bool "Generic support for MPC5125 based boards"
+	depends on PPC_MPC512x
+	select DEFAULT_UIMAGE
+	select PPC_INDIRECT_PCI
+	default n
+
+config MPC5125_TWR
+	bool "Freescale MPC5125 Tower system"
+	depends on PPC_MPC512x
+	select PPC_MPC5125
+	help
+	  This option enables support for the MPC5125 TWR board.
+
 config PDM360NG
 	bool "ifm PDM360NG board"
 	depends on PPC_MPC512x
(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/Makefile
index 4efc1c4..5c17561 100644

arch/powerpc/platforms/512x/Makefile +1 -0
@@ -5,3 +5,4 @@ obj-y				+=3D clock.o mpc512x_shared.o
 obj-$(CONFIG_MPC5121_ADS)	+=3D mpc5121_ads.o mpc5121_ads_cpld.o
 obj-$(CONFIG_MPC5121_GENERIC)	+=3D mpc5121_generic.o
 obj-$(CONFIG_PDM360NG)		+=3D pdm360ng.o
+obj-$(CONFIG_MPC5125_TWR)	+=3D mpc5125_twr.o
(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/clock.c
index 3dc2a8d..5cadf8e 100644

arch/powerpc/platforms/512x/clock.c +21 -1
@@ -606,6 +606,21 @@ static void rate_clks_init(void)
  */
 struct clk dev_clks[2][32];
 
+char *mpc512x_select_psc_compat(void)
+{
+	char *psc_compats[] =3D {
+		"fsl,mpc5121-psc",
+		"fsl,mpc5125-psc"
+	};
+	int i;
+
+	for (i =3D 0; i < ARRAY_SIZE(psc_compats); i++)
+		if (of_find_compatible_node(NULL, NULL, psc_compats[i]))
+			return psc_compats[i];
+
+	return NULL;
+}
+
 /*
  * Given a psc number return the dev_clk
  * associated with it

@@ -679,8 +694,13 @@ static void psc_clks_init(void)
 	struct device_node *np;
 	const u32 *cell_index;
 	struct platform_device *ofdev;
+	char *psc_compat;
+
+	psc_compat =3D mpc512x_select_psc_compat();
+	if (!psc_compat)
+		return;
 
-	for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+	for_each_compatible_node(np, NULL, psc_compat) {
 		cell_index =3D of_get_property(np, "cell-index", NULL);
 		if (cell_index) {
 			int pscnum =3D *cell_index;
(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/mpc5125_twr.c
new file mode 100644
index 0000000..b4f931f

arch/powerpc/platforms/512x/mpc5125_twr.c new file +59 -0

59 lines not on this page · raw message

S=3D3
+
+static void mpc5125_psc_iopad_init(void __iomem *ioctl, char *name) +{
+ struct device_node *np;
+ const u32 *cell_index;
+ char *default_psc =3D "fsl,mpc5125-psc";
+ char *psc_name;
+
+ if (name)
+ psc_name =3D name;
+ else
+ psc_name =3D default_psc;
+
+ for_each_compatible_node(np, NULL, psc_name) {
+ cell_index =3D of_get_property(np, "cell-index", NULL);
+ if (cell_index) {
+ u8 __iomem *pscioctl;
+ int psc_num =3D *cell_index;
+ if (psc_num > 1)
+ continue;
+
+ pscioctl =3D ioctl + PSC_TO_IOCTL_OFFSET(psc_num);
+ out_8(pscioctl + IOCTL_PSCx_0, IOCTL_PSCx_0_MODE); // NOTE maybe wrong
+ out_8(pscioctl + IOCTL_PSCx_1, IOCTL_DEFAULT_MODE);
+ out_8(pscioctl + IOCTL_PSCx_2, IOCTL_DEFAULT_MODE);
+ out_8(pscioctl + IOCTL_PSCx_3, IOCTL_DEFAULT_MODE);
+ out_8(pscioctl + IOCTL_PSCx_4, IOCTL_DEFAULT_MODE);
+ }
+ }
+}
+
+static void mpc5125_fec2_usb_io_init(void __iomem *ioctl, int isusb) +{
+ int i;
+ const u8 offset[12] =3D {
+ IOCTL_USB1_DATA0, IOCTL_USB1_DATA1,
+ IOCTL_USB1_DATA2, IOCTL_USB1_DATA3,
+ IOCTL_USB1_DATA4, IOCTL_USB1_DATA5,
+ IOCTL_USB1_DATA6, IOCTL_USB1_DATA7,
+ IOCTL_USB1_STOP, IOCTL_USB1_CLK,
+ IOCTL_USB1_NEXT, IOCTL_USB1_DIR
+ };
+ u8 mode;
+
+ mode =3D (isusb) ? IOCTL_DEFAULT_MODE : IOCTL_FEC2_MODE;
+ for (i =3D 0; i < ARRAY_SIZE(offset); i++)
+ out_8(ioctl + offset[i], mode);
+}
+
+static void __init mpc5125_board_setup(void)
+{
+ struct device_node *np;
+
+ /*
+ * io pad config
+ */
+ np =3D of_find_compatible_node(NULL, NULL, "fsl,mpc5125-ioctl");
+ if (np) {
+ void __iomem *ioctl =3D of_iomap(np, 0);
+
+ mpc5125_psc_iopad_init(ioctl, NULL);
+ mpc5125_fec2_usb_io_init(ioctl, 0);
+
+ of_node_put(np);
+ iounmap(ioctl);
+ }
+}
+
+static void __init mpc5125_ads_setup_arch(void)
+{
+ printk(KERN_INFO "MPC5125 ADS board from Freescale Semiconductor\n");
+
+ mpc5125_board_setup();
+}
+
+static struct of_device_id __initdata of_bus_ids[] =3D {
+ { .name =3D "soc", },
+ {},
+};
+
+static void __init mpc5125_ads_declare_of_platform_devices(void) +{
+ struct device_node *np;
+
+ if (of_platform_bus_probe(NULL, of_bus_ids, NULL))
+ printk(KERN_ERR __FILE__ ": "
+ "Error while probing of_platform bus\n");
+
+ np =3D of_find_compatible_node(NULL, NULL, "fsl,mpc5125-nfc");
+ if (np) {
+ of_platform_device_create(np, NULL, NULL);
+ of_node_put(np);
+ }
+}
+
+static void __init mpc5125_ads_init(void)
+{
+ mpc5125_ads_declare_of_platform_devices();
+ mpc5121_clk_init();
+ mpc512x_restart_init();
+ mpc512x_psc_fifo_init();
+}
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init mpc5125_ads_probe(void)
+{
+ unsigned long root =3D of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "fsl,mpc5125ads");
+}
+
+define_machine(mpc5125_ads) {
+ .name =3D "MPC5125 ADS",
+ .probe =3D mpc5125_ads_probe,
+ .setup_arch =3D mpc5125_ads_setup_arch,
+ .init =3D mpc5125_ads_init,
+ .init_IRQ =3D mpc512x_init_IRQ,
+ .get_irq =3D ipic_get_irq,
+ .calibrate_decr =3D generic_calibrate_decr,
+ .restart =3D mpc512x_restart,
+};

(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/mpc512x.h
index 1ab6d11..91c903f 100644

arch/powerpc/platforms/512x/mpc512x.h +4 -1
@@ -13,8 +13,11 @@
 #define __MPC512X_H__
 extern void __init mpc512x_init_IRQ(void);
 extern void __init mpc512x_init(void);
+extern void __init mpc512x_restart_init(void);
 extern int __init mpc5121_clk_init(void);
-void __init mpc512x_declare_of_platform_devices(void);
+extern void __init mpc512x_declare_of_platform_devices(void);
+extern void __init mpc512x_psc_fifo_init(void);
+extern char *mpc512x_select_psc_compat(void);
 extern void mpc512x_restart(char *cmd);
 extern void mpc512x_init_diu(void);
 extern void mpc512x_setup_diu(void);
(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/mpc512x_shared.c
index e41ebbd..52283d6 100644

arch/powerpc/platforms/512x/mpc512x_shared.c +9 -2
@@ -32,7 +32,7 @@
 
 static struct mpc512x_reset_module __iomem *reset_module_base;
 
-static void __init mpc512x_restart_init(void)
+void __init mpc512x_restart_init(void)
 {
 	struct device_node *np;
 

@@ -407,9 +407,16 @@ void __init mpc512x_psc_fifo_init(void)
 	void __iomem *psc;
 	unsigned int tx_fifo_size;
 	unsigned int rx_fifo_size;
+	char *psc_compat;
 	int fifobase =3D 0; /* current fifo address in 32 bit words */
 
-	for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+	psc_compat =3D mpc512x_select_psc_compat();
+	if (!psc_compat) {
+		pr_err("%s: no compatible devices found\n", __func__);
+		return;
+	}
+
+	for_each_compatible_node(np, NULL, psc_compat) {
 		tx_fifo_size =3D get_fifo_size(np, "fsl,tx-fifo-size");
 		rx_fifo_size =3D get_fifo_size(np, "fsl,rx-fifo-size");

2011/3/18 Wolfram Sang <[email protected]>

Quoted 6 lines

Hi Vladimir,

(if possible, please provide a diffstat with the patches)

arch/powerpc/platfor=

Quoted 1 line
arch/powerpc/platfor= renamed from arch/powerpc/platforms/512x/clock.c +0 -0

ms/512x/clock.c

Quoted 4 lines

arch/powerpc/platforms/512x/clock.c static void psc_calc_rate(struct clk *clk, int psc=

Quoted 4 lines

index 3dc2a8d..962c0ba 100644

arch/powerpc/platforms/512x/clock.c +0 -0
@@ -669,6 +669,13 @@ static void psc_calc_rate(struct clk *clk, int psc=

num, struct device_node *np)

Quoted 17 lines
Quoted 17 lines
arch/powerpc/platforms/512x/clock.c +7 -0
 =C2=A0 =C2=A0 =C2=A0 clk->rate =3D mclk_src / mclk_div;
 =C2=A0}
 
+
+#ifdef CONFIG_PPC_MPC5125
+#define PSC_PREFIX "mpc5125"
+#else
+#define PSC_PREFIX "mpc5121"
+#endif
+

=C2=A0/*
=C2=A0 * Find all psc nodes in device tree and assign a clock =C2=A0 * with name "psc%d_mclk" and dev pointing at the device

arch/powerpc/platforms/512x/clock.c +0 -0
@@ -680,7 +687,7 @@ static void psc_clks_init(void)
 =C2=A0 =C2=A0 =C2=A0 const u32 *cell_index;
 =C2=A0 =C2=A0 =C2=A0 struct platform_device *ofdev;
Quoted 2 lines

arch/powerpc/platforms/512x/clock.c static void psc_clks_init(void) · line 690

Quoted 2 lines
arch/powerpc/platforms/512x/clock.c +1 -1
- =C2=A0 =C2=A0 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+ =C2=A0 =C2=A0 for_each_compatible_node(np, NULL, "fsl," PSC_PREFIX "-=

psc") {

Quoted 12 lines

Uh, that makes it impossible to have one kernel for mpc5121/5.

Quoted 9 lines
arch/powerpc/platforms/512x/clock.c +1 -1
-void __init mpc512x_psc_fifo_init(void)
+void __init mpc512x_psc_fifo_init(char *psc_name)
 =C2=A0{
 =C2=A0 =C2=A0 =C2=A0 struct device_node *np;

=C2=A0 =C2=A0 =C2=A0 void __iomem *psc;
=C2=A0 =C2=A0 =C2=A0 unsigned int tx_fifo_size;
=C2=A0 =C2=A0 =C2=A0 unsigned int rx_fifo_size;
+ =C2=A0 =C2=A0 char *default_psc =3D "fsl,mpc5121-psc"; =C2=A0 =C2=A0 =C2=A0 int fifobase =3D 0; /* current fifo address in 32 =

bit words */

Quoted 9 lines
Quoted 6 lines

- =C2=A0 =C2=A0 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+ =C2=A0 =C2=A0 if (!psc_name)
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 psc_name =3D default_psc; +
+ =C2=A0 =C2=A0 for_each_compatible_node(np, NULL, psc_name) {

I think this goes more to the right direction, although you passed the non-default string for mpc5125 in the board-config, which is the wrong pl=

ace,

Quoted 5 lines

because it is a platform thing.

What about something like:

=C2=A0 =C2=A0 =C2=A0 =C2=A0if of_find_compatible_node(startpoint, NULL, "=

fsl,mpc5121-psc")

Quoted 1 line

=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0psc_compat =3D "fs=

l,mpc5121-psc";

Quoted 1 line

=C2=A0 =C2=A0 =C2=A0 =C2=A0else if of_find_compatible_node(startpoint, NU=

LL, "fsl,mpc5125-psc")

Quoted 1 line

=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0psc_compat =3D "fs=

l,mpc5125-psc";

Quoted 2 lines

=C2=A0 =C2=A0 =C2=A0 =C2=A0else if
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Problem handlin=

g */

Quoted 2 lines

Dunno, might be worth to put it into a function as it could be used here =

and in

Quoted 3 lines

the block above.

Also, I noticed quite a number of magic values (e.g. 0x76). I guess those=

are

Quoted 8 lines

register and bit names, which should be used instead.

Thanks,

=C2=A0 Wolfram

--
Pengutronix e.K. =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | Wolfram Sang =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|

Quoted 1 line

Industrial Linux Solutions =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=

=A0 =C2=A0 | http://www.pengutronix.de/ =C2=A0|

Quoted 9 lines

-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.9 (GNU/Linux)

iEYEARECAAYFAk2CfFYACgkQD27XaX1/VRsmcwCfdqwIn6V6VDwm7wZXm1PDHXmx 0mcAnirFHcCmZ4TqqNXbXfOOWsDPFauA
=3DU2sn
-----END PGP SIGNATURE-----

#3 lore raw
Quoted 13 lines · On Fri, Mar 18, 2011 at 02:35:24PM +0300, [email protected] wrote:
arch/powerpc/platforms/512x/clock.c +4 -0
index 3dc2a8d..5cadf8e 100644
@@ -606,6 +606,21 @@ static void rate_clks_init(void)
  */
 struct clk dev_clks[2][32];
 
+char *mpc512x_select_psc_compat(void)
+{
+	char *psc_compats[] = {
+		"fsl,mpc5121-psc",

arch/powerpc/platforms/512x/clock.c static void rate_clks_init(void) · line 622

Quoted 10 lines
arch/powerpc/platforms/512x/clock.c +10 -0
+		"fsl,mpc5125-psc"
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(psc_compats); i++)
+		if (of_find_compatible_node(NULL, NULL, psc_compats[i]))
+			return psc_compats[i];
+
+	return NULL;
+}

Function looks good to me. Shouldn't that rather be in mpc512x_shared?

arch/powerpc/platforms/512x/clock.c static void rate_clks_init(void) · line 623

Quoted 1 line
arch/powerpc/platforms/512x/clock.c +1 -0
+// IOCTL registers for USB1/FEC2

No c++-style comments, please (here and later).

arch/powerpc/platforms/512x/clock.c static void rate_clks_init(void)

Quoted 11 lines
arch/powerpc/platforms/512x/clock.c +11 -0
+static void mpc5125_psc_iopad_init(void __iomem *ioctl, char *name)
+{
+	struct device_node *np;
+	const u32 *cell_index;
+	char *default_psc = "fsl,mpc5125-psc";
+	char *psc_name;
+
+	if (name)
+		psc_name = name;
+	else
+		psc_name = default_psc;

Caller sets name to NULL. Is this really used?

arch/powerpc/platforms/512x/clock.c

Quoted 3 lines
arch/powerpc/platforms/512x/clock.c +3 -0
+
+	for_each_compatible_node(np, NULL, psc_name) {
+		cell_index = of_get_property(np, "cell-index", NULL);

I seem to recall 'cell-index' is deprecated. Grant?

arch/powerpc/platforms/512x/clock.c

Quoted 8 lines
arch/powerpc/platforms/512x/clock.c +8 -0
+		if (cell_index) {
+			u8 __iomem *pscioctl;
+			int psc_num = *cell_index;
+			if (psc_num > 1)
+				continue;
+
+			pscioctl = ioctl + PSC_TO_IOCTL_OFFSET(psc_num);
+			out_8(pscioctl + IOCTL_PSCx_0, IOCTL_PSCx_0_MODE); // NOTE maybe wrong

Why is it 'maybe wrong'? Can it be improved somehow?

arch/powerpc/platforms/512x/clock.c

Quoted 4 lines
arch/powerpc/platforms/512x/clock.c +4 -0
+			out_8(pscioctl + IOCTL_PSCx_1, IOCTL_DEFAULT_MODE);
+			out_8(pscioctl + IOCTL_PSCx_2, IOCTL_DEFAULT_MODE);
+			out_8(pscioctl + IOCTL_PSCx_3, IOCTL_DEFAULT_MODE);
+			out_8(pscioctl + IOCTL_PSCx_4, IOCTL_DEFAULT_MODE);

The defines make it much more readable, thanks.

arch/powerpc/platforms/512x/clock.c

Quoted 3 lines
arch/powerpc/platforms/512x/clock.c +3 -0
+		}
+	}
+}

Is this function really board-specific or platform specific?

Quoted 7 lines
arch/powerpc/platforms/512x/clock.c +7 -0
+static void mpc5125_fec2_usb_io_init(void __iomem *ioctl, int isusb)
+{
+	int i;
+	const u8 offset[12] = {
+		IOCTL_USB1_DATA0, IOCTL_USB1_DATA1,
+		IOCTL_USB1_DATA2, IOCTL_USB1_DATA3,
+		IOCTL_USB1_DATA4, IOCTL_USB1_DATA5,

arch/powerpc/platforms/512x/clock.c

Quoted 10 lines
arch/powerpc/platforms/512x/clock.c +10 -0
+		IOCTL_USB1_DATA6, IOCTL_USB1_DATA7,
+		IOCTL_USB1_STOP, IOCTL_USB1_CLK,
+		IOCTL_USB1_NEXT, IOCTL_USB1_DIR
+	};
+	u8 mode;
+
+	mode = (isusb) ? IOCTL_DEFAULT_MODE : IOCTL_FEC2_MODE;
+	for (i = 0; i < ARRAY_SIZE(offset); i++)
+		out_8(ioctl + offset[i], mode);
+}

Same question here and later. If it is board specific, the function name should have something like 'twr' in it; but a few things seem mpc5125-generic to me, if I am not mistaken?

Regards,

Wolfram

Signature · 2 lines
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
author
#4 lore raw

commit 3b94215206569d5c2bad20397cebfa9570c921bc

Author: Ermakov Vladimir <[email protected]>
Date:   Thu Mar 17 11:10:49 2011 +0300

Adds Freescale TWR-MPC5125 device tree and platform code.

Currently following is supported:
- NAND
- FEC1 and FEC2
- RTC
- PSC UART

Signed-off-by Vladimir Ermakov <[email protected]>

---
v2:
- add PSC compat string selection
- add ioctl defines

v3:
- less verbose interrupt-parent
- move mpc512x_select_psc_compat() to mpc512x_shared.c
- remove unneded mpc5125_psc_iopad_init()
- fix board prefixes

(quoted diff) +0 -0

b/arch/powerpc/boot/dts/mpc5125twr.dts
new file mode 100644
index 0000000..d899f92

arch/powerpc/boot/dts/mpc5125twr.dts new file +6 -0
@@ -0,0 +1,368 @@
+/*
+ * STx/Freescale ADS5125 MPC5125 silicon
+ *
+ * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute  it and/or modify i=

t
+ * under the terms of the GNU General Public License as published by th= e
+ * Free Software Foundation; either version 2 of the License, or (at you= r
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model =3D "mpc5125twr"; // In BSP "mpc5125ads"
+ compatible =3D "fsl,mpc5125ads";
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+ interrupt-parent =3D <&ipic>;
+
+ cpus {
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+
+ PowerPC,5125@0 {
+ device_type =3D "cpu";
+ reg =3D <0>;
+ d-cache-line-size =3D <0x20>; // 32 bytes
+ i-cache-line-size =3D <0x20>; // 32 bytes
+ d-cache-size =3D <0x8000>; // L1, 32K
+ i-cache-size =3D <0x8000>; // L1, 32K
+ timebase-frequency =3D <49500000>;// 49.5 MHz (csb/4)
+ bus-frequency =3D <198000000>; // 198 MHz csb bus
+ clock-frequency =3D <396000000>; // 396 MHz ppc core
+ };
+ };
+
+ memory {
+ device_type =3D "memory";
+ reg =3D <0x00000000 0x10000000>; // 256MB at 0
+ };
+
+ sram@30000000 {
+ compatible =3D "fsl,mpc5121-sram";
+ reg =3D <0x30000000 0x08000>; // 32K at 0x30000000
+ };
+
+ nfc@40000000 {
+ compatible =3D "fsl,mpc5125-nfc";
+ reg =3D <0x40000000 0x100000>; // 1M at 0x40000000
+ interrupts =3D <6 0x8>;
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+ bank-width =3D <1>;
+ write-size =3D <4096>;
+ spare-size =3D <128>;
+ chips =3D <1>;
+ // NOTE: partition map different than in BSP
+ // First three is the same as in BSP, other differ.
+ nand-spl@0 {
+ label =3D "loader";
+ reg =3D <0x00000000 0x00100000>;
+ read-only;
+ };
+ uboot@100000 {
+ label =3D "uboot";
+ reg =3D <0x00100000 0x00100000>;
+ read-only;
+ };
+ uboot-env@200000 {
+ label =3D "uboot-env";
+ reg =3D <0x00200000 0x00100000>;
+ read-only;
+ };
+ kernel@300000 {
+ label =3D "kernel";
+ reg =3D <0x00300000 0x00800000>;
+ };
+ device-tree@b00000 {
+ label =3D "device-tree";
+ reg =3D <0x00b00000 0x00100000>;
+ };
+ ramboot-rootfs@c00000 {
+ label =3D "ramboot-rootfs";
+ reg =3D <0x00c00000 0x00800000>;
+ };
+ rootfs@1400000 {
+ label =3D "rootfs";
+ reg =3D <0x01400000 0x01400000>;
+ };
+ user@2800000 {
+ label =3D "user";
+ reg =3D <0x02800000 0x01400000>;
+ };
+ SRAM@4200000 {
+ label =3D "SRAM"; // NVRAM emul
+ reg =3D <0x04200000 0x01400000>;
+ };
+ prom@5600000 {
+ label =3D "prom";
+ reg =3D <0x05600000 0x01400000>;
+ };
+ //data@2800000 {
+ // label =3D "data";
+ // reg =3D <0x28000000 0xeac00000>;
+ //};
+ };
+
+ soc@80000000 {
+ compatible =3D "fsl,mpc5121-immr";
+ device_type =3D "soc";
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+ #interrupt-cells =3D <2>;
+ ranges =3D <0x0 0x80000000 0x400000>;
+ reg =3D <0x80000000 0x400000>;
+ bus-frequency =3D <66000000>; // 66 MHz ips bus
+
+ // IPIC
+ // interrupts cell =3D <intr #, sense>
+ // sense values match linux IORESOURCE_IRQ_* defines:
+ // sense =3D=3D 8: Level, low assertion
+ // sense =3D=3D 2: Edge, high-to-low change
+ //
+ ipic: interrupt-controller@c00 {
+ compatible =3D "fsl,mpc5121-ipic", "fsl,ipic";
+ interrupt-controller;
+ #address-cells =3D <0>;
+ #interrupt-cells =3D <2>;
+ reg =3D <0xc00 0x100>;
+ };
+
+ rtc@a00 { // Real time clock
+ compatible =3D "fsl,mpc5121-rtc";
+ reg =3D <0xa00 0x100>;
+ interrupts =3D <79 0x8 80 0x8>;
+ };
+
+ reset@e00 { // Reset module
+ compatible =3D "fsl,mpc5121-reset";
+ reg =3D <0xe00 0x100>;
+ };
+
+ clock@f00 { // Clock control
+ compatible =3D "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
+ reg =3D <0xf00 0x100>;
+ };
+
+ pmc@1000{ // Power Management Controller
+ compatible =3D "fsl,mpc5121-pmc";
+ reg =3D <0x1000 0x100>;
+ interrupts =3D <83 0x2>;
+ };
+
+ gpio@1100 {
+ compatible =3D "fsl,mpc5125-gpio";
+ cell-index =3D <0>;
+ reg =3D <0x1100 0x080>;
+ interrupts =3D <78 0x8>;
+ };
+
+ gpio@1180 {
+ compatible =3D "fsl,mpc5125-gpio1";
+ cell-index =3D <1>;
+ reg =3D <0x1180 0x080>;
+ interrupts =3D <78 0x8>;
+ };
+
+ can@1300 { // CAN rev.2
+ compatible =3D "fsl,mpc5121-mscan";
+ cell-index =3D <0>;
+ interrupts =3D <12 0x8>;
+ reg =3D <0x1300 0x80>;
+ };
+
+ can@1380 {
+ compatible =3D "fsl,mpc5121-mscan";
+ cell-index =3D <1>;
+ interrupts =3D <13 0x8>;
+ reg =3D <0x1380 0x80>;
+ };
+
+ sdhc@1500 {
+ compatible =3D "fsl,mpc5125-sdhc";
+ interrupts =3D <8 0x8>;
+ reg =3D <0x1500 0x100>;
+ };
+
+ i2c@1700 {
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ compatible =3D "fsl-i2c";
+ cell-index =3D <0>;
+ reg =3D <0x1700 0x20>;
+ interrupts =3D <0x9 0x8>;
+ fsl5200-clocking;
+ };
+
+ i2c@1720 {
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ compatible =3D "fsl-i2c";
+ cell-index =3D <1>;
+ reg =3D <0x1720 0x20>;
+ interrupts =3D <0xa 0x8>;
+ fsl5200-clocking;
+ };
+
+ i2c@1740 {
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ compatible =3D "fsl-i2c";
+ cell-index =3D <2>;
+ reg =3D <0x1740 0x20>;
+ interrupts =3D <0xb 0x8>;
+ fsl5200-clocking;
+ };
+
+ i2ccontrol@1760 {
+ compatible =3D "fsl,mpc5121-i2c-ctrl";
+ reg =3D <0x1760 0x8>;
+ };
+
+ //diu@2100 {
+ // device_type =3D "display";
+ // compatible =3D "fsl-diu";
+ // reg =3D <0x2100 0x100>;
+ // interrupts =3D <64 0x8>;
+ //};
+
+ // MPC5125e has two more CAN ports
+ // but they are not used on ADS5125
+ //can@2300 {
+ // compatible =3D "fsl,mpc5121-mscan";
+ // cell-index =3D <2>;
+ // interrupts =3D <90 0x8>;
+ // reg =3D <0x2300 0x80>;
+ //};
+
+ //can@2380 {
+ // compatible =3D "fsl,mpc5121-mscan";
+ // cell-index =3D <3>;
+ // interrupts =3D <91 0x8>;
+ // reg =3D <0x2380 0x80>;
+ //};
+
+ mdio@2800 {
+ compatible =3D "fsl,mpc5121-fec-mdio";
+ reg =3D <0x2800 0x800>;
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ phy0: ethernet-phy@0 {
+ reg =3D <1>;
+ device_type =3D "ethernet-phy";
+ };
+ };
+
+ ethernet@2800 {
+ compatible =3D "fsl,mpc5121-fec";
+ reg =3D <0x2800 0x800>;
+ local-mac-address =3D [ 00 00 00 00 00 00 ];
+ interrupts =3D <4 0x8>;
+ phy-handle =3D < &phy0 >;
+ };
+
+ // USB ULPI1
+ //usb@3000 {
+ // device_type =3D "usb";
+ // compatible =3D "fsl-usb2-dr";
+ // reg =3D <0x3000 0x400>;
+ // #address-cells =3D <1>;
+ // #size-cells =3D <0>;
+ // interrupts =3D <43 0x8>;
+ // dr_mode =3D "host";
+ // phy_type =3D "ulpi";
+ // big-endian-regs;
+ //};
+
+ // USB ULPI2
+ //usb@4000 {
+ // device_type =3D "usb";
+ // compatible =3D "fsl-usb2-dr";
+ // reg =3D <0x4000 0x400>;
+ // #address-cells =3D <1>;
+ // #size-cells =3D <0>;
+ // interrupts =3D <44 0x8>;
+ // dr_mode =3D "otg";
+ // phy_type =3D "ulpi";
+ // big-endian-regs;
+ //};
+
+ mdio@4800 {
+ compatible =3D "fsl,mpc5121-fec-mdio";
+ reg =3D <0x4800 0x800>;
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ phy1: ethernet-phy@0 {
+ reg =3D <1>;
+ device_type =3D "ethernet-phy";
+ };
+ };
+
+ ethernet@4800 {
+ compatible =3D "fsl,mpc5121-fec";
+ reg =3D <0x4800 0x800>;
+ local-mac-address =3D [ 00 00 00 00 00 00 ];
+ interrupts =3D <5 0x8>;
+ phy-handle =3D < &phy1 >;
+ };
+
+ // IO control
+ ioctl@a000 {
+ compatible =3D "fsl,mpc5125-ioctl";
+ reg =3D <0xA000 0x1000>;
+ };
+
+ // PSC0 in ac97 mode
+ //ac97@11000 {
+ // device_type =3D "sound";
+ // compatible =3D "fsl,mpc5125-psc-ac97", "fsl,mpc5125-psc";
+ // cell-index =3D <0>;
+ // reg =3D <0x11000 0x100>;
+ // interrupts =3D <40 0x8>;
+ // fsl,mode =3D "ac97-slave";
+ // rx-fifo-size =3D <384>;
+ // tx-fifo-size =3D <384>;
+ //};
+
+ // 5125 PSCs are not 52xx or 5121 PSC compatible
+ // PSC1 uart0 aka ttyPSC0
+ serial@11100 {
+ device_type =3D "serial";
+ compatible =3D "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
+ port-number =3D <0>;
+ cell-index =3D <1>;
+ reg =3D <0x11100 0x100>;
+ interrupts =3D <40 0x8 71 0x8>;
+ fsl,rx-fifo-size =3D <16>;
+ fsl,tx-fifo-size =3D <16>;
+ nodcd;
+ };
+
+ // PSC9 uart1 aka ttyPSC1
+ serial@11900 {
+ device_type =3D "serial";
+ compatible =3D "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
+ port-number =3D <1>;
+ cell-index =3D <9>;
+ reg =3D <0x11900 0x100>;
+ interrupts =3D <40 0x8 32 0x8>;
+ fsl,rx-fifo-size =3D <16>;
+ fsl,tx-fifo-size =3D <16>;
+ nodcd;
+ };
+
+ pscfifo@11f00 {
+ compatible =3D "fsl,mpc5121-psc-fifo";
+ reg =3D <0x11f00 0x100>;
+ interrupts =3D <40 0x8>;
+ };
+
+ dma@14000 {
+ compatible =3D "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2"
+ reg =3D <0x14000 0x1800>;
+ interrupts =3D <65 0x8>;
+ };
+ };
+};

(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/Kconfig
index 27b0651..0dde4b0 100644

arch/powerpc/platforms/512x/Kconfig +14 -0
@@ -26,6 +26,20 @@ config MPC5121_GENERIC
 	  Compatible boards include:  Protonic LVT base boards (ZANMCU
 	  and VICVT2).
 
+config PPC_MPC5125
+	bool "Generic support for MPC5125 based boards"
+	depends on PPC_MPC512x
+	select DEFAULT_UIMAGE
+	select PPC_INDIRECT_PCI
+	default n
+
+config MPC5125_TWR
+	bool "Freescale MPC5125 Tower system"
+	depends on PPC_MPC512x
+	select PPC_MPC5125
+	help
+	  This option enables support for the MPC5125 TWR board.
+
 config PDM360NG
 	bool "ifm PDM360NG board"
 	depends on PPC_MPC512x
(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/Makefile
index 4efc1c4..5c17561 100644

arch/powerpc/platforms/512x/Makefile +1 -0
@@ -5,3 +5,4 @@ obj-y				+=3D clock.o mpc512x_shared.o
 obj-$(CONFIG_MPC5121_ADS)	+=3D mpc5121_ads.o mpc5121_ads_cpld.o
 obj-$(CONFIG_MPC5121_GENERIC)	+=3D mpc5121_generic.o
 obj-$(CONFIG_PDM360NG)		+=3D pdm360ng.o
+obj-$(CONFIG_MPC5125_TWR)	+=3D mpc5125_twr.o
(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/clock.c
index 3dc2a8d..07e0bc0 100644

arch/powerpc/platforms/512x/clock.c +8 -1
@@ -27,6 +27,8 @@
 #include <asm/mpc5xxx.h>
 #include <asm/clk_interface.h>
 
+#include "mpc512x.h"
+
 #undef CLK_DEBUG
 
 static int clocks_initialized;

@@ -679,8 +681,13 @@ static void psc_clks_init(void)
 	struct device_node *np;
 	const u32 *cell_index;
 	struct platform_device *ofdev;
+	char *psc_compat;
+
+	psc_compat =3D mpc512x_select_psc_compat();
+	if (!psc_compat)
+		return;
 
-	for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+	for_each_compatible_node(np, NULL, psc_compat) {
 		cell_index =3D of_get_property(np, "cell-index", NULL);
 		if (cell_index) {
 			int pscnum =3D *cell_index;
(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/mpc5125_twr.c
new file mode 100644
index 0000000..7c7facf

arch/powerpc/platforms/512x/mpc5125_twr.c new file +49 -0

49 lines not on this page · raw message

/
+#define IOCTL_FEC2_MODE 0x43 /* FUNCMUX=3D2, PUD=3D0, PUE=3D0, DS=3D3 */
+
+/* Select mode of USB1 pads.
+ * They could be configured as USB (default), FEC2
+ * and several PSC's and/or GPIO's.
+ * Board specific. It can be platform specific in the future.
+ */
+static void mpc5125_twr_fec2_usb_iopad_init(void __iomem *ioctl, int isusb= )
+{
+ int i;
+ const u8 offset[12] =3D {
+ IOCTL_USB1_DATA0, IOCTL_USB1_DATA1,
+ IOCTL_USB1_DATA2, IOCTL_USB1_DATA3,
+ IOCTL_USB1_DATA4, IOCTL_USB1_DATA5,
+ IOCTL_USB1_DATA6, IOCTL_USB1_DATA7,
+ IOCTL_USB1_STOP, IOCTL_USB1_CLK,
+ IOCTL_USB1_NEXT, IOCTL_USB1_DIR
+ };
+ u8 mode;
+
+ mode =3D (isusb) ? IOCTL_DEFAULT_MODE : IOCTL_FEC2_MODE;
+ for (i =3D 0; i < ARRAY_SIZE(offset); i++)
+ out_8(ioctl + offset[i], mode);
+}
+
+static void __init mpc5125_twr_setup_arch(void)
+{
+ struct device_node *np;
+
+ printk(KERN_INFO "TWR-MPC5125 board from Freescale Semiconductor\n");
+
+ /*
+ * io pad config
+ */
+ np =3D of_find_compatible_node(NULL, NULL, "fsl,mpc5125-ioctl");
+ if (np) {
+ void __iomem *ioctl =3D of_iomap(np, 0);
+
+ mpc5125_twr_fec2_usb_iopad_init(ioctl, 0);
+
+ of_node_put(np);
+ iounmap(ioctl);
+ }
+}
+
+static struct of_device_id __initdata of_bus_ids[] =3D {
+ { .name =3D "soc", },
+ {},
+};
+
+static void __init mpc5125_twr_declare_of_platform_devices(void) +{
+ struct device_node *np;
+
+ if (of_platform_bus_probe(NULL, of_bus_ids, NULL))
+ printk(KERN_ERR __FILE__ ": "
+ "Error while probing of_platform bus\n");
+
+ np =3D of_find_compatible_node(NULL, NULL, "fsl,mpc5125-nfc");
+ if (np) {
+ of_platform_device_create(np, NULL, NULL);
+ of_node_put(np);
+ }
+}
+
+static void __init mpc5125_twr_init(void)
+{
+ mpc5125_twr_declare_of_platform_devices();
+ mpc5121_clk_init();
+ mpc512x_restart_init();
+ mpc512x_psc_fifo_init();
+}
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init mpc5125_twr_probe(void)
+{
+ unsigned long root =3D of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "fsl,mpc5125ads");
+}
+
+define_machine(mpc5125_twr) {
+ .name =3D "TWR-MPC5125",
+ .probe =3D mpc5125_twr_probe,
+ .setup_arch =3D mpc5125_twr_setup_arch,
+ .init =3D mpc5125_twr_init,
+ .init_IRQ =3D mpc512x_init_IRQ,
+ .get_irq =3D ipic_get_irq,
+ .calibrate_decr =3D generic_calibrate_decr,
+ .restart =3D mpc512x_restart,
+};

(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/mpc512x.h
index 1ab6d11..91c903f 100644

arch/powerpc/platforms/512x/mpc512x.h +4 -1
@@ -13,8 +13,11 @@
 #define __MPC512X_H__
 extern void __init mpc512x_init_IRQ(void);
 extern void __init mpc512x_init(void);
+extern void __init mpc512x_restart_init(void);
 extern int __init mpc5121_clk_init(void);
-void __init mpc512x_declare_of_platform_devices(void);
+extern void __init mpc512x_declare_of_platform_devices(void);
+extern void __init mpc512x_psc_fifo_init(void);
+extern char *mpc512x_select_psc_compat(void);
 extern void mpc512x_restart(char *cmd);
 extern void mpc512x_init_diu(void);
 extern void mpc512x_setup_diu(void);
(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/mpc512x_shared.c
index e41ebbd..e79d8ae 100644

arch/powerpc/platforms/512x/mpc512x_shared.c +24 -2
@@ -32,7 +32,7 @@
 
 static struct mpc512x_reset_module __iomem *reset_module_base;
 
-static void __init mpc512x_restart_init(void)
+void __init mpc512x_restart_init(void)
 {
 	struct device_node *np;
 

@@ -382,6 +382,21 @@ void __init mpc512x_declare_of_platform_devices(void)
 
 #define DEFAULT_FIFO_SIZE 16
 
+char *mpc512x_select_psc_compat(void)
+{
+	char *psc_compats[] =3D {
+		"fsl,mpc5121-psc",
+		"fsl,mpc5125-psc"
+	};
+	int i;
+
+	for (i =3D 0; i < ARRAY_SIZE(psc_compats); i++)
+		if (of_find_compatible_node(NULL, NULL, psc_compats[i]))
+			return psc_compats[i];
+
+	return NULL;
+}
+
 static unsigned int __init get_fifo_size(struct device_node *np,
 					 char *prop_name)
 {

@@ -407,9 +422,16 @@ void __init mpc512x_psc_fifo_init(void)
 	void __iomem *psc;
 	unsigned int tx_fifo_size;
 	unsigned int rx_fifo_size;
+	char *psc_compat;
 	int fifobase =3D 0; /* current fifo address in 32 bit words */
 
-	for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+	psc_compat =3D mpc512x_select_psc_compat();
+	if (!psc_compat) {
+		pr_err("%s: no compatible devices found\n", __func__);
+		return;
+	}
+
+	for_each_compatible_node(np, NULL, psc_compat) {
 		tx_fifo_size =3D get_fifo_size(np, "fsl,tx-fifo-size");
 		rx_fifo_size =3D get_fifo_size(np, "fsl,rx-fifo-size");

2011/3/18 Wolfram Sang <[email protected]>:

Quoted 11 lines · On Fri, Mar 18, 2011 at 02:35:24PM +0300, [email protected] wrote:
Quoted 10 lines
arch/powerpc/platforms/512x/clock.c +0 -0
index 3dc2a8d..5cadf8e 100644
@@ -606,6 +606,21 @@ static void rate_clks_init(void)

=C2=A0 */
=C2=A0struct clk dev_clks[2][32];

Quoted 10 lines

arch/powerpc/platforms/512x/clock.c

Quoted 10 lines
arch/powerpc/platforms/512x/clock.c +10 -0
+char *mpc512x_select_psc_compat(void)
+{
+ =C2=A0 =C2=A0 char *psc_compats[] =3D {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "fsl,mpc5121-psc",
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "fsl,mpc5125-psc"
+ =C2=A0 =C2=A0 };
+ =C2=A0 =C2=A0 int i;
+
+ =C2=A0 =C2=A0 for (i =3D 0; i < ARRAY_SIZE(psc_compats); i++)
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (of_find_compatible_node(=

NULL, NULL, psc_compats[i]))

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

return psc_compats[i];

Quoted 10 lines

arch/powerpc/platforms/512x/clock.c

Quoted 3 lines
arch/powerpc/platforms/512x/clock.c +3 -0
+
+ =C2=A0 =C2=A0 return NULL;
+}

Function looks good to me. Shouldn't that rather be in mpc512x_shared?

Quoted 1 line

+// IOCTL registers for USB1/FEC2

No c++-style comments, please (here and later).

Quoted 17 lines

arch/powerpc/platforms/512x/clock.c

Quoted 11 lines
arch/powerpc/platforms/512x/clock.c +11 -0
+static void mpc5125_psc_iopad_init(void __iomem *ioctl, char *name)
+{
+ =C2=A0 =C2=A0 struct device_node *np;
+ =C2=A0 =C2=A0 const u32 *cell_index;
+ =C2=A0 =C2=A0 char *default_psc =3D "fsl,mpc5125-psc";
+ =C2=A0 =C2=A0 char *psc_name;
+
+ =C2=A0 =C2=A0 if (name)
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 psc_name =3D name;
+ =C2=A0 =C2=A0 else
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 psc_name =3D default_psc;

Caller sets name to NULL. Is this really used?

Quoted 3 lines

+
+ =C2=A0 =C2=A0 for_each_compatible_node(np, NULL, psc_name) {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cell_index =3D of_get_proper=

ty(np, "cell-index", NULL);

Quoted 5 lines

I seem to recall 'cell-index' is deprecated. Grant?

Quoted 2 lines

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (cell_index) {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

u8 __iomem *pscioctl;

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

int psc_num =3D *cell_index;

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

if (psc_num > 1)

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

=C2=A0 =C2=A0 =C2=A0 =C2=A0 continue;

Quoted 2 lines
Quoted 2 lines

+
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

pscioctl =3D ioctl + PSC_TO_IOCTL_OFFSET(psc_num);

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

out_8(pscioctl + IOCTL_PSCx_0, IOCTL_PSCx_0_MODE); // NOTE maybe wrong

Quoted 4 lines

Why is it 'maybe wrong'? Can it be improved somehow?

Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

out_8(pscioctl + IOCTL_PSCx_1, IOCTL_DEFAULT_MODE);

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

out_8(pscioctl + IOCTL_PSCx_2, IOCTL_DEFAULT_MODE);

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

out_8(pscioctl + IOCTL_PSCx_3, IOCTL_DEFAULT_MODE);

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

out_8(pscioctl + IOCTL_PSCx_4, IOCTL_DEFAULT_MODE);

Quoted 7 lines

The defines make it much more readable, thanks.

Quoted 3 lines

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+ =C2=A0 =C2=A0 }
+}

Quoted 8 lines

Is this function really board-specific or platform specific?

arch/powerpc/platforms/512x/clock.c

Quoted 5 lines
arch/powerpc/platforms/512x/clock.c +5 -0
+static void mpc5125_fec2_usb_io_init(void __iomem *ioctl, int isusb)
+{
+ =C2=A0 =C2=A0 int i;
+ =C2=A0 =C2=A0 const u8 offset[12] =3D {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 IOCTL_USB1_DATA0, IOCTL_USB1=

_DATA1,

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 IOCTL_USB1_DATA2, IOCTL_USB1=

_DATA3,

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 IOCTL_USB1_DATA4, IOCTL_USB1=

_DATA5,

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 IOCTL_USB1_DATA6, IOCTL_USB1=

_DATA7,

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 IOCTL_USB1_STOP, IOCTL_USB1_=

CLK,

Quoted 1 line
Quoted 1 line

+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 IOCTL_USB1_NEXT, IOCTL_USB1_=

DIR

Quoted 6 lines
Quoted 6 lines

+ =C2=A0 =C2=A0 };
+ =C2=A0 =C2=A0 u8 mode;
+
+ =C2=A0 =C2=A0 mode =3D (isusb) ? IOCTL_DEFAULT_MODE : IOCTL_FEC2_MODE;
+ =C2=A0 =C2=A0 for (i =3D 0; i < ARRAY_SIZE(offset); i++)
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 out_8(ioctl + offset[i], mod=

e);

Quoted 3 lines
Quoted 1 line

+}

Same question here and later. If it is board specific, the function name =

should

Quoted 9 lines

have something like 'twr' in it; but a few things seem mpc5125-generic to me, if I am not mistaken?

Regards,

=C2=A0 Wolfram

--
Pengutronix e.K. =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =

=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | Wolfram Sang =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|

Quoted 1 line

Industrial Linux Solutions =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=

=A0 =C2=A0 | http://www.pengutronix.de/ =C2=A0|

Quoted 10 lines

-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)

iEYEARECAAYFAk2DUdUACgkQD27XaX1/VRtRhwCfU5saH7ThSl1WsdlSseySqvbF BFEAoKskDlkkz53myb4FpvOBlMdAtUS1
=3D554E
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author
#5 lore raw

Adds Freescale TWR-MPC5125 device tree and platform code.

Currently following is supported:
- NAND
- FEC1 and FEC2
- RTC
- PSC UART

NAND flash controller require more tests, so it will be later.

Signed-off-by Vladimir Ermakov <[email protected]>

---
v2:
- add PSC compat string selection
- add ioctl defines

v3:
- less verbose interrupt-parent
- move mpc512x_select_psc_compat() to mpc512x_shared.c
- remove unneded mpc5125_psc_iopad_init()
- fix board prefixes

v4:
- remove device_type from ethernet nodes
- add aliases for ethernet nodes
- add phy-connection-type
- extend size of rootfs partition

---
 arch/powerpc/boot/dts/mpc5125twr.dts         |  376 ++++++++++++++++++++++++++
 arch/powerpc/platforms/512x/Kconfig          |   14 +
 arch/powerpc/platforms/512x/Makefile         |    1 +
 arch/powerpc/platforms/512x/clock.c          |    9 +-
 arch/powerpc/platforms/512x/mpc5125_twr.c    |  142 ++++++++++
 arch/powerpc/platforms/512x/mpc512x.h        |    5 +-
 arch/powerpc/platforms/512x/mpc512x_shared.c |   26 ++-
 7 files changed, 569 insertions(+), 4 deletions(-)
(quoted diff) +0 -0

b/arch/powerpc/boot/dts/mpc5125twr.dts
new file mode 100644
index 0000000..ca3851d

arch/powerpc/boot/dts/mpc5125twr.dts new file +376 -0

376 lines not on this page · raw message

(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/Kconfig
index 27b0651..0dde4b0 100644

arch/powerpc/platforms/512x/Kconfig +14 -0
@@ -26,6 +26,20 @@ config MPC5121_GENERIC
 	  Compatible boards include:  Protonic LVT base boards (ZANMCU
 	  and VICVT2).
 
+config PPC_MPC5125
+	bool "Generic support for MPC5125 based boards"
+	depends on PPC_MPC512x
+	select DEFAULT_UIMAGE
+	select PPC_INDIRECT_PCI
+	default n
+
+config MPC5125_TWR
+	bool "Freescale MPC5125 Tower system"
+	depends on PPC_MPC512x
+	select PPC_MPC5125
+	help
+	  This option enables support for the MPC5125 TWR board.
+
 config PDM360NG
 	bool "ifm PDM360NG board"
 	depends on PPC_MPC512x
(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/Makefile
index 4efc1c4..5c17561 100644

arch/powerpc/platforms/512x/Makefile +1 -0
@@ -5,3 +5,4 @@ obj-y				+= clock.o mpc512x_shared.o
 obj-$(CONFIG_MPC5121_ADS)	+= mpc5121_ads.o mpc5121_ads_cpld.o
 obj-$(CONFIG_MPC5121_GENERIC)	+= mpc5121_generic.o
 obj-$(CONFIG_PDM360NG)		+= pdm360ng.o
+obj-$(CONFIG_MPC5125_TWR)	+= mpc5125_twr.o
(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/clock.c
index 3dc2a8d..07e0bc0 100644

arch/powerpc/platforms/512x/clock.c +8 -1
@@ -27,6 +27,8 @@
 #include <asm/mpc5xxx.h>
 #include <asm/clk_interface.h>
 
+#include "mpc512x.h"
+
 #undef CLK_DEBUG
 
 static int clocks_initialized;

@@ -679,8 +681,13 @@ static void psc_clks_init(void)
 	struct device_node *np;
 	const u32 *cell_index;
 	struct platform_device *ofdev;
+	char *psc_compat;
+
+	psc_compat = mpc512x_select_psc_compat();
+	if (!psc_compat)
+		return;
 
-	for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+	for_each_compatible_node(np, NULL, psc_compat) {
 		cell_index = of_get_property(np, "cell-index", NULL);
 		if (cell_index) {
 			int pscnum = *cell_index;
(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/mpc5125_twr.c
new file mode 100644
index 0000000..7c7facf

arch/powerpc/platforms/512x/mpc5125_twr.c new file +142 -0

142 lines not on this page · raw message

(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/mpc512x.h
index 1ab6d11..91c903f 100644

arch/powerpc/platforms/512x/mpc512x.h +4 -1
@@ -13,8 +13,11 @@
 #define __MPC512X_H__
 extern void __init mpc512x_init_IRQ(void);
 extern void __init mpc512x_init(void);
+extern void __init mpc512x_restart_init(void);
 extern int __init mpc5121_clk_init(void);
-void __init mpc512x_declare_of_platform_devices(void);
+extern void __init mpc512x_declare_of_platform_devices(void);
+extern void __init mpc512x_psc_fifo_init(void);
+extern char *mpc512x_select_psc_compat(void);
 extern void mpc512x_restart(char *cmd);
 extern void mpc512x_init_diu(void);
 extern void mpc512x_setup_diu(void);
(quoted diff) +0 -0

b/arch/powerpc/platforms/512x/mpc512x_shared.c
index e41ebbd..e79d8ae 100644

arch/powerpc/platforms/512x/mpc512x_shared.c +24 -2
@@ -32,7 +32,7 @@
 
 static struct mpc512x_reset_module __iomem *reset_module_base;
 
-static void __init mpc512x_restart_init(void)
+void __init mpc512x_restart_init(void)
 {
 	struct device_node *np;
 

@@ -382,6 +382,21 @@ void __init mpc512x_declare_of_platform_devices(void)
 
 #define DEFAULT_FIFO_SIZE 16
 
+char *mpc512x_select_psc_compat(void)
+{
+	char *psc_compats[] = {
+		"fsl,mpc5121-psc",
+		"fsl,mpc5125-psc"
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(psc_compats); i++)
+		if (of_find_compatible_node(NULL, NULL, psc_compats[i]))
+			return psc_compats[i];
+
+	return NULL;
+}
+
 static unsigned int __init get_fifo_size(struct device_node *np,
 					 char *prop_name)
 {

@@ -407,9 +422,16 @@ void __init mpc512x_psc_fifo_init(void)
 	void __iomem *psc;
 	unsigned int tx_fifo_size;
 	unsigned int rx_fifo_size;
+	char *psc_compat;
 	int fifobase = 0; /* current fifo address in 32 bit words */
 
-	for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+	psc_compat = mpc512x_select_psc_compat();
+	if (!psc_compat) {
+		pr_err("%s: no compatible devices found\n", __func__);
+		return;
+	}
+
+	for_each_compatible_node(np, NULL, psc_compat) {
 		tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size");
 		rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size");
Signature · 1 line
1.7.1