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mtd/nand: Add initial support for TWR-MPC5125

PATCH In review Vladimir Ermakov 1 participant 1 message Mar 16, 2011

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PATCH 4/4 mtd/nand: Add initial support for TWR-MPC5125

Adds NAND Flash Controller driver for MPC5125. Also adds chip id for Micron's NAND used in TWR-MPC5125.

Driver ported from original Freescale BSP (kernel 2.6.29.1).

---

drivers/mtd/nand/Kconfig +20 -0
index a92054e..eb660a8 100644
@@ -472,6 +472,26 @@ config MTD_NAND_MPC5121_NFC
 	  This enables the driver for the NAND flash controller on the
 	  MPC5121 SoC.
 
+config MTD_NAND_MPC5125_NFC
+	tristate "MPC5125 built-in NAND Flash Controller support"
+	depends on PPC_MPC512x
+	help
+	  This enables the driver for the NAND flash controller on the
+	  MPC5125 SoC.
+
+config MTD_NAND_MPC5125_HWECC
+	bool "Enable hardware ECC"
+	depends on MTD_NAND_MPC5125_NFC
+	help
+	  This enables the support for Software ECC handling. By
+	  default FSL NAND controller Hardware ECC is supported.
+
+config NFC_DMA_ENABLE
+	bool "Enable NAND Flash DMA"
+	depends on MTD_NAND_MPC5125_NFC
+	help
+	  This enables the nfc dma support
+
 config MTD_NAND_MXC
 	tristate "MXC NAND support"
 	depends on IMX_HAVE_PLATFORM_MXC_NAND
drivers/mtd/nand/Makefile +1 -0
index 5745d83..bd354cd 100644
@@ -47,6 +47,7 @@ obj-$(CONFIG_MTD_NAND_NUC900)		+= nuc900_nand.o
 obj-$(CONFIG_MTD_NAND_NOMADIK)		+= nomadik_nand.o
 obj-$(CONFIG_MTD_NAND_BCM_UMI)		+= bcm_umi_nand.o nand_bcm_umi.o
 obj-$(CONFIG_MTD_NAND_MPC5121_NFC)	+= mpc5121_nfc.o
+obj-$(CONFIG_MTD_NAND_MPC5125_NFC)	+= mpc5125_nfc.o
 obj-$(CONFIG_MTD_NAND_RICOH)		+= r852.o
 obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740_nand.o
 
drivers/mtd/nand/mpc5125_nfc.c new file +1290 -0

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drivers/mtd/nand/mpc5125_nfc.h new file +293 -0

293 lines not on this page · raw message

drivers/mtd/nand/nand_ids.c +2 -0
index 00cf1b0..6755191 100644
@@ -66,6 +66,8 @@ struct nand_flash_dev nand_flash_ids[] = {
 
 	{"NAND 256MiB 3,3V 8-bit",	0x71, 512, 256, 0x4000, 0},
 
+	{"NAND 4GiB 3,3V 8-bit",	0x68, 4096, 4096, 0x100000, 0},
+
 	/*
 	 * These are the new chips with large page size. The pagesize and the
 	 * erasesize is determined from the extended id bytes