Support for NXP LPC2K SoCs

Core files (including IRQ handling) for NXP LPC2K architecture.

Signed-off-by Ithamar R. Adema <[email protected]>

---

arch/arm/mach-lpc2k/include/mach/entry-macro.S new file +22 -0

new file mode 100644
index 0000000..f6c7a46
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2011 Team Embedded VOF
+ *     Ithamar R. Adema <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/hardware.h>
+
+        .macro  disable_fiq
+        .endm
+
+		.macro	get_irqnr_preamble, base, tmp
+		ldr	\base, =APH_VIC_BASE
+		.endm
+
+		.macro	arch_ret_to_user, tmp1, tmp2
+		.endm
+
+		.macro get_irqnr_and_base, irqnr, irqstat, base, tmp

Core files (including IRQ handling) for NXP LPC2K architecture.

arch/arm/Kconfig +0 -0

index e34bf02..331540d 100644
@@ -490,6 +490,18 @@ config ARCH_LOKI

? ? ? ?help
? ? ? ? ?Support for the Marvell Loki (88RC8480) SoC.

arch/arm/Kconfig +12 -0

+config ARCH_LPC2K
+ ? ? ? bool "NXP LPC2K Family"
+ ? ? ? depends on !MMU
+ ? ? ? select CPU_ARM7TDMI
+ ? ? ? select ARM_VIC
+ ? ? ? select GENERIC_TIME
+ ? ? ? select GENERIC_CLOCKEVENTS
+ ? ? ? help
+ ? ? ? ? Support for NXP LPC2K family of SoCs. These SoCs are based on
+ ? ? ? ? an ARM7TDMI-S core, and have optional on-chip flash and SRAM,
+ ? ? ? ? also UART, I2C, SPI, SSP, CAN, RTC, and other peripherals.
+

?config ARCH_LPC32XX
? ? ? ?bool "NXP LPC32XX"
? ? ? ?select CPU_ARM926T

arch/arm/Kconfig +0 -0

@@ -928,6 +940,8 @@ source "arch/arm/mach-ks8695/Kconfig"
 

?source "arch/arm/mach-loki/Kconfig"

is there any good reason why you don't add your stuff to lpc32xx?

arch/arm/mach- renamed from arch/arm/mach-lpc2k/include/mach/system.h +0 -0

lpc2k/include/mach/system.h
new file mode 100644
index 0000000..fbbea43

arch/arm/mach-lpc2k/include/mach/system.h new file +6 -0

@@ -0,0 +1,23 @@
+/*
+ * Copyright 2011 Team Embedded VOF
+ *     Ithamar R. Adema <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as

arch/arm/mach-lpc2k/include/mach/system.h line 16

Quoted 4 lines

arch/arm/mach-lpc2k/include/mach/system.h new file +4 -0

+static void arch_idle(void)
+{
+	cpu_do_idle();
+}

The 24xx devices have a CPU idle down register (PCON) that will suspend the CPU clock until the next interrupt. *pcon = 1;

arch/arm/mach-lpc2k/include/mach/system.h line 21

Quoted 5 lines

arch/arm/mach-lpc2k/include/mach/system.h new file +5 -0

+
+static inline void arch_reset(char mode, const char *cmd)
+{
+	cpu_reset(0);
+}

The entire system can be reset via RESETOUT using the watchdog timer.

Since the LPC2K does not have an MMU (ARM7TDMI based), it expects the vectors to be stored in on-chip SRAM. However, this moves the vectors too far away from the stubs page, requiring the vector jumps to be indirect.

Since now VECTOR_BASE is below PHYS_OFFSET, do not try to reserve the vector page, as it will fail (and prevent the kernel from booting).

Also, commit 247055aa (6384/1: Remove the domain switching on ARMv6k/v7 CPUs) broke the placement of vectors in the !MMU case, so fix this too.

Signed-off-by Ithamar R. Adema <[email protected]>

---
 arch/arm/Kconfig             |    1 +
 arch/arm/kernel/entry-armv.S |   18 ++++++++++++++++++
 arch/arm/kernel/traps.c      |    2 +-
 arch/arm/mm/nommu.c          |    2 ++
 4 files changed, 22 insertions(+), 1 deletions(-)

arch/arm/Kconfig +1 -0

index 331540d..9c12d71 100644
@@ -186,6 +186,7 @@ config VECTORS_BASE
 	hex
 	default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 	default DRAM_BASE if REMAP_VECTORS_TO_RAM
+	default 0x40000000 if ARCH_LPC2K
 	default 0x00000000
 	help
 	  The base address of exception vectors.

arch/arm/kernel/entry-armv.S +1 -0

index e8d8856..618a971 100644
@@ -1208,6 +1208,7 @@ __stubs_end:
 
 	.globl	__vectors_start
 __vectors_start:
+#ifndef CONFIG_ARCH_LPC2K
  ARM(	swi	SYS_ERROR0	)
  THUMB(	svc	#0		)
  THUMB(	nop			)

arch/arm/kernel/entry-armv.S +15 -0

+	ldr	pc, .vector_und
+	ldr	pc, .vector_swi
+	ldr	pc, .vector_pabt
+	ldr	pc, .vector_dabt
+	ldr	pc, .vector_addrexcptn
+	ldr	pc, .vector_irq
+	ldr	pc, .vector_fiq
+.vector_und:		.word   vector_und
+.vector_swi:		.word   vector_swi
+.vector_pabt:		.word   vector_pabt
+.vector_dabt:		.word   vector_dabt
+.vector_addrexcptn:	.word   vector_addrexcptn
+.vector_irq:		.word   vector_irq
+.vector_fiq:		.word   vector_fiq
+#endif
 
 	.globl	__vectors_end
 __vectors_end:

arch/arm/kernel/traps.c +1 -1

index 21ac43f..639c4c8 100644
@@ -758,7 +758,7 @@ static void __init kuser_get_tls_init(unsigned long vectors)
 
 void __init early_trap_init(void)
 {
-#if defined(CONFIG_CPU_USE_DOMAINS)
+#if defined(CONFIG_CPU_USE_DOMAINS) || !defined(CONFIG_MMU)
 	unsigned long vectors = CONFIG_VECTORS_BASE;
 #else
 	unsigned long vectors = (unsigned long)vectors_page;

arch/arm/mm/nommu.c +2 -0

index 687d023..e3bec02 100644
@@ -24,7 +24,9 @@ void __init arm_mm_memblock_reserve(void)
 	 * some architectures which the DRAM is the exception vector to trap,
 	 * alloc_page breaks with error, although it is not NULL, but "0."
 	 */
+#if PHYS_OFFSET <= CONFIG_VECTORS_BASE
 	memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
+#endif
 }
 
 /*

Signature · 7 lines

1.7.1


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Quoted 6 lines · Ithamar R. Adema

arch/arm/kernel/entry-armv.S +0 -0

index e8d8856..618a971 100644
@@ -1208,6 +1208,7 @@ __stubs_end:
 

arch/arm/kernel/entry-armv.S __vectors_start: · line 1222

Quoted 11 lines

arch/arm/kernel/entry-armv.S +2 -0

 	.globl	__vectors_start
 __vectors_start:
+#ifndef CONFIG_ARCH_LPC2K
  ARM(	swi	SYS_ERROR0	)
  THUMB(	svc	#0		)
  THUMB(	nop			)

@@ -1218,6 +1219,23 @@ __vectors_start:
 	W(b)	vector_addrexcptn + stubs_offset
 	W(b)	vector_irq + stubs_offset
 	W(b)	vector_fiq + stubs_offset
+#else /* CONFIG_ARCH_LPC2K */

The description from the commit log should be repeated here.

And I wonder if this shouldn't depend on CONFIG_ARCH_LPC2K but CONFIG_MMU.

arch/arm/kernel/entry-armv.S __vectors_start: · line 1223

Quoted 1 line

arch/arm/kernel/entry-armv.S +1 -0

+	swi	SYS_ERROR0

I think arm7tdmi doesn't have thumb2, does it? If it has you need to do ARM(swi SYS_ERROR0)
THUMB(svc ..)
...

as above

Quoted 7 lines · Uwe Kleine-K??nig

Quoted 6 lines · Ithamar R. Adema

arch/arm/kernel/entry-armv.S +0 -0

index e8d8856..618a971 100644
@@ -1208,6 +1208,7 @@ __stubs_end:
 

Quoted 12 lines

arch/arm/kernel/entry-armv.S __vectors_start: · line 1222

Quoted 11 lines

arch/arm/kernel/entry-armv.S +2 -0

  	.globl	__vectors_start
  __vectors_start:
+#ifndef CONFIG_ARCH_LPC2K
   ARM(	swi	SYS_ERROR0	)
   THUMB(	svc	#0		)
   THUMB(	nop			)

@@ -1218,6 +1219,23 @@ __vectors_start:
  	W(b)	vector_addrexcptn + stubs_offset
  	W(b)	vector_irq + stubs_offset
  	W(b)	vector_fiq + stubs_offset
+#else /* CONFIG_ARCH_LPC2K */

The description from the commit log should be repeated here.

OK, will include the description as comment there in the next version.

Quoted 2 lines

And I wonder if this shouldn't depend on CONFIG_ARCH_LPC2K but CONFIG_MMU.

Well, looking at th uClinux kernel tree, it seems this was only done for the NXP LPC2K range, so that's why I kept it under CONFIG_ARCH_LPC2K.

Quoted 7 lines

arch/arm/kernel/entry-armv.S __vectors_start: · line 1223

Quoted 1 line

arch/arm/kernel/entry-armv.S +1 -0

+	swi	SYS_ERROR0

I think arm7tdmi doesn't have thumb2, does it? If it has you need to do ARM(swi SYS_ERROR0)
THUMB(svc ..)
...

as above

Correct, the ARM7TDMI-S only supports Thumb, not Thumb2.

Thanks for reviewing!

Ithamar.

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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

arch/arm/mach-lpc2k/clock.c new file +4 -0

+struct clk {
+	int		refcount;
+	struct clk	*parent;
+	unsigned long	rate;

(quoted diff) +5 -2

+
+/*-----------------------------------------------------------------------
--
+ * Standard clock functions defined in include/linux/clk.h
+ *-----------------------------------------------------------------------
--*/
+

Quoted 1 line

+static DEFINE_MUTEX(clocks_mutex);

I tried this lock mechanism and occasionally I get warnings when mutex checking is enabled and multiple calls occur to the clk_* functions with active clock management. Spinlocks might be better, but maybe some one else can chime in here.

arch/arm/mach-lpc2k/include/mach/regs-clock.h new file +9 -0

new file mode 100644
index 0000000..1c94582
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2011 Team Embedded VOF
+ *     Ithamar R. Adema <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+

arch/arm/mach-lpc2k/include/mach/regs-clock.h new file +1 -0

+#define PLLE		(1 << 24)

Quoted 20 lines

arch/arm/mach-lpc2k/include/mach/regs-clock.h new file +13 -0

new file mode 100644
index 0000000..1c94582
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2011 Team Embedded VOF
+ *     Ithamar R. Adema <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef MACH_LPC2K_REGS_CLOCK_H
+#define MACH_LPC2K_REGS_CLOCK_H
+
+#define CLKSRCSEL	0x10c

arch/arm/mach-lpc2k/include/mach/regs-clock.h line 19

Quoted 6 lines

arch/arm/mach-lpc2k/include/mach/regs-clock.h new file +6 -0

+#define CLKSRC(x)	((x) & 3)
+#define PLLCON		0x080
+#define PLLCFG		0x084
+#define PLLSTAT		0x088
+#define M(x)		(((x) & 0x7fff) + 1)
+#define N(x)		((((x) >> 16) & 0xf) + 1)

N has a field size of 8 bits? Mask should be 0xff

This code was mostly "borrowed" form the lpc32xx implementation.

Signed-off-by Ithamar R. Adema <[email protected]>

---
 arch/arm/mach-lpc2k/Makefile |    2 +-
 arch/arm/mach-lpc2k/time.c   |  174 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 175 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-lpc2k/time.c

arch/arm/mach-lpc2k/Makefile +1 -1

index 9eb0a6a..267432c 100644
@@ -1 +1 @@
-obj-y	:= clock.o irq.o
+obj-y	:= clock.o irq.o time.o

arch/arm/mach-lpc2k/time.c new file +94 -0

new file mode 100644
index 0000000..b430f7c
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2011 Team Embeded VOF
+ * Copyright (C) 2009 - 2010 NXP Semiconductors
+ * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
+ *                    Ed Schouten <[email protected]>
+ *                    Laurens Timmermans <[email protected]>
+ *
+ * Based on timer code from plat-lpc32xx.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/time.h>
+#include <linux/err.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+
+#define IR		0x00
+#define TCR		0x04
+#define TC		0x08
+#define PR		0x0c
+#define PC		0x10
+#define MCR		0x14
+#define MR0		0x18
+#define MR1		0x1c
+#define MR2		0x20
+#define CCR		0x28
+#define CR0		0x2c
+#define CR1		0x30
+#define CR2		0x34
+#define CR3		0x38
+#define EMR		0x3c
+#define CTCR		0x70
+
+#define IR_MR_SHIFT	0
+#define IR_CR_SHIFT	4
+
+#define TCR_EN		(1 << 0)
+#define TCR_RESET	(1 << 1)
+
+
+static void __iomem *timer0 = (void __iomem *)APB_TIMER0_BASE;
+static void __iomem *timer1 = (void __iomem *)APB_TIMER1_BASE;
+
+static cycle_t lpc2k_clksrc_read(struct clocksource *cs)
+{
+	return __raw_readl(timer1 + TC);
+}
+
+static struct clocksource lpc2k_clksrc = {
+	.name	= "lpc2k_clksrc",
+	.rating	= 300,
+	.read	= lpc2k_clksrc_read,
+	.mask	= CLOCKSOURCE_MASK(32),
+	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int lpc2k_clkevt_next_event(unsigned long delta,
+	struct clock_event_device *dev)
+{
+	__raw_writel(TCR_RESET, timer0 + TCR);
+	__raw_writel(delta, timer0 + PR);
+	__raw_writel(TCR_EN, timer0 + TCR);
+
+	return 0;
+}
+
+static void lpc2k_clkevt_mode(enum clock_event_mode mode,
+	struct clock_event_device *dev)
+{
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		BUG();
+		break;
+
+	case CLOCK_EVT_MODE_ONESHOT:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+		/*
+		 * Disable the timer. When using oneshot, we must also
+		 * disable the timer to wait for the first call to
+		 * set_next_event().
+		 */
+		__raw_writel(0, timer0 + TCR);
+		break;
+

arch/arm/mach-lpc2k/time.c new file +42 -0

+	.rating		= 300,
+	.set_next_event	= lpc2k_clkevt_next_event,
+	.set_mode	= lpc2k_clkevt_mode,
+};
+
+static irqreturn_t lpc2k_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = &lpc2k_clkevt;
+
+	/* Clear match */
+	__raw_writel((1 << IR_MR_SHIFT), timer0 + IR);
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction lpc2k_timer_irq = {
+	.name		= "LPC2K Timer Tick",
+	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+	.handler	= lpc2k_timer_interrupt,
+};
+
+/*
+ * The clock management driver isn't initialized at this point, so the
+ * clocks need to be enabled here manually and then tagged as used in
+ * the clock driver initialization
+ */
+static void __init lpc2k_timer_init(void)
+{
+	unsigned long rate;
+	struct clk *clk;
+
+	clk = clk_get(NULL, "timer1");
+	BUG_ON(IS_ERR(clk));
+
+	clk_enable(clk);
+	rate = clk_get_rate(clk);
+	clk_put(clk);
+
+	/* Initial timer setup */
+	__raw_writel(0, timer0 + TCR);

arch/arm/mach-lpc2k/time.c new file +18 -1

+	lpc2k_clkevt.max_delta_ns = clockevent_delta2ns(-1,
+		&lpc2k_clkevt);
+	lpc2k_clkevt.min_delta_ns = clockevent_delta2ns(1,
+		&lpc2k_clkevt) + 1;
+	lpc2k_clkevt.cpumask = cpumask_of(0);
+	clockevents_register_device(&lpc2k_clkevt);
+
+	/* Use timer1 as clock source. */
+	__raw_writel(TCR_RESET, timer1 + TCR);
+	__raw_writel(0, timer1 + PR);
+	__raw_writel(0, timer1 + MCR);
+	__raw_writel(TCR_EN, timer1 + TCR);
+	clocksource_register_hz(&lpc2k_clksrc, rate);
+}
+
+struct sys_timer lpc2k_timer = {
+	.init		= &lpc2k_timer_init,
+};
-- 1.7.1

One pedantic nitpick, but otherwise looks nice to me.

arch/arm/mach-lpc2k/time.c line 104

Quoted 4 lines

arch/arm/mach-lpc2k/time.c new file +4 -0

+static struct clock_event_device lpc2k_clkevt = {
+	.name		= "lpc2k_clkevt",
+	.features	= CLOCK_EVT_FEAT_ONESHOT,
+	.shift		= 32,

You shouldn't need to specify a shift if you use clockevents_calc_mult_shift() and let the core code calculate mult and shift for you.

arch/arm/mach-lpc2k/mach-lpc2478oem.c new file +4 -1

+	.init_irq	= lpc2478oem_init_irq,
+	.timer		= &lpc2k_timer,
+	.init_machine	= lpc2478oem_init_machine,
+MACHINE_END
--

1.7.1

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arch/arm/mach-lpc2k/mach-lpc2478oem.c line 23

Quoted 4 lines

arch/arm/mach-lpc2k/mach-lpc2478oem.c new file +4 -0

+
+#define EXTPOLAR	0x14c
+
+static unsigned long mfp_cfgs[] = {

Should this be initdata?

Quoted 1 line

+MACHINE_START(LPC2478OEM, "Embedded Artists LPC2478 OEM Board")

Just a nit, but the machine ID should probably be unique to this board and not the 2478, ie EA2478OEM. If someone else releases a LPC2478 based board, it can't use this same id. This would apply to the filename too (lpc2478oem.c) - the name is somewhat generic and might be better named something like plat-ea2478oem.c.

arch/arm/mach-lpc2k/mach-lpc2478oem.c new file +3 -0

+static void __init lpc2478oem_init_irq(void)
+{
+	/* XXX workaround for the fact that EINT3 is connected to high-

active

(quoted diff) +1 -0

+	 * signal, but can't be disabled. As the EINT3 interrupt is also

used

arch/arm/mach-lpc2k/mach-lpc2478oem.c new file +7 -0

+}
+
+MACHINE_START(LPC2478OEM, "Embedded Artists LPC2478 OEM Board")
+	.init_irq	= lpc2478oem_init_irq,
+	.timer		= &lpc2k_timer,
+	.init_machine	= lpc2478oem_init_machine,
+MACHINE_END

Quoted 1 line

+ lpc2k_init_clocks(12000000UL, 32768000UL);

Should the RTC clock be 32768?

Subject: [PATCH 0/9] Support for NXP LPC2K SoCs

The following patch series implements support for the ARM7TDMI-S based NXP LPC2K System-on-Chips, and, as first board, the EmbeddedArtists LPC2478 Developer's Kit.

This code will work on the LPC23XX and LPC24XX ranges of chips, but will need some more work for LPC21XX and LPC22XX chips.

The following patch series implements support for the ARM7TDMI-S based NXP LPC2K System-on-Chips, and, as first board, the EmbeddedArtists LPC2478 Developer's Kit.

This code will work on the LPC23XX and LPC24XX ranges of chips, but will need some more work for LPC21XX and LPC22XX chips.