x86/mrst: move sfi timer irqs after gsi_top
PATCH 1/1 x86/mrst: move sfi timer irqs after gsi_top
Moorestown borrows mp_irqs for its early SFI device IRQs, it used to be 1:1 mapped between irq # and ioapic pin#. After gsi_top is introduced, we have to allocate irqs on top of gsi_top since below that irqs are not set to ioapic chip whereas Moorestown SFI device irqs are all routed via ioapic chip.
Without this fix, Moorestown fails to boot at secondary clock setup since it cannot do request_irq on cpu 1 timer which does not have a valid irq_chip.
Also use correct MP configuration table entry type INTSRC, which is used for IO interrupt assignment.
--- arch/x86/kernel/apb_timer.c | 2 +- arch/x86/platform/mrst/mrst.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)
arch/x86/kernel/apb_timer.c +1 -1
@@ -630,7 +630,7 @@ void __init apbt_time_init(void) p_mtmr =sfi_get_mtmr (i);if (p_mtmr) { adev->tick = p_mtmr->freq_hz; - adev->irq = p_mtmr->irq; + adev->irq = p_mtmr->irq + gsi_top; }else printk (KERN_ERR "Failed to get timer for cpu %d\n" , i); adev->count =0 ;
arch/x86/platform/mrst/mrst.c +2 -2
@@ -97,12 +97,12 @@ static int __init sfi_parse_mtmr(struct sfi_table_header *table) pentry->freq_hz, pentry->irq);if (!pentry->irq)continue ; - mp_irq.type =MP_IOAPIC ; + mp_irq.type =MP_INTSRC ; mp_irq.irqtype = mp_INT;/* triggering mode edge bit 2-3, active high polarity bit 0-1 */ mp_irq.irqflag =5 ; mp_irq.srcbus =0 ; - mp_irq.srcbusirq = pentry->irq;/* IRQ */ + mp_irq.srcbusirq = pentry->irq + gsi_top;/* IRQ */ mp_irq.dstapic =MP_APIC_ALL ; mp_irq.dstirq = pentry->irq;mp_save_irq (&mp_irq);
Signature · 1 line
1.7.1
A message that is not in the archive (sent off-list or not yet received): [email protected]
Hi Jacob,
The mrst vrtc driver has the similar irq number problem in 2.6.39-rc2, how about the following patch to solve it in ioapic code.
Also I saw NR_IRQS_LEGACY are used in several other places of io_apic code, it may has some potential issue for mrst which I'm not sure.
Thanks,
Feng
---------------------
Quoted 1 line
From
9bfe95ca6b1737a0418c6403f9684da9fb844cbfMon Sep 17 00:00:00 2001
From: Feng Tang <[email protected]>
Date: Thu, 7 Apr 2011 09:08:00 +0800
Subject: [PATCH] x86: ioapic: use legacy_pic->nr_legacy_irqs instead of NR_IRQS_LEGACY for pin_2_irq()
legacy_pic->nr_legacy_irqs has the correct number of legacy irqs for a x86 platform (legacy PC, Moorestown etc).
--- arch/x86/kernel/apic/io_apic.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
arch/x86/kernel/apic/io_apic.c +1 -1
@@ -954,7 +954,7 @@ static int pin_2_irq(int idx, int apic, int pin) }else {u32 gsi = mp_gsi_routing[apic].gsi_base + pin; -if (gsi >=NR_IRQS_LEGACY ) +if (gsi >= legacy_pic->nr_legacy_irqs) irq = gsi;else irq = gsi_top + gsi;
Signature · 1 line
1.7.0.4
Quoted 70 lines
From: Jacob Pan <[email protected]>
Date: 2011/4/5
Subject: [PATCH] x86/mrst: move sfi timer irqs aftergsi_top
To: LKML <[email protected]>, "H. Peter Anvin" <[email protected]>, Ingo Molnar <[email protected]>, Thomas Gleixner <[email protected]>, Arjan van de Ven <[email protected]>, Alan Cox <[email protected]>
抄送： Jacob Pan <[email protected]>Moorestown borrows
mp_irqsfor its early SFI device IRQs, it used to be 1:1 mapped between irq # and ioapic pin#. Aftergsi_topis introduced, we have to allocate irqs on top ofgsi_topsince below that irqs are not set to ioapic chip whereas Moorestown SFI device irqs are all routed via ioapic chip.Without this fix, Moorestown fails to boot at secondary clock setup since it cannot do
request_irqon cpu 1 timer which does not have a validirq_chip.Also use correct MP configuration table entry type INTSRC, which is used for IO interrupt assignment.
Signed-off-by Jacob Pan <[email protected]>--- arch/x86/kernel/apb_timer.c | 2 +- arch/x86/platform/mrst/mrst.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)arch/x86/kernel/apb_timer.c +1
-1@@ -630,7 +630,7 @@ void __init apbt_time_init(void) p_mtmr =sfi_get_mtmr (i);if (p_mtmr) { adev->tick = p_mtmr->freq_hz; - adev->irq = p_mtmr->irq; + adev->irq = p_mtmr->irq + gsi_top; }else printk(KERN_ERR "Failed to get timer for cpu %d\n", i); adev->count = 0;(quoted diff) +0
-0
b/arch/x86/platform/mrst/mrst.cindex 5c0207b..448c20d 100644arch/x86/platform/mrst/mrst.c +2
-2@@ -97,12 +97,12 @@ static int __init sfi_parse_mtmr(struct sfi_table_header *table) pentry->freq_hz, pentry->irq);if (!pentry->irq)continue ; -mp_irq.type = MP_IOAPIC; + mp_irq.type =MP_INTSRC ; mp_irq.irqtype = mp_INT;/* triggering mode edge bit 2-3, active high polarity bit 0-1 */ mp_irq.irqflag =5 ; mp_irq.srcbus =0 ; - mp_irq.srcbusirq = pentry->irq;/* IRQ */ + mp_irq.srcbusirq = pentry->irq + gsi_top;/* IRQ */ mp_irq.dstapic =MP_APIC_ALL ; mp_irq.dstirq = pentry->irq;mp_save_irq(&mp_irq);--
1.7.1--
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Quoted 4 lines · On Thu, 7 Apr 2011 09:30:21 +0800 Feng Tang <[email protected]> wrote:
Hi Jacob,
The mrst vrtc driver has the similar irq number problem in 2.6.39-rc2, how about the following patch to solve it in ioapic code.
Just dug up the old thread in https://lkml.org/lkml/2010/6/10/70. I actually have been through this before, I just sent out another patch for this as suggested by Eric.
This patch is withdrawn now.
Thanks,
Jacob