Big Endian support for RV730 (Mesa r600)

PATCH In review Cédric Cano 2 participants 4 messages Apr 12, 2011 – Apr 14, 2011

Share & tools

Cédric Cano

author

2011-04-12 11:31 UTC #0 lore raw

PATCH 1/1 Big Endian support for RV730 (Mesa r600)

Here you are a patch that adds big endian support for rv730 in r600 classic mesa driver. The BE modifications are almost the same as the DRM / DDX driver modifications (http://lists.freedesktop.org/archives/dri-devel/2011-February/008151.html).

I used the mesa-demos to test the driver status on big endian platform. Nearly all demos renders the same as on Intel architecture. Nevertheless, there are still some issues in glReadPixels (r600_blit) with some formats. I can't figure out exactly what and when data must be swapped (set_tex_resoures, set_render_target...). Review of the patch would be greatly appreciated.

It seems that r600g will be the default for Mesa 7.11 so I'll try to enable big endian support for Gallium now.

Regards
Cédric Cano

src/mesa/drivers/dri/r600/defaultendian.h +2 -2

diff -Naur Mesa-7.10/src/mesa/drivers/dri/r600/defaultendian.h Mesa-7.10/src/mesa/drivers/dri/r600/defaultendian.h
@@ -29,8 +29,8 @@
 #define _DEFINEENDIAN_H_
 
 //We have to choose a reg bits orientation if there is no compile flag for it.
-#if defined(LITTLEENDIAN_CPU)
-#elif defined(BIGENDIAN_CPU)
+#ifdef MESA_BIG_ENDIAN
+#define BIGENDIAN_CPU
 #else
 #define LITTLEENDIAN_CPU
 #endif

src/mesa/drivers/dri/r600/r600_blit.c +108 -9

351 lines not on this page · raw message

src/mesa/drivers/dri/r600/r600_blit_shaders.h +4 -0

diff -Naur Mesa-7.10/src/mesa/drivers/dri/r600/r600_blit_shaders.h Mesa-7.10/src/mesa/drivers/dri/r600/r600_blit_shaders.h
@@ -10,7 +10,11 @@
         0x00000000,
         0x3c000000, // SQ_VTX_INST_FETCH BUFFER_ID(0) MEGA_FETCH_COUNT(16)
         0x68cd1000, // DST_GPR(0) DST_SWZ: XYZW DATA_FORMAT(35) SQ_NUM_FORMAT_SCALED SQ_FORMAT_COMP_SIGNED
+#ifdef MESA_BIG_ENDIAN
+		0x000a0000, // ENDIAN_SWAP(SQ_ENDIAN_8IN32) MEGA_FETCH(1)
+#else
         0x00080000, // ENDIAN_SWAP(SQ_ENDIAN_NONE) MEGA_FETCH(1)
+#endif
         0x00000000, // VTX_DWORD_PAD
 };

src/mesa/drivers/dri/r600/r600_emit.c +11 -5

diff -Naur Mesa-7.10/src/mesa/drivers/dri/r600/r600_emit.c Mesa-7.10/src/mesa/drivers/dri/r600/r600_emit.c
@@ -100,14 +100,17 @@
                                int sizeinBYTE)
 {	
 	struct radeon_bo * pbo = (struct radeon_bo *)constbo;
-	uint8_t *out;
+	uint32_t *out;
+	int i;
 
 	radeon_bo_map(pbo, 1);
 
-	out = (uint8_t*)(pbo->ptr);
-    out = (uint8_t*)ADD_POINTERS(pbo->ptr, bo_offset);
+	out = (uint32_t*)(pbo->ptr);
+    out = (uint32_t*)ADD_POINTERS(pbo->ptr, bo_offset);
 
-	memcpy(out, data, sizeinBYTE);
+	for(i = 0; i < sizeinBYTE / 4; i++) {
+		out[i] = CPU_TO_LE32(*((uint32_t *)data + i));
+	}
 
 	radeon_bo_unmap(pbo);

@@ -123,6 +126,7 @@
 	radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
 	struct radeon_bo * pbo;
 	uint32_t *out;
+	int i;
 shader_again_alloc:
 	pbo = radeon_bo_open(radeonctx->radeonScreen->bom,
 			0,

@@ -154,7 +158,9 @@
 
 	out = (uint32_t*)(pbo->ptr);
 
-	memcpy(out, data, sizeinDWORD * 4);
+	for(i = 0; i < sizeinDWORD; i++) {
+		out[i] = CPU_TO_LE32(*((uint32_t *)data + i));
+	}
 
 	radeon_bo_unmap(pbo);

src/mesa/drivers/dri/r600/r600_texstate.c +145 -4

293 lines not on this page · raw message

src/mesa/drivers/dri/r600/r700_assembler.c +10 -1

diff -Naur Mesa-7.10/src/mesa/drivers/dri/r600/r700_assembler.c Mesa-7.10/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -1184,7 +1184,12 @@
     SETfield(vfetch_instruction_ptr->m_Word2.val, 0,
              EG_VTX_WORD2__OFFSET_shift,
              EG_VTX_WORD2__OFFSET_mask); 
-    SETfield(vfetch_instruction_ptr->m_Word2.val, SQ_ENDIAN_NONE,
+    SETfield(vfetch_instruction_ptr->m_Word2.val, 
+#ifdef MESA_BIG_ENDIAN
+			 SQ_ENDIAN_8IN32,
+#else
+			 SQ_ENDIAN_NONE,
+#endif
              EG_VTX_WORD2__ENDIAN_SWAP_shift,
              EG_VTX_WORD2__ENDIAN_SWAP_mask);
     SETfield(vfetch_instruction_ptr->m_Word2.val, 0,

@@ -1290,7 +1295,11 @@
 
 	vfetch_instruction_ptr->m_Word1.f.use_const_fields = 1;
     vfetch_instruction_ptr->m_Word1.f.data_format      = data_format;
+#ifdef MESA_BIG_ENDIAN
+    vfetch_instruction_ptr->m_Word2.f.endian_swap      = SQ_ENDIAN_8IN32;
+#else
     vfetch_instruction_ptr->m_Word2.f.endian_swap      = SQ_ENDIAN_NONE;
+#endif
 
     if(1 == _signed)
     {

src/mesa/drivers/dri/r600/r700_assembler.h +133 -0

214 lines not on this page · raw message

src/mesa/drivers/dri/r600/r700_chip.c +9 -1

diff -Naur Mesa-7.10/src/mesa/drivers/dri/r600/r700_chip.c Mesa-7.10/src/mesa/drivers/dri/r600/r700_chip.c
@@ -202,7 +202,15 @@
     SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
 	     SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
 	     SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
-    
+	SETfield(uSQ_VTX_CONSTANT_WORD2_0, 
+#ifdef MESA_BIG_ENDIAN 
+			 SQ_ENDIAN_8IN32,
+#else
+			 SQ_ENDIAN_NONE,
+#endif
+             SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift,
+             SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask);
+
     if(GL_TRUE == pStreamDesc->normalize)
     {
         SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,

src/mesa/drivers/dri/r600/r700_render.c +19 -0

diff -Naur Mesa-7.10/src/mesa/drivers/dri/r600/r700_render.c Mesa-7.10/src/mesa/drivers/dri/r600/r700_render.c
@@ -276,6 +276,16 @@
             SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
     }
 
+	/* 16-bit indexes are packed in a 32-bit value */
+	SETfield(vgt_index_type,
+#if MESA_BIG_ENDIAN
+			VGT_DMA_SWAP_32_BIT,
+#else
+			VGT_DMA_SWAP_NONE,
+#endif
+			SWAP_MODE_shift, SWAP_MODE_mask);
+
+
     vgt_num_indices = num_indices;
     SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
     SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);

@@ -348,6 +358,15 @@
             SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
     }
 
+	/* 16-bit indexes are packed in a 32-bit value */
+	SETfield(vgt_index_type,
+#if MESA_BIG_ENDIAN
+			VGT_DMA_SWAP_32_BIT,
+#else
+			VGT_DMA_SWAP_NONE,
+#endif
+			SWAP_MODE_shift, SWAP_MODE_mask);
+
     vgt_num_indices = num_indices;
     SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);

src/mesa/drivers/dri/radeon/radeon_common.c +1 -1

diff -Naur Mesa-7.10/src/mesa/drivers/dri/radeon/radeon_common.c Mesa-7.10/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -966,7 +966,7 @@
 
 	fprintf(stderr, "  emit %s %d/%d\n", state->name, dwords, state->cmd_size);
 
-	if (radeon_is_debug_enabled(RADEON_STATE, RADEON_TRACE)) {
+	if (state->cmd && radeon_is_debug_enabled(RADEON_STATE, RADEON_TRACE)) {
 		if (dwords > state->cmd_size)
 			dwords = state->cmd_size;
 		for (i = 0; i < dwords;) {

src/mesa/drivers/dri/radeon/radeon_span.c +66 ~~-27~~

222 lines not on this page · raw message

_______________________________________________
dri-devel mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/dri-devel

Benjamin Herrenschmidt

2011-04-13 12:05 UTC #1 lore raw

Quoted 14 lines · Cédric Cano

Hi
Here you are a patch that adds big endian support for rv730 in r600 classic mesa driver. The BE modifications are almost the same as the DRM / DDX driver modifications
(http://lists.freedesktop.org/archives/dri-devel/2011-February/008151.html).
I used the mesa-demos to test the driver status on big endian platform. Nearly all demos renders the same as on Intel architecture. Nevertheless, there are still some issues in glReadPixels (r600_blit) with some formats. I can't figure out exactly what and when data must be swapped (set_tex_resoures, set_render_target...). Review of the patch would be greatly appreciated.

Quoted 2 lines

It seems that r600g will be the default for Mesa 7.11 so I'll try to enable big endian support for Gallium now.

Cool stuff !

I'll try to test that one of these days on various ppc's

Cheers,
Ben.

_______________________________________________
dri-devel mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/dri-devel

Benjamin Herrenschmidt

2011-04-13 12:10 UTC #2 lore raw

Quoted 15 lines · Benjamin Herrenschmidt

Quoted 14 lines · Cédric Cano
Hi
Here you are a patch that adds big endian support for rv730 in r600 classic mesa driver. The BE modifications are almost the same as the DRM / DDX driver modifications
(http://lists.freedesktop.org/archives/dri-devel/2011-February/008151.html).
I used the mesa-demos to test the driver status on big endian platform. Nearly all demos renders the same as on Intel architecture. Nevertheless, there are still some issues in glReadPixels (r600_blit) with some formats. I can't figure out exactly what and when data must be swapped (set_tex_resoures, set_render_target...). Review of the patch would be greatly appreciated.

Quoted 6 lines

Quoted 2 lines
It seems that r600g will be the default for Mesa 7.11 so I'll try to enable big endian support for Gallium now.
Cool stuff !
I'll try to test that one of these days on various ppc's

BTW. I see you used some FSL embedded board. Do you have your PCIe MMIO space above 32-bit ? Last I looked, there was a bunch of fixing needing to be done, among others in the TTM, to make that work.

I had some preliminary patches but they bitrot... mostly the issue is to make sure than a phys_addr_t is used instead of an unsigned long whenever it tries to store the physical address of an object.

Ben.

_______________________________________________
dri-devel mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/dri-devel

Cédric Cano

author

2011-04-14 07:54 UTC #3 lore raw

Quoted 25 lines · Benjamin Herrenschmidt

Quoted 15 lines · Benjamin Herrenschmidt
Quoted 14 lines · Cédric Cano
Hi
Here you are a patch that adds big endian support for rv730 in r600 classic mesa driver. The BE modifications are almost the same as the DRM / DDX driver modifications
(http://lists.freedesktop.org/archives/dri-devel/2011-February/008151.html).
I used the mesa-demos to test the driver status on big endian platform. Nearly all demos renders the same as on Intel architecture. Nevertheless, there are still some issues in glReadPixels (r600_blit) with some formats. I can't figure out exactly what and when data must be swapped (set_tex_resoures, set_render_target...). Review of the patch would be greatly appreciated.
Quoted 5 lines
Quoted 2 lines
It seems that r600g will be the default for Mesa 7.11 so I'll try to enable big endian support for Gallium now.
Cool stuff !
I'll try to test that one of these days on various ppc's
BTW. I see you used some FSL embedded board. Do you have your PCIe MMIO space above 32-bit ? Last I looked, there was a bunch of fixing needing to be done, among others in the TTM, to make that work.

Quoted 8 lines

I had some preliminary patches but they bitrot... mostly the issue is to make sure than a phys_addr_t is used instead of an unsigned long whenever it tries to store the physical address of an object.
Ben.

Hi Ben,

I don't use Freescale eval boards but our custom PowerPC design. We didn't enable the 36-bit addressing mode yet.

Cédric

_______________________________________________
dri-devel mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/dri-devel