ARM: kprobes: Fixes and additions for ARM instruction emulation (part 6)
cover ARM: kprobes: Fixes and additions for ARM instruction emulation (part 6)
(This is a sixth and final set of patches)
When kprobes are inserted into code an ARM instruction is replaced by a breakpoint. When this is hit, the original instruction must be emulated out-of-line. This patchset fixes some bugs in the instruction decoding and adds emulation for some newer ARMv7 instructions.
[PATCH 1/5] ARM: kprobes: Reject probing of undefined data processing instructions [PATCH 2/5] ARM: kprobes: Add emulation of MOVW and MOVT instructions [PATCH 3/5] ARM: kprobes: Add emulation of SBFX, UBFX, BFI and BFC instructions [PATCH 4/5] ARM: kprobes: Add emulation of hint instructions like NOP and WFI [PATCH 5/5] ARM: kprobes: Tidy-up kprobes-decode.c
PATCH 1/5 ARM: kprobes: Reject probing of undefined data processing instructions
From: Jon Medhurst <[email protected]>
The instruction decoding in space_cccc_000x needs to reject probing of instructions with undefined patterns as they may in future become defined and then emulated faultily - as has already happened with the SMC instruction.
This fix is achieved by testing for the instruction patterns we want to probe and making the the default fall-through paths reject probes. This also allows us to remove some explicit tests for instructions that we wish to reject, as that is now the default action.
--- arch/arm/kernel/kprobes-decode.c | 31 +++++++++++++++++-------------- 1 files changed, 17 insertions(+), 14 deletions(-)
arch/arm/kernel/kprobes-decode.c +17 -14
@@ -966,14 +966,6 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)/* cccc 0001 0xx0 xxxx xxxx xxxx xxxx xxx0 xxxx */ if ((insn &0x0f900010 ) ==0x01000000 ) { -/* BXJ : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */ -/* MSR : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */ -/* MRS spsr : cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */ -if ((insn &0x0ff000f0 ) ==0x01200020 || - (insn &0x0fb000f0 ) ==0x01200000 || - (insn &0x0ff000f0 ) ==0x01400000 ) -return INSN_REJECTED ; -/* MRS cpsr : cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */ if ((insn &0x0ff000f0 ) ==0x01000000 ) {if (is_r15 (insn,12 ))
@@ -994,17 +986,21 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)/* SMLAxy : cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx : Q */ /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx : Q */ -return prep_emulate_rd16rn12rs8rm0_wflags (insn, asi); +if ((insn &0x0ff00090 ) ==0x01000080 || + (insn &0x0ff000b0 ) ==0x01200080 ) +return prep_emulate_rd16rn12rs8rm0_wflags (insn, asi); + +/* BXJ : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */ +/* MSR : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */ +/* MRS spsr : cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */ +/* Other instruction encodings aren't yet defined */ +return INSN_REJECTED ; }/* cccc 0001 0xx0 xxxx xxxx xxxx xxxx 0xx1 xxxx */ else if ((insn &0x0f900090 ) ==0x01000010 ) { -/* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */ -if ((insn &0xfff000f0 ) ==0xe1200070 ) -return INSN_REJECTED ; -/* BLX(2) : cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */ /* BX : cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */ if ((insn &0x0ff000d0 ) ==0x01200010 ) {
@@ -1022,7 +1018,14 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)/* QSUB : cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx :Q */ /* QDADD : cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx :Q */ /* QDSUB : cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx :Q */ -return prep_emulate_rd12rn16rm0_wflags (insn, asi); +if ((insn &0x0f9000f0 ) ==0x01000050 ) +return prep_emulate_rd12rn16rm0_wflags (insn, asi); + +/* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */ +/* SMC : cccc 0001 0110 xxxx xxxx xxxx 0111 xxxx */ + +/* Other instruction encodings aren't yet defined */ +return INSN_REJECTED ; }/* cccc 0000 xxxx xxxx xxxx xxxx xxxx 1001 xxxx */
Signature · 1 line
1.7.2.5
PATCH 2/5 ARM: kprobes: Add emulation of MOVW and MOVT instructions
In reply to TixyFrom: Jon Medhurst <[email protected]>
The MOVW and MOVT instructions account for approximately 7% of all instructions in a ARMv7 kernel as GCC uses them instead of a literal pool.
--- arch/arm/kernel/kprobes-decode.c | 30 ++++++++++++++++++++++++++++-- 1 files changed, 28 insertions(+), 2 deletions(-)
arch/arm/kernel/kprobes-decode.c +28 -2
@@ -661,6 +661,17 @@ static void __kprobes emulate_nop(struct kprobe *p, struct pt_regs *regs) { } +static void __kprobes +emulate_rd12_modify (struct kprobe *p,struct pt_regs *regs) +{ +insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0 ]; +kprobe_opcode_t insn = p->opcode; +int rd = (insn >>12 ) &0xf ; +long rdv = regs->uregs[rd]; + + regs->uregs[rd] =insnslot_1arg_rflags (rdv, regs->ARM_cpsr, i_fn); +} +static void __kprobes emulate_rd12rm0 (struct kprobe *p,struct pt_regs *regs) {insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0 ];
@@ -847,6 +858,18 @@ prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi) }static enum kprobe_insn __kprobes +prep_emulate_rd12_modify (kprobe_opcode_t insn,struct arch_specific_insn *asi) +{ +if (is_r15 (insn,12 )) +return INSN_REJECTED ;/* Rd is PC */ + + insn &=0xffff0fff ;/* Rd = r0 */ + asi->insn[0 ] = insn; + asi->insn_handler = emulate_rd12_modify; +return INSN_GOOD ; +} + +static enum kprobe_insn __kprobes prep_emulate_rd12rm0 (kprobe_opcode_t insn,struct arch_specific_insn *asi) {if (is_r15 (insn,12 ))
@@ -1170,14 +1193,17 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)static enum kprobe_insn __kprobes space_cccc_001x (kprobe_opcode_t insn,struct arch_specific_insn *asi) { +/* MOVW : cccc 0011 0000 xxxx xxxx xxxx xxxx xxxx */ +/* MOVT : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx */ +if ((insn &0x0fb00000 ) ==0x03000000 ) +return prep_emulate_rd12_modify (insn, asi); +/* * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx -* Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx * ALU op with S bit and Rd == 15 : * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx */ if ((insn &0x0fb00000 ) ==0x03200000 ||/* MSR */ - (insn &0x0ff00000 ) ==0x03400000 ||/* Undef */ (insn &0x0e10f000 ) ==0x0210f000 )/* ALU s-bit, R15 */ return INSN_REJECTED ;
Signature · 1 line
1.7.2.5
PATCH 3/5 ARM: kprobes: Add emulation of SBFX, UBFX, BFI and BFC instructions
In reply to TixyFrom: Jon Medhurst <[email protected]>
These bit field manipulation instructions occur several thousand times in an ARMv7 kernel.
--- arch/arm/kernel/kprobes-decode.c | 42 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 42 insertions(+), 0 deletions(-)
arch/arm/kernel/kprobes-decode.c +42 -0
@@ -672,6 +672,19 @@ emulate_rd12_modify(struct kprobe *p, struct pt_regs *regs) regs->uregs[rd] =insnslot_1arg_rflags (rdv, regs->ARM_cpsr, i_fn); } +static void __kprobes +emulate_rd12rn0_modify (struct kprobe *p,struct pt_regs *regs) +{ +insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0 ]; +kprobe_opcode_t insn = p->opcode; +int rd = (insn >>12 ) &0xf ; +int rn = insn &0xf ; +long rdv = regs->uregs[rd]; +long rnv = regs->uregs[rn]; + + regs->uregs[rd] =insnslot_2arg_rflags (rdv, rnv, regs->ARM_cpsr, i_fn); +} +static void __kprobes emulate_rd12rm0 (struct kprobe *p,struct pt_regs *regs) {insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0 ];
@@ -870,6 +883,20 @@ prep_emulate_rd12_modify(kprobe_opcode_t insn, struct arch_specific_insn *asi) }static enum kprobe_insn __kprobes +prep_emulate_rd12rn0_modify (kprobe_opcode_t insn, +struct arch_specific_insn *asi) +{ +if (is_r15 (insn,12 )) +return INSN_REJECTED ;/* Rd is PC */ + + insn &=0xffff0ff0 ;/* Rd = r0 */ + insn |=0x00000001 ;/* Rn = r1 */ + asi->insn[0 ] = insn; + asi->insn_handler = emulate_rd12rn0_modify; +return INSN_GOOD ; +} + +static enum kprobe_insn __kprobes prep_emulate_rd12rm0 (kprobe_opcode_t insn,struct arch_specific_insn *asi) {if (is_r15 (insn,12 ))
@@ -1396,6 +1423,21 @@ space_cccc_0111__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)if ((insn &0x0ff000d0 ) ==0x075000d0 )return prep_emulate_rd16rn12rs8rm0_wflags (insn, asi); +/* SBFX : cccc 0111 101x xxxx xxxx xxxx x101 xxxx : */ +/* UBFX : cccc 0111 111x xxxx xxxx xxxx x101 xxxx : */ +if ((insn &0x0fa00070 ) ==0x07a00050 ) +return prep_emulate_rd12rm0 (insn, asi); + +/* BFI : cccc 0111 110x xxxx xxxx xxxx x001 xxxx : */ +/* BFC : cccc 0111 110x xxxx xxxx xxxx x001 1111 : */ +if ((insn &0x0fe00070 ) ==0x07c00010 ) { + +if ((insn &0x0000000f ) ==0x0000000f ) +return prep_emulate_rd12_modify (insn, asi); +else +return prep_emulate_rd12rn0_modify (insn, asi); + } +return INSN_REJECTED ; }
Signature · 1 line
1.7.2.5
PATCH 4/5 ARM: kprobes: Add emulation of hint instructions like NOP and WFI
In reply to TixyFrom: Jon Medhurst <[email protected]>
Being able to probe NOP instructions is useful for hard-coding probeable locations and is used by the kprobes test code.
--- arch/arm/kernel/kprobes-decode.c | 24 ++++++++++++++++++++++++ 1 files changed, 24 insertions(+), 0 deletions(-)
arch/arm/kernel/kprobes-decode.c +24 -0
@@ -1225,6 +1225,30 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)if ((insn &0x0fb00000 ) ==0x03000000 )return prep_emulate_rd12_modify (insn, asi); +/* hints : cccc 0011 0010 0000 xxxx xxxx xxxx xxxx */ +if ((insn &0x0fff0000 ) ==0x03200000 ) { +unsigned op2 = insn &0x000000ff ; +if (op2 ==0x01 || op2 ==0x04 ) { +/* YIELD : cccc 0011 0010 0000 xxxx xxxx 0000 0001 */ +/* SEV : cccc 0011 0010 0000 xxxx xxxx 0000 0100 */ + asi->insn[0 ] = insn; + asi->insn_handler = emulate_none; +return INSN_GOOD ; + }else if (op2 <=0x03 ) { +/* NOP : cccc 0011 0010 0000 xxxx xxxx 0000 0000 */ +/* WFE : cccc 0011 0010 0000 xxxx xxxx 0000 0010 */ +/* WFI : cccc 0011 0010 0000 xxxx xxxx 0000 0011 */ +/* +* We make WFE and WFI true NOPs to avoid stalls due +* to missing events whilst processing the probe. +*/ + asi->insn_handler = emulate_nop; +return INSN_GOOD_NO_SLOT ; + } +/* For DBG and unallocated hints it's safest to reject them */ +return INSN_REJECTED ; + } +/* * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx * ALU op with S bit and Rd == 15 :
Signature · 1 line
1.7.2.5
PATCH 5/5 ARM: kprobes: Tidy-up kprobes-decode.c
In reply to TixyFrom: Jon Medhurst <[email protected]>
- Remove coding standard violations reported by checkpatch.pl
- Delete comment about handling of conditional branches which is no longer true.
- Delete comment at end of file which lists all ARM instructions. This duplicates data available in the ARM ARM and seems like an unnecessary maintenance burden to keep this up to date and accurate.
--- arch/arm/kernel/kprobes-decode.c | 131 +++++++------------------------------- 1 files changed, 23 insertions(+), 108 deletions(-)
arch/arm/kernel/kprobes-decode.c +23 -108
@@ -34,9 +34,6 @@* * *) If the PC is written to by the instruction, the * instruction must be fully simulated in software. -* If it is a conditional instruction, the handler -* will use insn[0] to copy its condition code to -* set r0 to 1 and insn[1] to "mov pc, lr" to return. * * *) Otherwise, a modified form of the instruction is * directly executed. Its handler calls the
@@ -1026,7 +1023,8 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)/* SMLALxy : cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */ if ((insn &0x0ff00090 ) ==0x01400080 ) -return prep_emulate_rdhi16rdlo12rs8rm0_wflags (insn, asi); +return prep_emulate_rdhi16rdlo12rs8rm0_wflags (insn, + asi);/* SMULWy : cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */ /* SMULxy : cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
@@ -1097,15 +1095,15 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)/* SMULLS : cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx :cc */ /* SMLAL : cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx : */ /* SMLALS : cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx :cc */ -if ((insn &0x00d00000 ) ==0x00500000 ) { +if ((insn &0x00d00000 ) ==0x00500000 )return INSN_REJECTED ; - }else if ((insn &0x00e00000 ) ==0x00000000 ) { -return prep_emulate_rd16rs8rm0_wflags (insn, asi); - }else if ((insn &0x00a00000 ) ==0x00200000 ) { -return prep_emulate_rd16rn12rs8rm0_wflags (insn, asi); - }else { -return prep_emulate_rdhi16rdlo12rs8rm0_wflags (insn, asi); - } +else if ((insn &0x00e00000 ) ==0x00000000 ) +return prep_emulate_rd16rs8rm0_wflags (insn, asi); +else if ((insn &0x00a00000 ) ==0x00200000 ) +return prep_emulate_rd16rn12rs8rm0_wflags (insn, asi); +else +return prep_emulate_rdhi16rdlo12rs8rm0_wflags (insn, + asi); }/* cccc 000x xxxx xxxx xxxx xxxx xxxx 1xx1 xxxx */
@@ -1171,7 +1169,7 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)/* * ALU op with S bit and Rd == 15 : -* cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx +* cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx */ if ((insn &0x0e10f000 ) ==0x0010f000 )return INSN_REJECTED ;
@@ -1401,11 +1399,10 @@ space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)if ((insn &0x00300000 ) ==0x00100000 )return INSN_REJECTED ;/* Unallocated space */ -if ((insn &0x000f0000 ) ==0x000f0000 ) { +if ((insn &0x000f0000 ) ==0x000f0000 )return prep_emulate_rd12rm0 (insn, asi); - }else { +else return prep_emulate_rd12rn16rm0_wflags (insn, asi); - } }/* Other instruction encodings aren't yet defined */
@@ -1436,11 +1433,10 @@ space_cccc_0111__1(kprobe_opcode_t insn, struct arch_specific_insn *asi) (insn & 0x0ff000d0) == 0x07500010 || (insn & 0x0ff000f0) == 0x07800010) { -if ((insn &0x0000f000 ) ==0x0000f000 ) { +if ((insn &0x0000f000 ) ==0x0000f000 )return prep_emulate_rd16rs8rm0_wflags (insn, asi); - }else { +else return prep_emulate_rd16rn12rs8rm0_wflags (insn, asi); - } }/* SMMLS : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx : */
@@ -1633,40 +1629,38 @@ arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi) asi->insn_check_cc = condition_checks[insn>>28 ]; asi->insn[1 ] =KPROBE_RETURN_INSTRUCTION ; -if ((insn &0xf0000000 ) ==0xf0000000 ) { +if ((insn &0xf0000000 ) ==0xf0000000 )return space_1111 (insn, asi); - }else if ((insn &0x0e000000 ) ==0x00000000 ) { +else if ((insn &0x0e000000 ) ==0x00000000 )return space_cccc_000x (insn, asi); - }else if ((insn &0x0e000000 ) ==0x02000000 ) { +else if ((insn &0x0e000000 ) ==0x02000000 )return space_cccc_001x (insn, asi); - }else if ((insn &0x0f000010 ) ==0x06000010 ) { +else if ((insn &0x0f000010 ) ==0x06000010 )return space_cccc_0110__1 (insn, asi); - }else if ((insn &0x0f000010 ) ==0x07000010 ) { +else if ((insn &0x0f000010 ) ==0x07000010 )return space_cccc_0111__1 (insn, asi); - }else if ((insn &0x0c000000 ) ==0x04000000 ) { +else if ((insn &0x0c000000 ) ==0x04000000 )return space_cccc_01xx (insn, asi); - }else if ((insn &0x0e000000 ) ==0x08000000 ) { +else if ((insn &0x0e000000 ) ==0x08000000 )return space_cccc_100x (insn, asi); - }else if ((insn &0x0e000000 ) ==0x0a000000 ) { +else if ((insn &0x0e000000 ) ==0x0a000000 )return space_cccc_101x (insn, asi); - } -return space_cccc_11xx (insn, asi); }
@@ -1674,82 +1668,3 @@ void __init arm_kprobe_decode_init(void) {find_str_pc_offset (); } - - -/* -* All ARM instructions listed below. -* -* Instructions and their general purpose registers are given. -* If a particular register may not use R15, it is prefixed with a "!". -* If marked with a "*" means the value returned by reading R15 -* is implementation defined. -* -* ADC/ADD/AND/BIC/CMN/CMP/EOR/MOV/MVN/ORR/RSB/RSC/SBC/SUB/TEQ -* TST: Rd, Rn, Rm, !Rs -* BX: Rm -* BLX(2): !Rm -* BX: Rm (R15 legal, but discouraged) -* BXJ: !Rm, -* CLZ: !Rd, !Rm -* CPY: Rd, Rm -* LDC/2,STC/2 immediate offset & unindex: Rn -* LDC/2,STC/2 immediate pre/post-indexed: !Rn -* LDM(1/3): !Rn, register_list -* LDM(2): !Rn, !register_list -* LDR,STR,PLD immediate offset: Rd, Rn -* LDR,STR,PLD register offset: Rd, Rn, !Rm -* LDR,STR,PLD scaled register offset: Rd, !Rn, !Rm -* LDR,STR immediate pre/post-indexed: Rd, !Rn -* LDR,STR register pre/post-indexed: Rd, !Rn, !Rm -* LDR,STR scaled register pre/post-indexed: Rd, !Rn, !Rm -* LDRB,STRB immediate offset: !Rd, Rn -* LDRB,STRB register offset: !Rd, Rn, !Rm -* LDRB,STRB scaled register offset: !Rd, !Rn, !Rm -* LDRB,STRB immediate pre/post-indexed: !Rd, !Rn -* LDRB,STRB register pre/post-indexed: !Rd, !Rn, !Rm -* LDRB,STRB scaled register pre/post-indexed: !Rd, !Rn, !Rm -* LDRT,LDRBT,STRBT immediate pre/post-indexed: !Rd, !Rn -* LDRT,LDRBT,STRBT register pre/post-indexed: !Rd, !Rn, !Rm -* LDRT,LDRBT,STRBT scaled register pre/post-indexed: !Rd, !Rn, !Rm -* LDRH/SH/SB/D,STRH/SH/SB/D immediate offset: !Rd, Rn -* LDRH/SH/SB/D,STRH/SH/SB/D register offset: !Rd, Rn, !Rm -* LDRH/SH/SB/D,STRH/SH/SB/D immediate pre/post-indexed: !Rd, !Rn -* LDRH/SH/SB/D,STRH/SH/SB/D register pre/post-indexed: !Rd, !Rn, !Rm -* LDREX: !Rd, !Rn -* MCR/2: !Rd -* MCRR/2,MRRC/2: !Rd, !Rn -* MLA: !Rd, !Rn, !Rm, !Rs -* MOV: Rd -* MRC/2: !Rd (if Rd==15, only changes cond codes, not the register) -* MRS,MSR: !Rd -* MUL: !Rd, !Rm, !Rs -* PKH{BT,TB}: !Rd, !Rn, !Rm -* QDADD,[U]QADD/16/8/SUBX: !Rd, !Rm, !Rn -* QDSUB,[U]QSUB/16/8/ADDX: !Rd, !Rm, !Rn -* REV/16/SH: !Rd, !Rm -* RFE: !Rn -* {S,U}[H]ADD{16,8,SUBX},{S,U}[H]SUB{16,8,ADDX}: !Rd, !Rn, !Rm -* SEL: !Rd, !Rn, !Rm -* SMLA<x><y>,SMLA{D,W<y>},SMLSD,SMML{A,S}: !Rd, !Rn, !Rm, !Rs -* SMLAL<x><y>,SMLA{D,LD},SMLSLD,SMMULL,SMULW<y>: !RdHi, !RdLo, !Rm, !Rs -* SMMUL,SMUAD,SMUL<x><y>,SMUSD: !Rd, !Rm, !Rs -* SSAT/16: !Rd, !Rm -* STM(1/2): !Rn, register_list* (R15 in reg list not recommended) -* STRT immediate pre/post-indexed: Rd*, !Rn -* STRT register pre/post-indexed: Rd*, !Rn, !Rm -* STRT scaled register pre/post-indexed: Rd*, !Rn, !Rm -* STREX: !Rd, !Rn, !Rm -* SWP/B: !Rd, !Rn, !Rm -* {S,U}XTA{B,B16,H}: !Rd, !Rn, !Rm -* {S,U}XT{B,B16,H}: !Rd, !Rm -* UM{AA,LA,UL}L: !RdHi, !RdLo, !Rm, !Rs -* USA{D8,A8,T,T16}: !Rd, !Rm, !Rs -* -* May transfer control by writing R15 (possible mode changes or alternate -* mode accesses marked by "*"): -* ALU op (* with s-bit), B, BL, BKPT, BLX(1/2), BX, BXJ, CPS*, CPY, -* LDM(1), LDM(2/3)*, LDR, MOV, RFE*, SWI* -* -* Instructions that do not take general registers, nor transfer control: -* CDP/2, SETEND, SRS* -*/
Signature · 1 line
1.7.2.5
cover ARM: kprobes: Fixes and additions for ARM instruction emulation (part 6)
In reply to TixyQuoted 7 lines · Tixy
(This is a sixth and final set of patches)
When kprobes are inserted into code an ARM instruction is replaced by a breakpoint. When this is hit, the original instruction must be emulated out-of-line. This patchset fixes some bugs in the instruction decoding and adds emulation for some newer ARMv7 instructions.
Quoted 5 lines
[PATCH 1/5] ARM: kprobes: Reject probing of undefined data processing instructions [PATCH 2/5] ARM: kprobes: Add emulation of MOVW and MOVT instructions [PATCH 3/5] ARM: kprobes: Add emulation of SBFX, UBFX, BFI and BFC instructions [PATCH 4/5] ARM: kprobes: Add emulation of hint instructions like NOP and WFI [PATCH 5/5] ARM: kprobes: Tidy-up
kprobes-decode.c
I notice that Nicolas merged the 5th set rather than this set - and Nicolas hasn't responded to these. Please check with Nicolas whether he's updated to the latest set.
cover ARM: kprobes: Fixes and additions for ARM instruction emulation (part 6)
Quoted 14 lines · Russell King - ARM Linux
Quoted 7 lines · Tixy
(This is a sixth and final set of patches)
When kprobes are inserted into code an ARM instruction is replaced by a breakpoint. When this is hit, the original instruction must be emulated out-of-line. This patchset fixes some bugs in the instruction decoding and adds emulation for some newer ARMv7 instructions.
Quoted 5 lines
[PATCH 1/5] ARM: kprobes: Reject probing of undefined data processing instructions [PATCH 2/5] ARM: kprobes: Add emulation of MOVW and MOVT instructions [PATCH 3/5] ARM: kprobes: Add emulation of SBFX, UBFX, BFI and BFC instructions [PATCH 4/5] ARM: kprobes: Add emulation of hint instructions like NOP and WFI [PATCH 5/5] ARM: kprobes: Tidy-up
kprobes-decode.c
Quoted 3 lines
I notice that Nicolas merged the 5th set rather than this set - and Nicolas hasn't responded to these. Please check with Nicolas whether he's updated to the latest set.
Nicolas, I see you have part 6 in your personal Linaro kprobes branch, but Russell seems to imply that this is missing from a merge you did elsewhere. (I'm unsure where this merge might be.)
Signature · 1 line
Tixy
cover ARM: kprobes: Fixes and additions for ARM instruction emulation (part 6)
Quoted 15 lines · Tixy
Quoted 14 lines · Russell King - ARM Linux
Quoted 12 lines · Tixy
(This is a sixth and final set of patches)
When kprobes are inserted into code an ARM instruction is replaced by a breakpoint. When this is hit, the original instruction must be emulated out-of-line. This patchset fixes some bugs in the instruction decoding and adds emulation for some newer ARMv7 instructions.
[PATCH 1/5] ARM: kprobes: Reject probing of undefined data processing instructions [PATCH 2/5] ARM: kprobes: Add emulation of MOVW and MOVT instructions [PATCH 3/5] ARM: kprobes: Add emulation of SBFX, UBFX, BFI and BFC instructions [PATCH 4/5] ARM: kprobes: Add emulation of hint instructions like NOP and WFI [PATCH 5/5] ARM: kprobes: Tidy-up
kprobes-decode.c
Quoted 7 lines
Quoted 3 lines
I notice that Nicolas merged the 5th set rather than this set - and Nicolas hasn't responded to these. Please check with Nicolas whether he's updated to the latest set.
Nicolas, I see you have part 6 in your personal Linaro kprobes branch, but Russell seems to imply that this is missing from a merge you did elsewhere. (I'm unsure where this merge might be.)
All the kprobes patches I've reviewed are in the kprobes branch ofgit://git.linaro.org/people/nico/linux. So far I have 31 patches in there. If something is missing please let me know.
I merged the lot in the Linaro kernel tree as well, that's all.
Nicolas
cover ARM: kprobes: Fixes and additions for ARM instruction emulation (part 6)
Quoted 25 lines · Nicolas Pitre
Quoted 15 lines · Tixy
Quoted 14 lines · Russell King - ARM Linux
Quoted 12 lines · Tixy
(This is a sixth and final set of patches)
When kprobes are inserted into code an ARM instruction is replaced by a breakpoint. When this is hit, the original instruction must be emulated out-of-line. This patchset fixes some bugs in the instruction decoding and adds emulation for some newer ARMv7 instructions.
[PATCH 1/5] ARM: kprobes: Reject probing of undefined data processing instructions [PATCH 2/5] ARM: kprobes: Add emulation of MOVW and MOVT instructions [PATCH 3/5] ARM: kprobes: Add emulation of SBFX, UBFX, BFI and BFC instructions [PATCH 4/5] ARM: kprobes: Add emulation of hint instructions like NOP and WFI [PATCH 5/5] ARM: kprobes: Tidy-up
kprobes-decode.cQuoted 7 lines
Quoted 3 lines
I notice that Nicolas merged the 5th set rather than this set - and Nicolas hasn't responded to these. Please check with Nicolas whether he's updated to the latest set.
Nicolas, I see you have part 6 in your personal Linaro kprobes branch, but Russell seems to imply that this is missing from a merge you did elsewhere. (I'm unsure where this merge might be.)
Quoted 5 lines
All the kprobes patches I've reviewed are in the kprobes branch of
git://git.linaro.org/people/nico/linux. So far I have 31 patches in there. If something is missing please let me know.I merged the lot in the Linaro kernel tree as well, that's all.
I'm only concerned because you apparantly replied to v5 of the patch series saying you merged that, and next day Tixy sent v6. So I'm wondering whether you merged v5 without the v6 updates or whether you did merge v6.
cover ARM: kprobes: Fixes and additions for ARM instruction emulation (part 6)
Quoted 30 lines · Russell King - ARM Linux
Quoted 29 lines · Nicolas Pitre
Quoted 15 lines · Tixy
Quoted 14 lines · Russell King - ARM Linux
Quoted 12 lines · Tixy
(This is a sixth and final set of patches)
When kprobes are inserted into code an ARM instruction is replaced by a breakpoint. When this is hit, the original instruction must be emulated out-of-line. This patchset fixes some bugs in the instruction decoding and adds emulation for some newer ARMv7 instructions.
[PATCH 1/5] ARM: kprobes: Reject probing of undefined data processing instructions [PATCH 2/5] ARM: kprobes: Add emulation of MOVW and MOVT instructions [PATCH 3/5] ARM: kprobes: Add emulation of SBFX, UBFX, BFI and BFC instructions [PATCH 4/5] ARM: kprobes: Add emulation of hint instructions like NOP and WFI [PATCH 5/5] ARM: kprobes: Tidy-up
kprobes-decode.cQuoted 7 lines
Quoted 3 lines
I notice that Nicolas merged the 5th set rather than this set - and Nicolas hasn't responded to these. Please check with Nicolas whether he's updated to the latest set.
Nicolas, I see you have part 6 in your personal Linaro kprobes branch, but Russell seems to imply that this is missing from a merge you did elsewhere. (I'm unsure where this merge might be.)
All the kprobes patches I've reviewed are in the kprobes branch of
git://git.linaro.org/people/nico/linux. So far I have 31 patches in there. If something is missing please let me know.
Quoted 6 lines
Quoted 1 line
I merged the lot in the Linaro kernel tree as well, that's all.
I'm only concerned because you apparantly replied to v5 of the patch series saying you merged that, and next day Tixy sent v6. So I'm wondering whether you merged v5 without the v6 updates or whether you did merge v6.
I can confirm that Nicolas has merged all six of my patch sets (29 patches total) and the 2 patches from Viktor. Nothing is missing.
Signature · 1 line
Tixy