ARM: rockchip: add dma support

The clock-tree contains clocks that should never get disabled automatically. One example are the base ACLKs, the base supplies for all peripherals.

Therefore add a structure similar to the sunxi clock-tree to protect these special clocks from being disabled.

Signed-off-by Heiko Stuebner <[email protected]>

Tested-by Doug Anderson <[email protected]>

Tested-by Kever Yang <[email protected]>

---

no change since v1

 drivers/clk/rockchip/clk-rk3188.c |  7 +++++++
 drivers/clk/rockchip/clk-rk3288.c |  7 +++++++
 drivers/clk/rockchip/clk.c        | 13 +++++++++++++
 drivers/clk/rockchip/clk.h        |  1 +
 4 files changed, 28 insertions(+)

(quoted diff) +0 -0

b/drivers/clk/rockchip/clk-rk3188.c index a83a6d8..732118e 100644

drivers/clk/rockchip/clk-rk3188.c +7 -0

@@ -599,6 +599,11 @@ static struct rockchip_clk_branch rk3188_clk_branches[]
 __initdata = { GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0,
 RK2928_CLKGATE_CON(8), 13, GFLAGS), };
 
+static const char *rk3188_critical_clocks[] __initconst = {
+	"aclk_cpu",
+	"aclk_peri",
+};
+
 static void __init rk3188_common_clk_init(struct device_node *np)
 {
 	void __iomem *reg_base;

@@ -628,6 +633,8 @@ static void __init rk3188_common_clk_init(struct
 device_node *np) RK3188_GRF_SOC_STATUS);
 	rockchip_clk_register_branches(common_clk_branches,
 				  ARRAY_SIZE(common_clk_branches));
+	rockchip_clk_protect_critical(rk3188_critical_clocks,
+				      ARRAY_SIZE(rk3188_critical_clocks));
 
 	rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
 				  ROCKCHIP_SOFTRST_HIWORD_MASK);

(quoted diff) +0 -0

b/drivers/clk/rockchip/clk-rk3288.c index 0d8c6c5..038b1aa 100644

drivers/clk/rockchip/clk-rk3288.c +7 -0

@@ -680,6 +680,11 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
 __initdata = { GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16),
 3, GFLAGS), };
 
+static const char *rk3288_critical_clocks[] __initconst = {
+	"aclk_cpu",
+	"aclk_peri",
+};
+
 static void __init rk3288_clk_init(struct device_node *np)
 {
 	void __iomem *reg_base;

@@ -710,6 +715,8 @@ static void __init rk3288_clk_init(struct device_node
 *np) RK3288_GRF_SOC_STATUS);
 	rockchip_clk_register_branches(rk3288_clk_branches,
 				  ARRAY_SIZE(rk3288_clk_branches));
+	rockchip_clk_protect_critical(rk3288_critical_clocks,
+				      ARRAY_SIZE(rk3288_critical_clocks));
 
 	rockchip_register_softrst(np, 9, reg_base + RK3288_SOFTRST_CON(0),
 				  ROCKCHIP_SOFTRST_HIWORD_MASK);

drivers/clk/rockchip/clk.c +2 -0

index 278cf9d..9189f1b 100644
@@ -242,3 +242,16 @@ void __init rockchip_clk_register_branches(
 		rockchip_clk_add_lookup(clk, list->id);
 	}
 }
+
+void __init rockchip_clk_protect_critical(const char *clocks[], int

nclocks) +{

drivers/clk/rockchip/clk.c +10 -0

+	int i;
+
+	/* Protect the clocks that needs to stay on */
+	for (i = 0; i < nclocks; i++) {
+		struct clk *clk = __clk_lookup(clocks[i]);
+
+		if (clk)
+			clk_prepare_enable(clk);
+	}
+}

drivers/clk/rockchip/clk.h +1 -0

index 887cbde..2b0bca1 100644
@@ -329,6 +329,7 @@ void rockchip_clk_register_branches(struct
 rockchip_clk_branch *clk_list, unsigned int nr_clk);
 void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
 				unsigned int nr_pll, int grf_lock_offset);
+void rockchip_clk_protect_critical(const char *clocks[], int nclocks);
 
 #define ROCKCHIP_SOFTRST_HIWORD_MASK	BIT(0)

All Rockchip SoCs currently supported use pl330 dma controllers. The first patch introduces the concept of critical clocks, stolen from sunxi, as some core clocks shouldn't be disabled under normal circumstances. The patch is necessary, as the amba bus uses strict clock gating, which without this patch results in the core aclk getting disabled halting the system, before other components are able to probe and maybe claim their clocks.

As the patches have no compile-time dependency on each other, the patchset could be split with the first patch going through the clock tree and the other three going through arm-soc.

changes since v1:
- address comment Sergei Shtylyov and rename nodes to dma-controller
- address comments from Doug Anderson:
- order by address
- rename the controller phandles to reflect the naming in the TRMs On the rk3066/rk3188 there is one diversion in this regard. The clocks really use indices 1 and 2 while the controllers references use 0 and 1 (dmac0 and dmac1), so to prevent to much confusion I used the clock indices for the handles instead of having dmac0 use ACLK_DMAC1
etc.
- address comment from Andreas F?rber adding suffixes of "_s" for the secure and "_ns" for the non-secure variants of the first controller As (nearly) all boards seem to use the secure controller, this becomes the default

Heiko Stuebner (4):
clk: rockchip: protect critical clocks from getting disabled
ARM: rockchip: enable the AMBA bus
ARM: dts: rockchip: add rk3288 dma controllers
ARM: dts: rockchip: add rk3188 dma controllers

 arch/arm/boot/dts/rk3288.dtsi     | 38
++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3xxx.dtsi     |
38 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig   
|  1 +
 drivers/clk/rockchip/clk-rk3188.c |  7 +++++++
 drivers/clk/rockchip/clk-rk3288.c |  7 +++++++
 drivers/clk/rockchip/clk.c        | 13 +++++++++++++
 drivers/clk/rockchip/clk.h        |  1 +
 7 files changed, 105 insertions(+)