perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events

PATCH In review Lin Ming 3 participants 10 messages May 6, 2011 – May 9, 2011

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Lin Ming

author

2011-05-06 07:05 UTC #0 lore raw

PATCH 1/1 perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events

Extend the Intel SandyBridge PMU driver with definitions for generic front-end and back-end stall events.

( As commit 3011203 says, these are only approximations. )

Signed-off-by Lin Ming <[email protected]>

---
 arch/x86/kernel/cpu/perf_event_intel.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

arch/x86/kernel/cpu/perf_event_intel.c +6 -0

index c1ec7a5..61cbf48 100644
@@ -1485,6 +1485,12 @@ static __init int intel_pmu_init(void)
 
 		x86_pmu.event_constraints = intel_snb_event_constraints;
 		x86_pmu.pebs_constraints = intel_snb_pebs_events;
+
+		/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
+		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
+		/* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
+		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
+
 		pr_cont("SandyBridge events, ");
 		break;

Signature · 1 line

1.7.4.4

Ingo Molnar

2011-05-06 07:38 UTC #1 lore raw

Quoted 15 lines · Lin Ming

Extend the Intel SandyBridge PMU driver with definitions for generic front-end and back-end stall events.
( As commit 3011203 says, these are only approximations. )
Signed-off-by Lin Ming <[email protected]>
---
 arch/x86/kernel/cpu/perf_event_intel.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)
arch/x86/kernel/cpu/perf_event_intel.c +0 -0
index c1ec7a5..61cbf48 100644

arch/x86/kernel/cpu/perf_event_intel.c static __init int intel_pmu_init(void) · line 1493

Quoted 9 lines

arch/x86/kernel/cpu/perf_event_intel.c +6 -0

@@ -1485,6 +1485,12 @@ static __init int intel_pmu_init(void)
 
 		x86_pmu.event_constraints = intel_snb_event_constraints;
 		x86_pmu.pebs_constraints = intel_snb_pebs_events;
+
+		/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
+		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
+		/* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
+		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
+

Nice!

Could you check Intel Atom perhaps as well, does it have any useful event to approximate this?

Thanks,

Ingo

Lin Ming

author

2011-05-06 07:42 UTC #2 lore raw

Quoted 29 lines · Ingo Molnar

Quoted 15 lines · Lin Ming
Extend the Intel SandyBridge PMU driver with definitions for generic front-end and back-end stall events.
( As commit 3011203 says, these are only approximations. )
Signed-off-by Lin Ming <[email protected]>
---
 arch/x86/kernel/cpu/perf_event_intel.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)
arch/x86/kernel/cpu/perf_event_intel.c +0 -0
index c1ec7a5..61cbf48 100644
arch/x86/kernel/cpu/perf_event_intel.c static __init int intel_pmu_init(void) · line 1493
Quoted 9 lines
arch/x86/kernel/cpu/perf_event_intel.c +6 -0
@@ -1485,6 +1485,12 @@ static __init int intel_pmu_init(void)
 
 		x86_pmu.event_constraints = intel_snb_event_constraints;
 		x86_pmu.pebs_constraints = intel_snb_pebs_events;
+
+		/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
+		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
+		/* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
+		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
+
Nice!

Quoted 2 lines

Could you check Intel Atom perhaps as well, does it have any useful event to approximate this?

OK, let me check.

Quoted 4 lines

Thanks,
Ingo

Lin Ming

author

2011-05-06 13:44 UTC #3 lore raw

Quoted 30 lines · Lin Ming

Quoted 29 lines · Ingo Molnar
Quoted 15 lines · Lin Ming
Extend the Intel SandyBridge PMU driver with definitions for generic front-end and back-end stall events.
( As commit 3011203 says, these are only approximations. )
Signed-off-by Lin Ming <[email protected]>
---
 arch/x86/kernel/cpu/perf_event_intel.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)
arch/x86/kernel/cpu/perf_event_intel.c +0 -0
index c1ec7a5..61cbf48 100644
arch/x86/kernel/cpu/perf_event_intel.c static __init int intel_pmu_init(void) · line 1493
Quoted 9 lines
arch/x86/kernel/cpu/perf_event_intel.c +6 -0
@@ -1485,6 +1485,12 @@ static __init int intel_pmu_init(void)
 
 		x86_pmu.event_constraints = intel_snb_event_constraints;
 		x86_pmu.pebs_constraints = intel_snb_pebs_events;
+
+		/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
+		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
+		/* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
+		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
+
Nice!

Quoted 4 lines

Quoted 2 lines
Could you check Intel Atom perhaps as well, does it have any useful event to approximate this?
OK, let me check.

Checked, but don't find this kind of event.

Quoted 6 lines

Quoted 5 lines
Thanks,
Ingo

Ingo Molnar

2011-05-06 09:20 UTC #4 lore raw

PATCH 1/1 perf events, x86: Implement Sandybridge last-level cache events

In reply to Ingo Molnar

Btw., there's another missing Intel SandyBridge related perf events feature as well which was not implemented with the Intel offcore bits.

Peter did a raw first cut - entirely untested, see it below. Would you be interested in testing it on Intel SandyBridge hw and sending (the working version) to lkml with your Signed-off-by if the events looks good to you in some real tests (i.e. are counting real LL cache events)?

Thanks,

Ingo

------------------->
Subject: perf events, x86: Implement Sandybridge last-level cache events
From: Peter Zijlstra <[email protected]>
Date: Fri May 06 11:15:30 CEST 2011

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/kernel/cpu/perf_event_intel.c |   68 +++++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)

arch/x86/kernel/cpu/perf_event_intel.c +68 -0

Index: tip/arch/x86/kernel/cpu/perf_event_intel.c
===================================================================
@@ -150,6 +150,72 @@ static u64 intel_pmu_event_map(int hw_ev
 	return intel_perfmon_event_map[hw_event];
 }
 
+/*
+ * Sandy Bridge MSR_OFFCORE_RESPONSE bits;
+ * See IA32 SDM Vol 3B 30.8.5
+ */
+
+#define SNB_DMND_DATA_RD	(1 << 0)
+#define SNB_DMND_RFO		(1 << 1)
+#define SNB_DMND_IFETCH		(1 << 2)
+#define SNB_DMND_WB		(1 << 3)
+#define SNB_PF_DATA_RD		(1 << 4)
+#define SNB_PF_DATA_RFO		(1 << 5)
+#define SNB_PF_IFETCH		(1 << 6)
+#define SNB_PF_LLC_DATA_RD	(1 << 7)
+#define SNB_PF_LLC_RFO		(1 << 8)
+#define SNB_PF_LLC_IFETCH	(1 << 9)
+#define SNB_BUS_LOCKS		(1 << 10)
+#define SNB_STRM_ST		(1 << 11)
+				/* hole */
+#define SNB_OFFCORE_OTHER	(1 << 15)
+#define SNB_COMMON		(1 << 16)
+#define SNB_NO_SUPP		(1 << 17)
+#define SNB_LLC_HITM		(1 << 18)
+#define SNB_LLC_HITE		(1 << 19)
+#define SNB_LLC_HITS		(1 << 20)
+#define SNB_LLC_HITF		(1 << 21)
+				/* hole */
+#define SNB_SNP_NONE		(1 << 31)
+#define SNB_SNP_NOT_NEEDED	(1 << 32)
+#define SNB_SNP_MISS		(1 << 33)
+#define SNB_SNP_NO_FWD		(1 << 34)
+#define SNB_SNP_FWD		(1 << 35)
+#define SNB_HITM		(1 << 36)
+#define SNB_NON_DRAM		(1 << 37)
+
+#define SNB_DMND_READ		(SNB_DMND_DATA_RD)
+#define SNB_DMND_WRITE		(SNB_DMND_RFO|SNB_DMND_WB|SNB_STRM_ST)
+#define SNB_DMND_PREFETCH	(SNB_PF_DATA_RD|SNB_PF_DATA_RFO)
+
+#define SNB_L3_HIT		()
+#define SNB_L3_MISS		()
+#define SNB_L3_ACCESS		(SNB_L3_HIT|SNB_L3_MISS)
+
+#define SNB_ALL_DRAM		()
+#define SNB_REMOTE_DRAM		()
+
+static __initconst const u64 snb_hw_cache_extra_regs
+				[PERF_COUNT_HW_CACHE_MAX]
+				[PERF_COUNT_HW_CACHE_OP_MAX]
+				[PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(LL  ) ] = {
+	[ C(OP_READ) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
+		[ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
+	},
+	[ C(OP_WRITE) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
+		[ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
+	},
+	[ C(OP_PREFETCH) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
+		[ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
+	},
+ }
+};
+
 static __initconst const u64 snb_hw_cache_event_ids
 				[PERF_COUNT_HW_CACHE_MAX]
 				[PERF_COUNT_HW_CACHE_OP_MAX]

@@ -1497,6 +1563,8 @@ static __init int intel_pmu_init(void)
 	case 42: /* SandyBridge */
 		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
+		memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
+		       sizeof(hw_cache_extra_regs));
 
 		intel_pmu_lbr_init_nhm();

Lin Ming

author

2011-05-06 13:47 UTC #5 lore raw

Re: [PATCH] perf events, x86: Implement Sandybridge last-level cache events

Quoted 7 lines · Ingo Molnar

Btw., there's another missing Intel SandyBridge related perf events feature as well which was not implemented with the Intel offcore bits.
Peter did a raw first cut - entirely untested, see it below. Would you be interested in testing it on Intel SandyBridge hw and sending (the working version) to lkml with your Signed-off-by if the events looks good to you in some real tests (i.e. are counting real LL cache events)?

OK, but I can't access SandyBridge machine at home now. Will try it next Monday.

Quoted 4 lines

Thanks,
Ingo

Lin Ming

author

2011-05-09 08:43 UTC #6 lore raw

Re: [PATCH] perf events, x86: Implement Sandybridge last-level cache events

Quoted 11 lines · Lin Ming

Quoted 7 lines · Ingo Molnar
Btw., there's another missing Intel SandyBridge related perf events feature as well which was not implemented with the Intel offcore bits.
Peter did a raw first cut - entirely untested, see it below. Would you be interested in testing it on Intel SandyBridge hw and sending (the working version) to lkml with your Signed-off-by if the events looks good to you in some real tests (i.e. are counting real LL cache events)?
OK, but I can't access SandyBridge machine at home now. Will try it next Monday.

The updated and tested patch at:
http://lkml.org/lkml/2011/5/9/80

Please help to review the definitions for SNB_L3_HIT/_MISS_/ACCESS. I'm really unsure for that.

Thanks,
Lin Ming

Quoted 6 lines

Quoted 5 lines
Thanks,
Ingo

tip-bot for Lin Ming

author

2011-05-06 07:41 UTC #7 lore raw

In reply to Lin Ming

Commit-ID:  e04d1b23f9706186187dcb0be1a752e48dcc540b
Gitweb:     http://git.kernel.org/tip/e04d1b23f9706186187dcb0be1a752e48dcc540b
Author:     Lin Ming <[email protected]>
AuthorDate: Fri, 6 May 2011 07:14:02 +0000
Committer:  Ingo Molnar <[email protected]>
CommitDate: Fri, 6 May 2011 09:37:03 +0200

perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events

Extend the Intel SandyBridge PMU driver with definitions for generic front-end and back-end stall events.

( As commit 3011203 "perf events, x86: Add Westmere stalled-cycles-frontend/backend
events" says, these are only approximations. )

Signed-off-by Lin Ming <[email protected]>

Cc Peter Zijlstra <[email protected]>

Cc Arnaldo Carvalho de Melo <[email protected]>

Cc Frederic Weisbecker <[email protected]>

Cc Mike Galbraith <[email protected]>

Cc Steven Rostedt <[email protected]>

Link http://lkml.kernel.org/r/[email protected] open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/kernel/cpu/perf_event_intel.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

arch/x86/kernel/cpu/perf_event_intel.c +6 -0

index e61539b..7cf2ec5 100644
@@ -1474,6 +1474,12 @@ static __init int intel_pmu_init(void)
 
 		x86_pmu.event_constraints = intel_snb_event_constraints;
 		x86_pmu.pebs_constraints = intel_snb_pebs_events;
+
+		/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
+		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
+		/* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
+		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
+
 		pr_cont("SandyBridge events, ");
 		break;

Steven Rostedt

2011-05-06 15:51 UTC #8 lore raw

Quoted 7 lines · tip-bot for Lin Ming

Commit-ID:  e04d1b23f9706186187dcb0be1a752e48dcc540b
Gitweb:     http://git.kernel.org/tip/e04d1b23f9706186187dcb0be1a752e48dcc540b
Author:     Lin Ming <[email protected]>
AuthorDate: Fri, 6 May 2011 07:14:02 +0000
Committer:  Ingo Molnar <[email protected]>
CommitDate: Fri, 6 May 2011 09:37:03 +0200

Quoted 7 lines

perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events
Extend the Intel SandyBridge PMU driver with definitions for generic front-end and back-end stall events.
( As commit 3011203 "perf events, x86: Add Westmere stalled-cycles-frontend/backend
events" says, these are only approximations. )

I now get the following build error:

In file included from /home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event.c:1449:0:
/home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c: In function 'intel_pmu_init':
/home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c:1479:27: error: 'PERF_COUNT_HW_STALLED_CYCLES_FRONTEND' undeclared (first use in this fun ction)
/home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c:1479:27: note: each undeclared identifier is reported only once for each function it appe ars in
/home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c:1481:27: error: 'PERF_COUNT_HW_STALLED_CYCLES_BACKEND' undeclared (first use in this func tion)

Config can be found here:

http://rostedt.homelinux.com/private/config-sandy-failed

-- Steve

Ingo Molnar

2011-05-06 19:08 UTC #9 lore raw

Quoted 27 lines · Steven Rostedt

Quoted 7 lines · tip-bot for Lin Ming
Commit-ID:  e04d1b23f9706186187dcb0be1a752e48dcc540b
Gitweb:     http://git.kernel.org/tip/e04d1b23f9706186187dcb0be1a752e48dcc540b
Author:     Lin Ming <[email protected]>
AuthorDate: Fri, 6 May 2011 07:14:02 +0000
Committer:  Ingo Molnar <[email protected]>
CommitDate: Fri, 6 May 2011 09:37:03 +0200
Quoted 7 lines
perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events
Extend the Intel SandyBridge PMU driver with definitions for generic front-end and back-end stall events.
( As commit 3011203 "perf events, x86: Add Westmere stalled-cycles-frontend/backend
events" says, these are only approximations. )
I now get the following build error:
In file included from /home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event.c:1449:0:
/home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c: In function 'intel_pmu_init':
/home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c:1479:27: error: 'PERF_COUNT_HW_STALLED_CYCLES_FRONTEND' undeclared (first use in this fun ction)
/home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c:1479:27: note: each undeclared identifier is reported only once for each function it appe ars in
/home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c:1481:27: error: 'PERF_COUNT_HW_STALLED_CYCLES_BACKEND' undeclared (first use in this func tion)

Quoted 3 lines

Config can be found here:
http://rostedt.homelinux.com/private/config-sandy-failed

Ok, could you check latest perf/core (57d524154ffe), does it work better?

Thanks,

Ingo