x86, intel: Output microcode revision v5
Subsystems (3)
PATCH 1/3 x86, intel: Output microcode revision v5
From: Andi Kleen <[email protected]>
I got a request to make it easier to determine the microcode update level on Intel CPUs. This patch adds a new "microcode" field to /proc/cpuinfo.
The microcode level is also outputed on fatal machine checks together with the other CPUID model information.
I removed the respective code from the microcode update driver, it just reads the field from cpu_data. Also when the microcode is updated it fills in the new values too.
I had to add a memory barrier to native_cpuid to prevent it being optimized away when the result is not used.
This turns out to clean up further code which already got this information manually. This is done in followon patches.
v2: Lots of updates based on feedback. v3: Rename cpu_update to microcode. Misc changes from feedback. v4: minor updates. rebased. v5: move MSR read to early_intel_init()
--- arch/x86/include/asm/processor.h | 4 +++- arch/x86/kernel/cpu/intel.c | 9 +++++++++ arch/x86/kernel/cpu/mcheck/mce.c | 9 +++++++-- arch/x86/kernel/cpu/proc.c | 3 ++- arch/x86/kernel/microcode_intel.c | 14 +++++--------- 5 files changed, 26 insertions(+), 13 deletions(-)
arch/x86/include/asm/processor.h +3 -1
@@ -111,6 +111,7 @@ struct cpuinfo_x86 {/* Index into per_cpu list: */ u16 cpu_index;#endif +u32 microcode; } __attribute__((__aligned__(SMP_CACHE_BYTES)));#define X86_VENDOR_INTEL 0
@@ -179,7 +180,8 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, "=b" (*ebx), "=c" (*ecx), "=d" (*edx) - : "0" (*eax), "2" (*ecx)); + : "0" (*eax), "2" (*ecx) + : "memory"); }static inline void load_cr3 (pgd_t *pgdir)
arch/x86/kernel/cpu/intel.c +9 -0
@@ -47,6 +47,15 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) (c->x86 == 0x6 && c->x86_model >= 0x0e))set_cpu_cap (c,X86_FEATURE_CONSTANT_TSC ); +if (c->x86 >=6 && !cpu_has (c,X86_FEATURE_IA64 )) { +unsigned lower_word; + +wrmsr (MSR_IA32_UCODE_REV ,0 ,0 ); +/* The CPUID 1 fills in the MSR as documented in the SDM */ +cpuid_eax (1 ); +rdmsr (MSR_IA32_UCODE_REV , lower_word, c->microcode); + } +/* * Atom erratum AAE44/AAF40/AAG38/AAH41: *
arch/x86/kernel/cpu/mcheck/mce.c +7 -2
@@ -217,8 +217,13 @@ static void print_mce(struct mce *m)pr_cont ("MISC %llx " , m->misc);pr_cont ("\n" ); -pr_emerg (HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n" , - m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid); +/* +* Note this output is parsed by external tools and old fields +* should not be changed. +*/ +pr_emerg (HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %u\n" , + m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, +cpu_data (m->extcpu).microcode);/* * Print out human-readable details about the MCE error,
arch/x86/kernel/cpu/proc.c +2 -1
@@ -85,6 +85,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)seq_printf (m,"stepping\t: %d\n" , c->x86_mask); else seq_printf(m, "stepping\t: unknown\n"); +if (c->microcode) +seq_printf (m,"microcode\t: %u\n" , c->microcode);if (cpu_has (c,X86_FEATURE_TSC )) {unsigned int freq =cpufreq_quick_get (cpu);
@@ -132,7 +134,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)seq_printf (m," [%d]" , i); } } -seq_printf (m,"\n\n" );return 0 ;
arch/x86/kernel/microcode_intel.c +5 -9
@@ -161,12 +161,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) csig->pf =1 << ((val[1 ] >>18 ) &7 ); } -wrmsr (MSR_IA32_UCODE_REV ,0 ,0 ); -/* see notes above for revision 1.07. Apparent chip bug */ -sync_core (); -/* get the current revision from MSR 0x8B */ -rdmsr (MSR_IA32_UCODE_REV , val[0 ], csig->rev); - + csig->rev = c->microcode;pr_info ("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n" , cpu_num, csig->sig, csig->pf, csig->rev);
@@ -299,9 +294,9 @@ static int apply_microcode(int cpu)struct microcode_intel *mc_intel;struct ucode_cpu_info *uci;unsigned int val[2 ]; -int cpu_num; +int cpu_num =raw_smp_processor_id (); +struct cpuinfo_x86 *c = &cpu_data (cpu_num); - cpu_num =raw_smp_processor_id (); uci = ucode_cpu_info + cpu; mc_intel = uci->mc;
@@ -317,7 +312,7 @@ static int apply_microcode(int cpu) (unsigned long) mc_intel->bits >> 16 >> 16);wrmsr (MSR_IA32_UCODE_REV ,0 ,0 ); -/* see notes above for revision 1.07. Apparent chip bug */ +/* As documented in the SDM: Do a CPUID 1 here */ sync_core ();/* get the current revision from MSR 0x8B */
@@ -335,6 +330,7 @@ static int apply_microcode(int cpu) (mc_intel->hdr.date >> 16) & 0xff); uci->cpu_sig.rev = val[1 ]; + c->microcode = val[1 ];return 0 ; }
Signature · 1 line
1.7.4.4
PATCH 2/3 x86, intel: Use cpu_update for Atom errata check
From: Andi Kleen <[email protected]>
Now that the cpu update level is available the Atom PSE errata check can use it directly without reading the MSR again.
--- arch/x86/kernel/cpu/intel.c | 15 ++++----------- 1 files changed, 4 insertions(+), 11 deletions(-)
arch/x86/kernel/cpu/intel.c +4 -11
@@ -64,17 +64,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)* need the microcode to have already been loaded... so if it is * not, recommend a BIOS update and disable large pages. */ -if (c->x86 ==6 && c->x86_model ==0x1c && c->x86_mask <=2 ) { -u32 ucode, junk; - -wrmsr (MSR_IA32_UCODE_REV ,0 ,0 ); -sync_core (); -rdmsr (MSR_IA32_UCODE_REV , junk, ucode); - -if (ucode <0x20e ) { -printk (KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n" ); -clear_cpu_cap (c,X86_FEATURE_PSE ); - } +if (c->x86 ==6 && c->x86_model ==0x1c && c->x86_mask <=2 && + c->microcode <0x20e ) { +printk (KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n" ); +clear_cpu_cap (c,X86_FEATURE_PSE ); }#ifdef CONFIG_X86_64
Signature · 1 line
1.7.4.4
PATCH 3/3 coretemp: Get microcode revision from cpu_data v2
In reply to Andi KleenFrom: Andi Kleen <[email protected]>
Now that the ucode revision is available in cpu_data remove the existing code in coretemp.c to query it manually. Read the ucode revision from cpu_data instead
v2: Fix misplaced variable init. Remove unused variables.
--- drivers/hwmon/coretemp.c | 31 +++++-------------------------- 1 files changed, 5 insertions(+), 26 deletions(-)
drivers/hwmon/coretemp.c +5 -26
@@ -325,15 +325,6 @@ static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)return adjust_tjmax (c, id, dev); } -static void __devinit get_ucode_rev_on_cpu (void *edx) -{ -u32 eax; - -wrmsr (MSR_IA32_UCODE_REV ,0 ,0 ); -sync_core (); -rdmsr (MSR_IA32_UCODE_REV , eax, *(u32 *)edx); -} -static int create_name_attr (struct platform_data *pdata,struct device *dev) {sysfs_attr_init (&pdata->name_attr.attr);
@@ -380,29 +371,17 @@ exit_free:static int __devinit chk_ucode_version (struct platform_device *pdev) {struct cpuinfo_x86 *c = &cpu_data (pdev->id); -int err; -u32 edx;/* * Check if we have problem with errata AE18 of Core processors: * Readings might stop update when processor visited too deep sleep, * fixed for stepping D0 (6EC). */ -if (c->x86_model ==0xe && c->x86_mask <0xc ) { -/* check for microcode update */ - err =smp_call_function_single (pdev->id, get_ucode_rev_on_cpu, - &edx,1 ); -if (err) { -dev_err (&pdev->dev, -"Cannot determine microcode revision of " -"CPU#%u (%d)!\n" , pdev->id, err); -return -ENODEV ; - }else if (edx <0x39 ) { -dev_err (&pdev->dev, -"Errata AE18 not fixed, update BIOS or " -"microcode of the CPU!\n" ); -return -ENODEV ; - } +if (c->x86_model ==0xe && c->x86_mask <0xc && c->microcode <0x39 ) { +dev_err (&pdev->dev, +"Errata AE18 not fixed, update BIOS or " +"microcode of the CPU!\n" ); +return -ENODEV ; }return 0 ; }
Signature · 1 line
1.7.4.4
Andi,
If you want me to apply these patches then they need to be reviewed and signed off by someone else who i trust and who i'm taking patches from.
Please point this person to the previous review iterations of this patch-set which were rather difficult, to make sure everything that was mentioned during review got propagated into the latest version of your patches.
Thanks,
Ingo
Quoted 6 lines · Ingo Molnar
Andi,
If you want me to apply these patches then they need to be reviewed and signed off by someone else who i trust and who i'm taking patches from.
Ingo,
There's noone else to sign off because noone else is writing the patches.
As far as I know all previous review comments that were addressable have been addressed.
You agreed at some point that the patch kit is a good idea,
so I trust that as a responsible maintainer you'll find a way to move them forward.
If any further changes are needed please let me know.
Thanks,
-Andi
Quoted 4 lines · Andi Kleen
Quoted 3 lines · Ingo Molnar
Andi,
Quoted 8 lines
Quoted 3 lines
If you want me to apply these patches then they need to be reviewed and signed off by someone else who i trust and who i'm taking patches from.
Ingo,
There's noone else to sign off because noone else is writing the patches.
The typical way of how such maintainer requests are solved is that you'll have to find someone who is willing and able to work with you on this topic, and who is willing to forward your patches to me or to the other x86 maintainers (or any of the submaintainers we pull from). It's not hard, we get and accept a lot of indirect patches.
Arguably i've already invested more time into this than i should have, this direct approach clearly does not work and i cannot trust you.
Thanks,
Ingo