ASoC: wm8940: Fix setting PLL Output clock division ratio
Subsystems (3)
PATCH 1/3 ASoC: wm8940: Fix setting PLL Output clock division ratio
According to the datasheet:
The PLL Output clock division ratio is controlled by BIT[5:4] of WM8940_GPIO register(08h).
Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.
--- sound/soc/codecs/wm8940.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
sound/soc/codecs/wm8940.c +2 -2
@@ -627,8 +627,8 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai, ret =snd_soc_write (codec,WM8940_CLOCK , reg | (div <<5 ));break ;case WM8940_OPCLKDIV : - reg =snd_soc_read (codec,WM8940_ADDCNTRL ) &0xFFCF ; - ret =snd_soc_write (codec,WM8940_ADDCNTRL , reg | (div <<4 )); + reg =snd_soc_read (codec,WM8940_GPIO ) &0xFFCF ; + ret =snd_soc_write (codec,WM8940_GPIO , reg | (div <<4 ));break ; }return ret;
Signature · 1 line
1.7.5.4
PATCH 2/3 ASoC: wm8940: Fix a typo for the mask of setting WM8940_BCLKDIV
The registers are 16 bits, thus remove an extra F for the mask.
--- sound/soc/codecs/wm8940.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
sound/soc/codecs/wm8940.c +1 -1
@@ -619,7 +619,7 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,switch (div_id) {case WM8940_BCLKDIV : - reg =snd_soc_read (codec,WM8940_CLOCK ) &0xFFEF3 ; + reg =snd_soc_read (codec,WM8940_CLOCK ) &0xFEF3 ; ret =snd_soc_write (codec,WM8940_CLOCK , reg | (div <<2 ));break ;case WM8940_MCLKDIV :
Signature · 1 line
1.7.5.4
Re: [PATCH 2/3] ASoC: wm8940: Fix a typo for the mask of setting WM8940_BCLKDIV
Quoted 14 lines · Axel Lin
The registers are 16 bits, thus remove an extra F for the mask.
Signed-off-by Axel Lin <[email protected]>---
sound/soc/codecs/wm8940.c | 2 +-1 files changed, 1 insertions(+), 1 deletions(-)sound/soc/codecs/wm8940.c +0
-0@@ -619,7 +619,7 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai, switch (div_id) {
Quoted 7 lines
case
WM8940_BCLKDIV:
- reg =snd_soc_read(codec, WM8940_CLOCK)&0xFFEF3;
+ reg =snd_soc_read(codec, WM8940_CLOCK)&0xFEF3; ret =snd_soc_write(codec, WM8940_CLOCK, reg | (div << 2)); break;
caseWM8940_MCLKDIV:
--
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RFC PATCH 3/3 ASoC: wm8940: Do not left shift the div parameter in wm8940_set_dai_clkdiv
In reply to Axel LinJust check with other codec drivers, we do left shit div for the corresponding bits from the caller in all other drivers. I don't find the caller calling wm8940_set_dai_clkdiv now, just make the behavior consistent with other drivers.
--- sound/soc/codecs/wm8940.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
sound/soc/codecs/wm8940.c +3 -3
@@ -620,15 +620,15 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,switch (div_id) {case WM8940_BCLKDIV : reg =snd_soc_read (codec,WM8940_CLOCK ) &0xFEF3 ; - ret =snd_soc_write (codec,WM8940_CLOCK , reg | (div <<2 )); + ret =snd_soc_write (codec,WM8940_CLOCK , reg | div);break ;case WM8940_MCLKDIV : reg =snd_soc_read (codec,WM8940_CLOCK ) &0xFF1F ; - ret =snd_soc_write (codec,WM8940_CLOCK , reg | (div <<5 )); + ret =snd_soc_write (codec,WM8940_CLOCK , reg | div);break ;case WM8940_OPCLKDIV : reg =snd_soc_read (codec,WM8940_GPIO ) &0xFFCF ; - ret =snd_soc_write (codec,WM8940_GPIO , reg | (div <<4 )); + ret =snd_soc_write (codec,WM8940_GPIO , reg | div);break ; }return ret;
Signature · 1 line
1.7.5.4
Re: [RFC][PATCH 3/3] ASoC: wm8940: Do not left shift the div parameter in wm8940_set_dai_clkdiv
Quoted 4 lines · Axel Lin
Just check with other codec drivers, we do left shit div for the corresponding bits from the caller in all other drivers. I don't find the caller calling
wm8940_set_dai_clkdivnow, just make the behavior consistent with other drivers.
The semantics for the clkdivs are entirely defined by the individual drivers - there's no actual standard here and I guess this may break some out of tree machines that people have. If we're going to a cleanup here it'd be better to improve the driver to figure out the divider configurations automatically as far as possible.
Quoted 18 lines · Axel Lin
According to the datasheet:
The PLL Output clock division ratio is controlled by BIT[5:4] ofWM8940_GPIOregister(08h).
Current code read/write theWM8940_ADDCNTRL(07h)register which is wrong.Signed-off-by Axel Lin <[email protected]>---
sound/soc/codecs/wm8940.c | 4 ++--1 files changed, 2 insertions(+), 2 deletions(-)sound/soc/codecs/wm8940.c +0
-0@@ -627,8 +627,8 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai, ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 5)); break;case
WM8940_OPCLKDIV:
Quoted 8 lines
- reg =
snd_soc_read(codec, WM8940_ADDCNTRL)&0xFFCF;
- ret =snd_soc_write(codec, WM8940_ADDCNTRL, reg | (div << 4));
+ reg =snd_soc_read(codec, WM8940_GPIO)&0xFFCF;
+ ret =snd_soc_write(codec, WM8940_GPIO, reg | (div << 4)); break;
}
return ret;
--
Mark Brown
AppliedQuoted 4 lines · Axel Lin
According to the datasheet:
The PLL Output clock division ratio is controlled by BIT[5:4] ofWM8940_GPIOregister(08h).
Current code read/write theWM8940_ADDCNTRL(07h)register which is wrong.
Applied this and patch 2, thanks.